Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.41	93.48	95.24		83.33	90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.41	93.48	95.24		83.33	90.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T6,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T10,T11,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T1,T2	VC_COV_UNR
1	Covered	T10,T11,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T10,T11,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T24
1	0	Covered	T6,T1,T2
1	1	Covered	T10,T11,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T24
0	1	Covered	T40,T148,T133
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T24
0	1	Covered	T24,T38,T40
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T11,T24
1	-	Covered	T24,T38,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T11,T24
DetectSt	168	Covered	T10,T11,T24
IdleSt	163	Covered	T6,T1,T2
StableSt	191	Covered	T10,T11,T24

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T11,T24
DebounceSt->IdleSt	163	Covered	T35,T64,T161
DetectSt->IdleSt	186	Covered	T40,T148,T133
DetectSt->StableSt	191	Covered	T10,T11,T24
IdleSt->DebounceSt	148	Covered	T10,T11,T24
StableSt->IdleSt	206	Covered	T24,T38,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T11,T24
0	1	Covered	T10,T11,T24
0	0	Excluded	T6,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T24
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T11,T24
IdleSt	0	-	-	-	-	-	-	Covered	T6,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T11,T24
DebounceSt	-	0	1	0	-	-	-	Covered	T35,T64,T161
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T11,T24
DetectSt	-	-	-	-	1	-	-	Covered	T40,T148,T133
DetectSt	-	-	-	-	0	1	-	Covered	T10,T11,T24
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T24,T38,T40
StableSt	-	-	-	-	-	-	0	Covered	T10,T11,T24
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9144370	118	0	0
CntIncr_A	9144370	28193	0	0
CntNoWrap_A	9144370	8508337	0	0
DetectStDropOut_A	9144370	4	0	0
DetectedOut_A	9144370	17329	0	0
DetectedPulseOut_A	9144370	51	0	0
DisabledIdleSt_A	9144370	8382254	0	0
DisabledNoDetection_A	9144370	8384498	0	0
EnterDebounceSt_A	9144370	63	0	0
EnterDetectSt_A	9144370	55	0	0
EnterStableSt_A	9144370	51	0	0
PulseIsPulse_A	9144370	51	0	0
StayInStableSt	9144370	17257	0	0
gen_high_level_sva.HighLevelEvent_A	9144370	8510753	0	0
gen_not_sticky_sva.StableStDropOut_A	9144370	28	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	118	0	0
T10	828	2	0	0
T11	889	2	0	0
T24	0	4	0	0
T28	502	0	0	0
T29	502	0	0	0
T34	14374	0	0	0
T35	0	3	0	0
T36	0	2	0	0
T38	0	2	0	0
T40	0	4	0	0
T64	0	3	0	0
T77	527	0	0	0
T86	0	2	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0
T170	0	4	0	0
T187	422	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	28193	0	0
T10	828	38	0	0
T11	889	84	0	0
T24	0	88	0	0
T28	502	0	0	0
T29	502	0	0	0
T34	14374	0	0	0
T35	0	60	0	0
T36	0	24838	0	0
T38	0	52	0	0
T40	0	164	0	0
T64	0	169	0	0
T77	527	0	0	0
T86	0	78	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0
T170	0	82	0	0
T187	422	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8508337	0	0
T1	11840	11427	0	0
T2	15507	15082	0	0
T6	507	106	0	0
T12	443	42	0	0
T13	17092	16645	0	0
T14	494	93	0	0
T15	16466	16065	0	0
T16	515	114	0	0
T17	422	21	0	0
T18	672	271	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	4	0	0
T39	853	0	0	0
T40	34038	1	0	0
T45	594	0	0	0
T46	5566	0	0	0
T47	41907	0	0	0
T133	0	1	0	0
T148	0	1	0	0
T165	0	1	0	0
T182	612	0	0	0
T183	17244	0	0	0
T184	35234	0	0	0
T185	423	0	0	0
T186	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	17329	0	0
T10	828	230	0	0
T11	889	166	0	0
T24	0	166	0	0
T28	502	0	0	0
T29	502	0	0	0
T34	14374	0	0	0
T35	0	19	0	0
T36	0	12912	0	0
T38	0	24	0	0
T40	0	143	0	0
T64	0	418	0	0
T77	527	0	0	0
T86	0	40	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0
T170	0	49	0	0
T187	422	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	51	0	0
T10	828	1	0	0
T11	889	1	0	0
T24	0	2	0	0
T28	502	0	0	0
T29	502	0	0	0
T34	14374	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T64	0	1	0	0
T77	527	0	0	0
T86	0	1	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0
T170	0	2	0	0
T187	422	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8382254	0	0
T1	11840	11427	0	0
T2	15507	15082	0	0
T6	507	106	0	0
T12	443	42	0	0
T13	17092	16645	0	0
T14	494	93	0	0
T15	16466	16065	0	0
T16	515	114	0	0
T17	422	21	0	0
T18	672	271	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8384498	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	63	0	0
T10	828	1	0	0
T11	889	1	0	0
T24	0	2	0	0
T28	502	0	0	0
T29	502	0	0	0
T34	14374	0	0	0
T35	0	2	0	0
T36	0	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T64	0	2	0	0
T77	527	0	0	0
T86	0	1	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0
T170	0	2	0	0
T187	422	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	55	0	0
T10	828	1	0	0
T11	889	1	0	0
T24	0	2	0	0
T28	502	0	0	0
T29	502	0	0	0
T34	14374	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T64	0	1	0	0
T77	527	0	0	0
T86	0	1	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0
T170	0	2	0	0
T187	422	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	51	0	0
T10	828	1	0	0
T11	889	1	0	0
T24	0	2	0	0
T28	502	0	0	0
T29	502	0	0	0
T34	14374	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T64	0	1	0	0
T77	527	0	0	0
T86	0	1	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0
T170	0	2	0	0
T187	422	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	51	0	0
T10	828	1	0	0
T11	889	1	0	0
T24	0	2	0	0
T28	502	0	0	0
T29	502	0	0	0
T34	14374	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T64	0	1	0	0
T77	527	0	0	0
T86	0	1	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0
T170	0	2	0	0
T187	422	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	17257	0	0
T10	828	228	0	0
T11	889	164	0	0
T24	0	163	0	0
T28	502	0	0	0
T29	502	0	0	0
T34	14374	0	0	0
T35	0	18	0	0
T36	0	12911	0	0
T38	0	23	0	0
T40	0	142	0	0
T64	0	417	0	0
T77	527	0	0	0
T86	0	38	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0
T170	0	47	0	0
T187	422	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8510753	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	28	0	0
T24	247596	1	0	0
T25	1657	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T58	16125	0	0	0
T64	0	1	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0
T149	0	1	0	0
T163	0	1	0	0
T170	0	2	0	0
T211	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T6,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T24,T38,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T1,T2	VC_COV_UNR
1	Covered	T24,T38,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T24,T38,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T24,T38
1	0	Covered	T6,T1,T2
1	1	Covered	T24,T38,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T24,T38,T39
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T24,T38,T39
0	1	Covered	T24,T39,T161
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T24,T38,T39
1	-	Covered	T24,T39,T161

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T24,T38,T39
DetectSt	168	Covered	T24,T38,T39
IdleSt	163	Covered	T6,T1,T2
StableSt	191	Covered	T24,T38,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T24,T38,T39
DebounceSt->IdleSt	163	Covered	T163
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T24,T38,T39
IdleSt->DebounceSt	148	Covered	T24,T38,T39
StableSt->IdleSt	206	Covered	T24,T39,T120

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T24,T38,T39
0	1	Covered	T24,T38,T39
0	0	Excluded	T6,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T24,T38,T39
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T24,T38,T39
IdleSt	0	-	-	-	-	-	-	Covered	T6,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T24,T38,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T163
DebounceSt	-	0	0	-	-	-	-	Covered	T24,T38,T39
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T24,T38,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T24,T39,T161
StableSt	-	-	-	-	-	-	0	Covered	T24,T38,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9144370	71	0	0
CntIncr_A	9144370	26612	0	0
CntNoWrap_A	9144370	8508384	0	0
DetectStDropOut_A	9144370	0	0	0
DetectedOut_A	9144370	2240	0	0
DetectedPulseOut_A	9144370	35	0	0
DisabledIdleSt_A	9144370	8408775	0	0
DisabledNoDetection_A	9144370	8411029	0	0
EnterDebounceSt_A	9144370	36	0	0
EnterDetectSt_A	9144370	35	0	0
EnterStableSt_A	9144370	35	0	0
PulseIsPulse_A	9144370	35	0	0
StayInStableSt	9144370	2186	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9144370	5968	0	0
gen_low_level_sva.LowLevelEvent_A	9144370	8510753	0	0
gen_not_sticky_sva.StableStDropOut_A	9144370	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	71	0	0
T24	247596	4	0	0
T25	1657	0	0	0
T36	0	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T58	16125	0	0	0
T64	0	2	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0
T120	0	4	0	0
T123	0	2	0	0
T148	0	2	0	0
T160	0	2	0	0
T163	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	26612	0	0
T24	247596	103	0	0
T25	1657	0	0	0
T36	0	24838	0	0
T38	0	52	0	0
T39	0	49	0	0
T58	16125	0	0	0
T64	0	78	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0
T120	0	112	0	0
T123	0	50	0	0
T148	0	22	0	0
T160	0	21	0	0
T163	0	71	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8508384	0	0
T1	11840	11427	0	0
T2	15507	15082	0	0
T6	507	106	0	0
T12	443	42	0	0
T13	17092	16645	0	0
T14	494	93	0	0
T15	16466	16065	0	0
T16	515	114	0	0
T17	422	21	0	0
T18	672	271	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	2240	0	0
T24	247596	257	0	0
T25	1657	0	0	0
T36	0	42	0	0
T38	0	43	0	0
T39	0	7	0	0
T58	16125	0	0	0
T64	0	52	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0
T120	0	80	0	0
T123	0	41	0	0
T148	0	126	0	0
T160	0	38	0	0
T161	0	191	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	35	0	0
T24	247596	2	0	0
T25	1657	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T58	16125	0	0	0
T64	0	1	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0
T120	0	2	0	0
T123	0	1	0	0
T148	0	1	0	0
T160	0	1	0	0
T161	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8408775	0	0
T1	11840	11427	0	0
T2	15507	15082	0	0
T6	507	106	0	0
T12	443	42	0	0
T13	17092	16645	0	0
T14	494	93	0	0
T15	16466	16065	0	0
T16	515	114	0	0
T17	422	21	0	0
T18	672	271	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8411029	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	36	0	0
T24	247596	2	0	0
T25	1657	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T58	16125	0	0	0
T64	0	1	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0
T120	0	2	0	0
T123	0	1	0	0
T148	0	1	0	0
T160	0	1	0	0
T163	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	35	0	0
T24	247596	2	0	0
T25	1657	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T58	16125	0	0	0
T64	0	1	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0
T120	0	2	0	0
T123	0	1	0	0
T148	0	1	0	0
T160	0	1	0	0
T161	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	35	0	0
T24	247596	2	0	0
T25	1657	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T58	16125	0	0	0
T64	0	1	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0
T120	0	2	0	0
T123	0	1	0	0
T148	0	1	0	0
T160	0	1	0	0
T161	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	35	0	0
T24	247596	2	0	0
T25	1657	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T58	16125	0	0	0
T64	0	1	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0
T120	0	2	0	0
T123	0	1	0	0
T148	0	1	0	0
T160	0	1	0	0
T161	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	2186	0	0
T24	247596	255	0	0
T25	1657	0	0	0
T36	0	40	0	0
T38	0	41	0	0
T39	0	6	0	0
T58	16125	0	0	0
T64	0	50	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0
T120	0	76	0	0
T123	0	39	0	0
T148	0	124	0	0
T160	0	36	0	0
T161	0	186	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	5968	0	0
T1	11840	23	0	0
T2	15507	32	0	0
T3	0	1	0	0
T4	0	7	0	0
T6	507	4	0	0
T12	443	5	0	0
T13	17092	14	0	0
T14	494	9	0	0
T15	16466	22	0	0
T16	515	0	0	0
T17	422	1	0	0
T18	672	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8510753	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	14	0	0
T24	247596	2	0	0
T25	1657	0	0	0
T39	0	1	0	0
T58	16125	0	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0
T154	0	1	0	0
T155	0	1	0	0
T161	0	3	0	0
T167	0	1	0	0
T181	0	1	0	0
T199	0	1	0	0
T212	0	1	0	0
T213	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T6,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T10,T11,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T1,T2	VC_COV_UNR
1	Covered	T10,T11,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T10,T11,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T24
1	0	Covered	T6,T1,T2
1	1	Covered	T10,T11,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T24
0	1	Covered	T36,T64,T148
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T24
0	1	Covered	T10,T24,T80
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T11,T24
1	-	Covered	T10,T24,T80

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T11,T24
DetectSt	168	Covered	T10,T11,T24
IdleSt	163	Covered	T6,T1,T2
StableSt	191	Covered	T10,T11,T24

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T11,T24
DebounceSt->IdleSt	163	Covered	T148,T159,T166
DetectSt->IdleSt	186	Covered	T36,T64,T148
DetectSt->StableSt	191	Covered	T10,T11,T24
IdleSt->DebounceSt	148	Covered	T10,T11,T24
StableSt->IdleSt	206	Covered	T10,T24,T80

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T11,T24
0	1	Covered	T10,T11,T24
0	0	Excluded	T6,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T24
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T11,T24
IdleSt	0	-	-	-	-	-	-	Covered	T6,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T11,T24
DebounceSt	-	0	1	0	-	-	-	Covered	T148,T159,T155
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T11,T24
DetectSt	-	-	-	-	1	-	-	Covered	T36,T64,T148
DetectSt	-	-	-	-	0	1	-	Covered	T10,T11,T24
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T24,T80
StableSt	-	-	-	-	-	-	0	Covered	T10,T11,T24
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9144370	149	0	0
CntIncr_A	9144370	37597	0	0
CntNoWrap_A	9144370	8508306	0	0
DetectStDropOut_A	9144370	6	0	0
DetectedOut_A	9144370	18935	0	0
DetectedPulseOut_A	9144370	66	0	0
DisabledIdleSt_A	9144370	8402274	0	0
DisabledNoDetection_A	9144370	8404508	0	0
EnterDebounceSt_A	9144370	78	0	0
EnterDetectSt_A	9144370	72	0	0
EnterStableSt_A	9144370	66	0	0
PulseIsPulse_A	9144370	66	0	0
StayInStableSt	9144370	18843	0	0
gen_high_level_sva.HighLevelEvent_A	9144370	8510753	0	0
gen_not_sticky_sva.StableStDropOut_A	9144370	38	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	149	0	0
T10	828	4	0	0
T11	889	2	0	0
T24	0	4	0	0
T28	502	0	0	0
T29	502	0	0	0
T34	14374	0	0	0
T36	0	6	0	0
T37	0	2	0	0
T40	0	2	0	0
T41	0	2	0	0
T77	527	0	0	0
T80	0	2	0	0
T88	0	2	0	0
T120	0	2	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0
T187	422	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	37597	0	0
T10	828	76	0	0
T11	889	84	0	0
T24	0	118	0	0
T28	502	0	0	0
T29	502	0	0	0
T34	14374	0	0	0
T36	0	24970	0	0
T37	0	81	0	0
T40	0	82	0	0
T41	0	38	0	0
T77	527	0	0	0
T80	0	43	0	0
T88	0	92	0	0
T120	0	66	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0
T187	422	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8508306	0	0
T1	11840	11427	0	0
T2	15507	15082	0	0
T6	507	106	0	0
T12	443	42	0	0
T13	17092	16645	0	0
T14	494	93	0	0
T15	16466	16065	0	0
T16	515	114	0	0
T17	422	21	0	0
T18	672	271	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	6	0	0
T36	121038	1	0	0
T37	625	0	0	0
T64	173148	1	0	0
T98	4866	0	0	0
T133	0	1	0	0
T148	0	1	0	0
T190	0	1	0	0
T212	0	1	0	0
T214	747	0	0	0
T215	503	0	0	0
T216	672	0	0	0
T217	503	0	0	0
T218	490	0	0	0
T219	421	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	18935	0	0
T10	828	108	0	0
T11	889	38	0	0
T24	0	189	0	0
T28	502	0	0	0
T29	502	0	0	0
T34	14374	0	0	0
T36	0	13158	0	0
T37	0	134	0	0
T40	0	142	0	0
T41	0	38	0	0
T77	527	0	0	0
T80	0	116	0	0
T88	0	141	0	0
T120	0	142	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0
T187	422	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	66	0	0
T10	828	2	0	0
T11	889	1	0	0
T24	0	2	0	0
T28	502	0	0	0
T29	502	0	0	0
T34	14374	0	0	0
T36	0	2	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T77	527	0	0	0
T80	0	1	0	0
T88	0	1	0	0
T120	0	1	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0
T187	422	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8402274	0	0
T1	11840	11427	0	0
T2	15507	15082	0	0
T6	507	106	0	0
T12	443	42	0	0
T13	17092	16645	0	0
T14	494	93	0	0
T15	16466	16065	0	0
T16	515	114	0	0
T17	422	21	0	0
T18	672	271	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8404508	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	78	0	0
T10	828	2	0	0
T11	889	1	0	0
T24	0	2	0	0
T28	502	0	0	0
T29	502	0	0	0
T34	14374	0	0	0
T36	0	3	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T77	527	0	0	0
T80	0	1	0	0
T88	0	1	0	0
T120	0	1	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0
T187	422	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	72	0	0
T10	828	2	0	0
T11	889	1	0	0
T24	0	2	0	0
T28	502	0	0	0
T29	502	0	0	0
T34	14374	0	0	0
T36	0	3	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T77	527	0	0	0
T80	0	1	0	0
T88	0	1	0	0
T120	0	1	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0
T187	422	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	66	0	0
T10	828	2	0	0
T11	889	1	0	0
T24	0	2	0	0
T28	502	0	0	0
T29	502	0	0	0
T34	14374	0	0	0
T36	0	2	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T77	527	0	0	0
T80	0	1	0	0
T88	0	1	0	0
T120	0	1	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0
T187	422	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	66	0	0
T10	828	2	0	0
T11	889	1	0	0
T24	0	2	0	0
T28	502	0	0	0
T29	502	0	0	0
T34	14374	0	0	0
T36	0	2	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T77	527	0	0	0
T80	0	1	0	0
T88	0	1	0	0
T120	0	1	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0
T187	422	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	18843	0	0
T10	828	106	0	0
T11	889	36	0	0
T24	0	187	0	0
T28	502	0	0	0
T29	502	0	0	0
T34	14374	0	0	0
T36	0	13156	0	0
T37	0	132	0	0
T40	0	141	0	0
T41	0	36	0	0
T77	527	0	0	0
T80	0	115	0	0
T88	0	139	0	0
T120	0	140	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0
T187	422	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8510753	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	38	0	0
T10	828	2	0	0
T11	889	0	0	0
T24	0	2	0	0
T28	502	0	0	0
T29	502	0	0	0
T34	14374	0	0	0
T36	0	2	0	0
T40	0	1	0	0
T64	0	4	0	0
T77	527	0	0	0
T80	0	1	0	0
T84	0	1	0	0
T149	0	1	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0
T163	0	1	0	0
T170	0	1	0	0
T187	422	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T6,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T10,T24,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T1,T2	VC_COV_UNR
1	Covered	T10,T24,T30

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T10,T24,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T11
1	0	Covered	T6,T1,T2
1	1	Covered	T10,T24,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T24,T30
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T24,T30
0	1	Covered	T10,T24,T35
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T24,T30
1	-	Covered	T10,T24,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T24,T30
DetectSt	168	Covered	T10,T24,T30
IdleSt	163	Covered	T6,T1,T2
StableSt	191	Covered	T10,T24,T30

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T24,T30
DebounceSt->IdleSt	163	Covered	T163,T200
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T10,T24,T30
IdleSt->DebounceSt	148	Covered	T10,T24,T30
StableSt->IdleSt	206	Covered	T10,T24,T30

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T24,T30
0	1	Covered	T10,T24,T30
0	0	Excluded	T6,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T24,T30
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T24,T30
IdleSt	0	-	-	-	-	-	-	Covered	T6,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T24,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T163
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T24,T30
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T10,T24,T30
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T24,T35
StableSt	-	-	-	-	-	-	0	Covered	T10,T24,T30
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9144370	105	0	0
CntIncr_A	9144370	33920	0	0
CntNoWrap_A	9144370	8508350	0	0
DetectStDropOut_A	9144370	0	0	0
DetectedOut_A	9144370	3160	0	0
DetectedPulseOut_A	9144370	52	0	0
DisabledIdleSt_A	9144370	8403344	0	0
DisabledNoDetection_A	9144370	8405584	0	0
EnterDebounceSt_A	9144370	54	0	0
EnterDetectSt_A	9144370	52	0	0
EnterStableSt_A	9144370	52	0	0
PulseIsPulse_A	9144370	52	0	0
StayInStableSt	9144370	3074	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9144370	6040	0	0
gen_low_level_sva.LowLevelEvent_A	9144370	8510753	0	0
gen_not_sticky_sva.StableStDropOut_A	9144370	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	105	0	0
T10	828	4	0	0
T11	889	0	0	0
T24	0	4	0	0
T28	502	0	0	0
T29	502	0	0	0
T30	0	2	0	0
T34	14374	0	0	0
T35	0	2	0	0
T36	0	6	0	0
T40	0	2	0	0
T64	0	10	0	0
T77	527	0	0	0
T86	0	2	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0
T162	0	2	0	0
T170	0	2	0	0
T187	422	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	33920	0	0
T10	828	76	0	0
T11	889	0	0	0
T24	0	118	0	0
T28	502	0	0	0
T29	502	0	0	0
T30	0	48	0	0
T34	14374	0	0	0
T35	0	30	0	0
T36	0	24970	0	0
T40	0	82	0	0
T64	0	289	0	0
T77	527	0	0	0
T86	0	78	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0
T162	0	23	0	0
T170	0	41	0	0
T187	422	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8508350	0	0
T1	11840	11427	0	0
T2	15507	15082	0	0
T6	507	106	0	0
T12	443	42	0	0
T13	17092	16645	0	0
T14	494	93	0	0
T15	16466	16065	0	0
T16	515	114	0	0
T17	422	21	0	0
T18	672	271	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	3160	0	0
T10	828	87	0	0
T11	889	0	0	0
T24	0	179	0	0
T28	502	0	0	0
T29	502	0	0	0
T30	0	49	0	0
T34	14374	0	0	0
T35	0	91	0	0
T36	0	128	0	0
T40	0	127	0	0
T64	0	240	0	0
T77	527	0	0	0
T86	0	40	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0
T162	0	42	0	0
T170	0	44	0	0
T187	422	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	52	0	0
T10	828	2	0	0
T11	889	0	0	0
T24	0	2	0	0
T28	502	0	0	0
T29	502	0	0	0
T30	0	1	0	0
T34	14374	0	0	0
T35	0	1	0	0
T36	0	3	0	0
T40	0	1	0	0
T64	0	5	0	0
T77	527	0	0	0
T86	0	1	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0
T162	0	1	0	0
T170	0	1	0	0
T187	422	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8403344	0	0
T1	11840	11427	0	0
T2	15507	15082	0	0
T6	507	106	0	0
T12	443	42	0	0
T13	17092	16645	0	0
T14	494	93	0	0
T15	16466	16065	0	0
T16	515	114	0	0
T17	422	21	0	0
T18	672	271	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8405584	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	54	0	0
T10	828	2	0	0
T11	889	0	0	0
T24	0	2	0	0
T28	502	0	0	0
T29	502	0	0	0
T30	0	1	0	0
T34	14374	0	0	0
T35	0	1	0	0
T36	0	3	0	0
T40	0	1	0	0
T64	0	5	0	0
T77	527	0	0	0
T86	0	1	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0
T162	0	1	0	0
T170	0	1	0	0
T187	422	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	52	0	0
T10	828	2	0	0
T11	889	0	0	0
T24	0	2	0	0
T28	502	0	0	0
T29	502	0	0	0
T30	0	1	0	0
T34	14374	0	0	0
T35	0	1	0	0
T36	0	3	0	0
T40	0	1	0	0
T64	0	5	0	0
T77	527	0	0	0
T86	0	1	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0
T162	0	1	0	0
T170	0	1	0	0
T187	422	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	52	0	0
T10	828	2	0	0
T11	889	0	0	0
T24	0	2	0	0
T28	502	0	0	0
T29	502	0	0	0
T30	0	1	0	0
T34	14374	0	0	0
T35	0	1	0	0
T36	0	3	0	0
T40	0	1	0	0
T64	0	5	0	0
T77	527	0	0	0
T86	0	1	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0
T162	0	1	0	0
T170	0	1	0	0
T187	422	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	52	0	0
T10	828	2	0	0
T11	889	0	0	0
T24	0	2	0	0
T28	502	0	0	0
T29	502	0	0	0
T30	0	1	0	0
T34	14374	0	0	0
T35	0	1	0	0
T36	0	3	0	0
T40	0	1	0	0
T64	0	5	0	0
T77	527	0	0	0
T86	0	1	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0
T162	0	1	0	0
T170	0	1	0	0
T187	422	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	3074	0	0
T10	828	84	0	0
T11	889	0	0	0
T24	0	176	0	0
T28	502	0	0	0
T29	502	0	0	0
T30	0	47	0	0
T34	14374	0	0	0
T35	0	90	0	0
T36	0	123	0	0
T40	0	125	0	0
T64	0	232	0	0
T77	527	0	0	0
T86	0	38	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0
T162	0	40	0	0
T170	0	42	0	0
T187	422	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	6040	0	0
T1	11840	31	0	0
T2	15507	29	0	0
T4	0	10	0	0
T5	0	33	0	0
T6	507	5	0	0
T12	443	4	0	0
T13	17092	12	0	0
T14	494	7	0	0
T15	16466	18	0	0
T16	515	0	0	0
T17	422	3	0	0
T18	672	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8510753	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	16	0	0
T10	828	1	0	0
T11	889	0	0	0
T24	0	1	0	0
T28	502	0	0	0
T29	502	0	0	0
T34	14374	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T64	0	2	0	0
T77	527	0	0	0
T133	0	1	0	0
T148	0	1	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0
T159	0	1	0	0
T161	0	2	0	0
T177	0	1	0	0
T187	422	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T6,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T3,T7,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T1,T2	VC_COV_UNR
1	Covered	T3,T7,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T3,T7,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T11
1	0	Covered	T6,T1,T2
1	1	Covered	T3,T7,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T11
0	1	Covered	T24
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T11
0	1	Covered	T7,T11,T37
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T7,T11
1	-	Covered	T7,T11,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T7,T11
DetectSt	168	Covered	T3,T7,T11
IdleSt	163	Covered	T6,T1,T2
StableSt	191	Covered	T3,T7,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T7,T11
DebounceSt->IdleSt	163	Covered	T64,T169,T189
DetectSt->IdleSt	186	Covered	T24
DetectSt->StableSt	191	Covered	T3,T7,T11
IdleSt->DebounceSt	148	Covered	T3,T7,T11
StableSt->IdleSt	206	Covered	T7,T11,T24

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T7,T11
0	1	Covered	T3,T7,T11
0	0	Excluded	T6,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T11
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T7,T11
IdleSt	0	-	-	-	-	-	-	Covered	T6,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T7,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T64,T169,T189
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T7,T11
DetectSt	-	-	-	-	1	-	-	Covered	T24
DetectSt	-	-	-	-	0	1	-	Covered	T3,T7,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T11,T37
StableSt	-	-	-	-	-	-	0	Covered	T3,T7,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9144370	116	0	0
CntIncr_A	9144370	32477	0	0
CntNoWrap_A	9144370	8508339	0	0
DetectStDropOut_A	9144370	1	0	0
DetectedOut_A	9144370	38129	0	0
DetectedPulseOut_A	9144370	55	0	0
DisabledIdleSt_A	9144370	8423234	0	0
DisabledNoDetection_A	9144370	8425482	0	0
EnterDebounceSt_A	9144370	60	0	0
EnterDetectSt_A	9144370	56	0	0
EnterStableSt_A	9144370	55	0	0
PulseIsPulse_A	9144370	55	0	0
StayInStableSt	9144370	38040	0	0
gen_high_level_sva.HighLevelEvent_A	9144370	8510753	0	0
gen_not_sticky_sva.StableStDropOut_A	9144370	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	116	0	0
T3	625	2	0	0
T4	22800	0	0	0
T5	16581	0	0	0
T7	649	4	0	0
T11	0	2	0	0
T24	0	6	0	0
T37	0	2	0	0
T50	800	0	0	0
T51	422	0	0	0
T52	1217	0	0	0
T53	705	0	0	0
T54	402	0	0	0
T55	434	0	0	0
T64	0	5	0	0
T86	0	2	0	0
T149	0	2	0	0
T162	0	2	0	0
T163	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	32477	0	0
T3	625	88	0	0
T4	22800	0	0	0
T5	16581	0	0	0
T7	649	60	0	0
T11	0	84	0	0
T24	0	168	0	0
T37	0	81	0	0
T50	800	0	0	0
T51	422	0	0	0
T52	1217	0	0	0
T53	705	0	0	0
T54	402	0	0	0
T55	434	0	0	0
T64	0	177	0	0
T86	0	78	0	0
T149	0	48	0	0
T162	0	23	0	0
T163	0	71	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8508339	0	0
T1	11840	11427	0	0
T2	15507	15082	0	0
T6	507	106	0	0
T12	443	42	0	0
T13	17092	16645	0	0
T14	494	93	0	0
T15	16466	16065	0	0
T16	515	114	0	0
T17	422	21	0	0
T18	672	271	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	1	0	0
T24	247596	1	0	0
T25	1657	0	0	0
T58	16125	0	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	38129	0	0
T3	625	128	0	0
T4	22800	0	0	0
T5	16581	0	0	0
T7	649	147	0	0
T11	0	272	0	0
T24	0	457	0	0
T37	0	13	0	0
T50	800	0	0	0
T51	422	0	0	0
T52	1217	0	0	0
T53	705	0	0	0
T54	402	0	0	0
T55	434	0	0	0
T64	0	355	0	0
T86	0	52	0	0
T149	0	322	0	0
T162	0	43	0	0
T163	0	95	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	55	0	0
T3	625	1	0	0
T4	22800	0	0	0
T5	16581	0	0	0
T7	649	2	0	0
T11	0	1	0	0
T24	0	2	0	0
T37	0	1	0	0
T50	800	0	0	0
T51	422	0	0	0
T52	1217	0	0	0
T53	705	0	0	0
T54	402	0	0	0
T55	434	0	0	0
T64	0	2	0	0
T86	0	1	0	0
T149	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8423234	0	0
T1	11840	11427	0	0
T2	15507	15082	0	0
T6	507	106	0	0
T12	443	42	0	0
T13	17092	16645	0	0
T14	494	93	0	0
T15	16466	16065	0	0
T16	515	114	0	0
T17	422	21	0	0
T18	672	271	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8425482	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	60	0	0
T3	625	1	0	0
T4	22800	0	0	0
T5	16581	0	0	0
T7	649	2	0	0
T11	0	1	0	0
T24	0	3	0	0
T37	0	1	0	0
T50	800	0	0	0
T51	422	0	0	0
T52	1217	0	0	0
T53	705	0	0	0
T54	402	0	0	0
T55	434	0	0	0
T64	0	3	0	0
T86	0	1	0	0
T149	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	56	0	0
T3	625	1	0	0
T4	22800	0	0	0
T5	16581	0	0	0
T7	649	2	0	0
T11	0	1	0	0
T24	0	3	0	0
T37	0	1	0	0
T50	800	0	0	0
T51	422	0	0	0
T52	1217	0	0	0
T53	705	0	0	0
T54	402	0	0	0
T55	434	0	0	0
T64	0	2	0	0
T86	0	1	0	0
T149	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	55	0	0
T3	625	1	0	0
T4	22800	0	0	0
T5	16581	0	0	0
T7	649	2	0	0
T11	0	1	0	0
T24	0	2	0	0
T37	0	1	0	0
T50	800	0	0	0
T51	422	0	0	0
T52	1217	0	0	0
T53	705	0	0	0
T54	402	0	0	0
T55	434	0	0	0
T64	0	2	0	0
T86	0	1	0	0
T149	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	55	0	0
T3	625	1	0	0
T4	22800	0	0	0
T5	16581	0	0	0
T7	649	2	0	0
T11	0	1	0	0
T24	0	2	0	0
T37	0	1	0	0
T50	800	0	0	0
T51	422	0	0	0
T52	1217	0	0	0
T53	705	0	0	0
T54	402	0	0	0
T55	434	0	0	0
T64	0	2	0	0
T86	0	1	0	0
T149	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	38040	0	0
T3	625	126	0	0
T4	22800	0	0	0
T5	16581	0	0	0
T7	649	144	0	0
T11	0	271	0	0
T24	0	453	0	0
T37	0	12	0	0
T50	800	0	0	0
T51	422	0	0	0
T52	1217	0	0	0
T53	705	0	0	0
T54	402	0	0	0
T55	434	0	0	0
T64	0	352	0	0
T86	0	50	0	0
T149	0	320	0	0
T162	0	41	0	0
T163	0	93	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8510753	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	19	0	0
T7	649	1	0	0
T8	26285	0	0	0
T9	20704	0	0	0
T10	828	0	0	0
T11	0	1	0	0
T27	491	0	0	0
T28	502	0	0	0
T37	0	1	0	0
T55	434	0	0	0
T64	0	1	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0
T156	0	1	0	0
T161	0	2	0	0
T166	0	1	0	0
T167	0	1	0	0
T176	0	2	0	0
T199	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T6,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T7,T35,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T1,T2	VC_COV_UNR
1	Covered	T7,T35,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T7,T35,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T10,T24
1	0	Covered	T6,T1,T2
1	1	Covered	T7,T35,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T37
0	1	Covered	T7
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T37
0	1	Covered	T35,T36,T64
1	0	Covered	T56,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T35,T36,T37
1	-	Covered	T35,T36,T64

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T35,T36
DetectSt	168	Covered	T7,T35,T36
IdleSt	163	Covered	T6,T1,T2
StableSt	191	Covered	T35,T36,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T35,T36
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T35,T36,T37
IdleSt->DebounceSt	148	Covered	T7,T35,T36
StableSt->IdleSt	206	Covered	T35,T36,T64

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T35,T36
0	1	Covered	T7,T35,T36
0	0	Excluded	T6,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T35,T36
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T35,T36
IdleSt	0	-	-	-	-	-	-	Covered	T6,T1,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T35,T36
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T35,T36
DetectSt	-	-	-	-	1	-	-	Covered	T7
DetectSt	-	-	-	-	0	1	-	Covered	T35,T36,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T35,T36,T64
StableSt	-	-	-	-	-	-	0	Covered	T35,T36,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9144370	66	0	0
CntIncr_A	9144370	1857	0	0
CntNoWrap_A	9144370	8508389	0	0
DetectStDropOut_A	9144370	1	0	0
DetectedOut_A	9144370	2661	0	0
DetectedPulseOut_A	9144370	32	0	0
DisabledIdleSt_A	9144370	8357275	0	0
DisabledNoDetection_A	9144370	8359514	0	0
EnterDebounceSt_A	9144370	33	0	0
EnterDetectSt_A	9144370	33	0	0
EnterStableSt_A	9144370	32	0	0
PulseIsPulse_A	9144370	32	0	0
StayInStableSt	9144370	2612	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9144370	6739	0	0
gen_low_level_sva.LowLevelEvent_A	9144370	8510753	0	0
gen_not_sticky_sva.StableStDropOut_A	9144370	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	66	0	0
T7	649	2	0	0
T8	26285	0	0	0
T9	20704	0	0	0
T10	828	0	0	0
T27	491	0	0	0
T28	502	0	0	0
T35	0	2	0	0
T36	0	4	0	0
T37	0	2	0	0
T55	434	0	0	0
T64	0	8	0	0
T123	0	2	0	0
T148	0	2	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0
T153	0	2	0	0
T170	0	2	0	0
T199	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	1857	0	0
T7	649	30	0	0
T8	26285	0	0	0
T9	20704	0	0	0
T10	828	0	0	0
T27	491	0	0	0
T28	502	0	0	0
T35	0	30	0	0
T36	0	132	0	0
T37	0	81	0	0
T55	434	0	0	0
T64	0	338	0	0
T123	0	50	0	0
T148	0	22	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0
T153	0	79	0	0
T170	0	41	0	0
T199	0	83	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8508389	0	0
T1	11840	11427	0	0
T2	15507	15082	0	0
T6	507	106	0	0
T12	443	42	0	0
T13	17092	16645	0	0
T14	494	93	0	0
T15	16466	16065	0	0
T16	515	114	0	0
T17	422	21	0	0
T18	672	271	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	1	0	0
T7	649	1	0	0
T8	26285	0	0	0
T9	20704	0	0	0
T10	828	0	0	0
T27	491	0	0	0
T28	502	0	0	0
T55	434	0	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	2661	0	0
T35	722	188	0	0
T36	121038	213	0	0
T37	625	40	0	0
T64	0	270	0	0
T98	4866	0	0	0
T123	0	40	0	0
T148	0	126	0	0
T153	0	120	0	0
T170	0	44	0	0
T181	0	409	0	0
T199	0	207	0	0
T214	747	0	0	0
T215	503	0	0	0
T216	672	0	0	0
T217	503	0	0	0
T218	490	0	0	0
T219	421	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	32	0	0
T35	722	1	0	0
T36	121038	2	0	0
T37	625	1	0	0
T64	0	4	0	0
T98	4866	0	0	0
T123	0	1	0	0
T148	0	1	0	0
T153	0	1	0	0
T170	0	1	0	0
T181	0	1	0	0
T199	0	1	0	0
T214	747	0	0	0
T215	503	0	0	0
T216	672	0	0	0
T217	503	0	0	0
T218	490	0	0	0
T219	421	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8357275	0	0
T1	11840	11427	0	0
T2	15507	15082	0	0
T6	507	106	0	0
T12	443	42	0	0
T13	17092	16645	0	0
T14	494	93	0	0
T15	16466	16065	0	0
T16	515	114	0	0
T17	422	21	0	0
T18	672	271	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8359514	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	33	0	0
T7	649	1	0	0
T8	26285	0	0	0
T9	20704	0	0	0
T10	828	0	0	0
T27	491	0	0	0
T28	502	0	0	0
T35	0	1	0	0
T36	0	2	0	0
T37	0	1	0	0
T55	434	0	0	0
T64	0	4	0	0
T123	0	1	0	0
T148	0	1	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0
T153	0	1	0	0
T170	0	1	0	0
T199	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	33	0	0
T7	649	1	0	0
T8	26285	0	0	0
T9	20704	0	0	0
T10	828	0	0	0
T27	491	0	0	0
T28	502	0	0	0
T35	0	1	0	0
T36	0	2	0	0
T37	0	1	0	0
T55	434	0	0	0
T64	0	4	0	0
T123	0	1	0	0
T148	0	1	0	0
T150	408	0	0	0
T151	639	0	0	0
T152	422	0	0	0
T153	0	1	0	0
T170	0	1	0	0
T199	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	32	0	0
T35	722	1	0	0
T36	121038	2	0	0
T37	625	1	0	0
T64	0	4	0	0
T98	4866	0	0	0
T123	0	1	0	0
T148	0	1	0	0
T153	0	1	0	0
T170	0	1	0	0
T181	0	1	0	0
T199	0	1	0	0
T214	747	0	0	0
T215	503	0	0	0
T216	672	0	0	0
T217	503	0	0	0
T218	490	0	0	0
T219	421	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	32	0	0
T35	722	1	0	0
T36	121038	2	0	0
T37	625	1	0	0
T64	0	4	0	0
T98	4866	0	0	0
T123	0	1	0	0
T148	0	1	0	0
T153	0	1	0	0
T170	0	1	0	0
T181	0	1	0	0
T199	0	1	0	0
T214	747	0	0	0
T215	503	0	0	0
T216	672	0	0	0
T217	503	0	0	0
T218	490	0	0	0
T219	421	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	2612	0	0
T35	722	187	0	0
T36	121038	210	0	0
T37	625	38	0	0
T64	0	265	0	0
T98	4866	0	0	0
T123	0	38	0	0
T148	0	124	0	0
T153	0	118	0	0
T170	0	42	0	0
T181	0	407	0	0
T199	0	205	0	0
T214	747	0	0	0
T215	503	0	0	0
T216	672	0	0	0
T217	503	0	0	0
T218	490	0	0	0
T219	421	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	6739	0	0
T1	11840	29	0	0
T2	15507	28	0	0
T4	0	10	0	0
T6	507	6	0	0
T12	443	4	0	0
T13	17092	10	0	0
T14	494	8	0	0
T15	16466	22	0	0
T16	515	0	0	0
T17	422	3	0	0
T18	672	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8510753	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	13	0	0
T35	722	1	0	0
T36	121038	1	0	0
T37	625	0	0	0
T64	0	3	0	0
T98	4866	0	0	0
T136	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T167	0	1	0	0
T190	0	1	0	0
T214	747	0	0	0
T215	503	0	0	0
T216	672	0	0	0
T217	503	0	0	0
T218	490	0	0	0
T219	421	0	0	0
T220	0	1	0	0
T221	0	1	0	0