Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T15
1	Covered	T6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T1,T2,T15

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T1,T2,T15

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T1,T2,T15

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T15
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T15

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T15
0	1	Covered	T44,T46,T83
1	0	Covered	T89,T222,T223

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T15
0	1	Covered	T1,T2,T15
1	0	Covered	T91,T92,T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T15
1	-	Covered	T1,T2,T15

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T15
DetectSt	168	Covered	T1,T2,T15
IdleSt	163	Covered	T6,T1,T2
StableSt	191	Covered	T1,T2,T15

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T15
DebounceSt->IdleSt	163	Covered	T15,T83,T105
DetectSt->IdleSt	186	Covered	T44,T46,T83
DetectSt->StableSt	191	Covered	T1,T2,T15
IdleSt->DebounceSt	148	Covered	T1,T2,T15
StableSt->IdleSt	206	Covered	T1,T2,T15

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T15
0	1	Covered	T1,T2,T15
0	0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T15
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T15
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T15
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T15
DebounceSt	-	0	1	0	-	-	-	Covered	T15,T83,T105
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T15
DetectSt	-	-	-	-	1	-	-	Covered	T44,T46,T83
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T15
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T15
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T15
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T15
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9144370	3112	0	0
CntIncr_A	9144370	112630	0	0
CntNoWrap_A	9144370	8505343	0	0
DetectStDropOut_A	9144370	447	0	0
DetectedOut_A	9144370	75367	0	0
DetectedPulseOut_A	9144370	865	0	0
DisabledIdleSt_A	9144370	8064675	0	0
DisabledNoDetection_A	9144370	8066757	0	0
EnterDebounceSt_A	9144370	1580	0	0
EnterDetectSt_A	9144370	1535	0	0
EnterStableSt_A	9144370	865	0	0
PulseIsPulse_A	9144370	865	0	0
StayInStableSt	9144370	74376	0	0
gen_high_event_sva.HighLevelEvent_A	9144370	8510753	0	0
gen_high_level_sva.HighLevelEvent_A	9144370	8510753	0	0
gen_not_sticky_sva.StableStDropOut_A	9144370	722	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	3112	0	0
T1	11840	20	0	0
T2	15507	12	0	0
T3	625	0	0	0
T5	0	64	0	0
T8	0	46	0	0
T9	0	54	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	24	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T44	0	48	0	0
T46	0	44	0	0
T81	0	2	0	0
T82	0	24	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	112630	0	0
T1	11840	670	0	0
T2	15507	468	0	0
T3	625	0	0	0
T5	0	2912	0	0
T8	0	1587	0	0
T9	0	1728	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	5215	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T44	0	1416	0	0
T46	0	1292	0	0
T81	0	21	0	0
T82	0	732	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8505343	0	0
T1	11840	11407	0	0
T2	15507	15070	0	0
T6	507	106	0	0
T12	443	42	0	0
T13	17092	16645	0	0
T14	494	93	0	0
T15	16466	16041	0	0
T16	515	114	0	0
T17	422	21	0	0
T18	672	271	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	447	0	0
T40	34038	0	0	0
T44	5569	24	0	0
T45	594	0	0	0
T46	0	22	0	0
T75	488	0	0	0
T83	0	1	0	0
T98	0	7	0	0
T101	0	3	0	0
T102	0	16	0	0
T104	0	15	0	0
T105	0	2	0	0
T106	0	22	0	0
T182	612	0	0	0
T183	17244	0	0	0
T184	35234	0	0	0
T185	423	0	0	0
T224	0	26	0	0
T225	521	0	0	0
T226	404	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	75367	0	0
T1	11840	703	0	0
T2	15507	557	0	0
T3	625	0	0	0
T5	0	4761	0	0
T8	0	2090	0	0
T9	0	1247	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	1929	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T81	0	81	0	0
T82	0	749	0	0
T90	0	2847	0	0
T227	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	865	0	0
T1	11840	10	0	0
T2	15507	6	0	0
T3	625	0	0	0
T5	0	32	0	0
T8	0	23	0	0
T9	0	27	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	8	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T81	0	1	0	0
T82	0	12	0	0
T90	0	26	0	0
T227	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8064675	0	0
T1	11840	6990	0	0
T2	15507	9483	0	0
T6	507	106	0	0
T12	443	42	0	0
T13	17092	16645	0	0
T14	494	93	0	0
T15	16466	2014	0	0
T16	515	114	0	0
T17	422	21	0	0
T18	672	271	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8066757	0	0
T1	11840	6991	0	0
T2	15507	9484	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	2014	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	1580	0	0
T1	11840	10	0	0
T2	15507	6	0	0
T3	625	0	0	0
T5	0	32	0	0
T8	0	23	0	0
T9	0	27	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	17	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T44	0	24	0	0
T46	0	22	0	0
T81	0	1	0	0
T82	0	12	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	1535	0	0
T1	11840	10	0	0
T2	15507	6	0	0
T3	625	0	0	0
T5	0	32	0	0
T8	0	23	0	0
T9	0	27	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	8	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T44	0	24	0	0
T46	0	22	0	0
T81	0	1	0	0
T82	0	12	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	865	0	0
T1	11840	10	0	0
T2	15507	6	0	0
T3	625	0	0	0
T5	0	32	0	0
T8	0	23	0	0
T9	0	27	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	8	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T81	0	1	0	0
T82	0	12	0	0
T90	0	26	0	0
T227	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	865	0	0
T1	11840	10	0	0
T2	15507	6	0	0
T3	625	0	0	0
T5	0	32	0	0
T8	0	23	0	0
T9	0	27	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	8	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T81	0	1	0	0
T82	0	12	0	0
T90	0	26	0	0
T227	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	74376	0	0
T1	11840	692	0	0
T2	15507	549	0	0
T3	625	0	0	0
T5	0	4728	0	0
T8	0	2062	0	0
T9	0	1218	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	1921	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T81	0	79	0	0
T82	0	737	0	0
T90	0	2814	0	0
T227	0	39	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8510753	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8510753	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	722	0	0
T1	11840	9	0	0
T2	15507	4	0	0
T3	625	0	0	0
T5	0	31	0	0
T8	0	18	0	0
T9	0	25	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	8	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T82	0	12	0	0
T90	0	19	0	0
T91	0	18	0	0
T228	0	18	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T13
1	Covered	T6,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T13
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T1,T2,T13

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T1,T2	VC_COV_UNR
1	Covered	T1,T2,T13

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T1,T2,T13

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T13
0	1	Covered	T4,T40,T97
1	0	Covered	T56,T57

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T13
0	1	Covered	T1,T2,T13
1	0	Covered	T5,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T13
1	-	Covered	T1,T2,T13

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T13
DetectSt	168	Covered	T1,T2,T13
IdleSt	163	Covered	T6,T1,T2
StableSt	191	Covered	T1,T2,T13

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T13
DebounceSt->IdleSt	163	Covered	T13,T4,T8
DetectSt->IdleSt	186	Covered	T4,T40,T97
DetectSt->StableSt	191	Covered	T1,T2,T13
IdleSt->DebounceSt	148	Covered	T1,T2,T13
StableSt->IdleSt	206	Covered	T1,T2,T13

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T13
0	1	Covered	T1,T2,T13
0	0	Excluded	T6,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T13
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T13
IdleSt	0	-	-	-	-	-	-	Covered	T6,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T13
DebounceSt	-	0	1	0	-	-	-	Covered	T13,T4,T8
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T13
DetectSt	-	-	-	-	1	-	-	Covered	T4,T40,T97
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T13
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T13
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T13
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T13
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9144370	914	0	0
CntIncr_A	9144370	45009	0	0
CntNoWrap_A	9144370	8507541	0	0
DetectStDropOut_A	9144370	64	0	0
DetectedOut_A	9144370	18355	0	0
DetectedPulseOut_A	9144370	357	0	0
DisabledIdleSt_A	9144370	8129809	0	0
DisabledNoDetection_A	9144370	8131381	0	0
EnterDebounceSt_A	9144370	490	0	0
EnterDetectSt_A	9144370	426	0	0
EnterStableSt_A	9144370	357	0	0
PulseIsPulse_A	9144370	357	0	0
StayInStableSt	9144370	17960	0	0
gen_high_level_sva.HighLevelEvent_A	9144370	8510753	0	0
gen_not_sticky_sva.StableStDropOut_A	9144370	313	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	914	0	0
T1	11840	2	0	0
T2	15507	2	0	0
T3	625	0	0	0
T4	0	9	0	0
T5	0	16	0	0
T8	0	9	0	0
T9	0	4	0	0
T12	443	0	0	0
T13	17092	11	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	8	0	0
T30	0	3	0	0
T96	0	14	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	45009	0	0
T1	11840	88	0	0
T2	15507	72	0	0
T3	625	0	0	0
T4	0	659	0	0
T5	0	496	0	0
T8	0	414	0	0
T9	0	166	0	0
T12	443	0	0	0
T13	17092	607	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	148	0	0
T30	0	195	0	0
T96	0	224	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8507541	0	0
T1	11840	11425	0	0
T2	15507	15080	0	0
T6	507	106	0	0
T12	443	42	0	0
T13	17092	16634	0	0
T14	494	93	0	0
T15	16466	16065	0	0
T16	515	114	0	0
T17	422	21	0	0
T18	672	271	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	64	0	0
T4	22800	4	0	0
T5	16581	0	0	0
T7	649	0	0	0
T8	26285	0	0	0
T36	0	1	0	0
T40	0	4	0	0
T50	800	0	0	0
T51	422	0	0	0
T52	1217	0	0	0
T53	705	0	0	0
T54	402	0	0	0
T55	434	0	0	0
T64	0	3	0	0
T97	0	3	0	0
T99	0	2	0	0
T100	0	9	0	0
T107	0	2	0	0
T108	0	2	0	0
T109	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	18355	0	0
T1	11840	37	0	0
T2	15507	59	0	0
T3	625	0	0	0
T5	0	2620	0	0
T8	0	163	0	0
T9	0	99	0	0
T12	443	0	0	0
T13	17092	320	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	94	0	0
T30	0	10	0	0
T96	0	185	0	0
T119	0	291	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	357	0	0
T1	11840	1	0	0
T2	15507	1	0	0
T3	625	0	0	0
T5	0	8	0	0
T8	0	4	0	0
T9	0	2	0	0
T12	443	0	0	0
T13	17092	5	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	4	0	0
T30	0	1	0	0
T96	0	7	0	0
T119	0	8	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8129809	0	0
T1	11840	10725	0	0
T2	15507	14527	0	0
T6	507	106	0	0
T12	443	42	0	0
T13	17092	12085	0	0
T14	494	93	0	0
T15	16466	14136	0	0
T16	515	114	0	0
T17	422	21	0	0
T18	672	271	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8131381	0	0
T1	11840	10727	0	0
T2	15507	14529	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	12085	0	0
T14	494	94	0	0
T15	16466	14137	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	490	0	0
T1	11840	1	0	0
T2	15507	1	0	0
T3	625	0	0	0
T4	0	5	0	0
T5	0	8	0	0
T8	0	5	0	0
T9	0	2	0	0
T12	443	0	0	0
T13	17092	6	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	4	0	0
T30	0	2	0	0
T96	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	426	0	0
T1	11840	1	0	0
T2	15507	1	0	0
T3	625	0	0	0
T4	0	4	0	0
T5	0	8	0	0
T8	0	4	0	0
T9	0	2	0	0
T12	443	0	0	0
T13	17092	5	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	4	0	0
T30	0	1	0	0
T96	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	357	0	0
T1	11840	1	0	0
T2	15507	1	0	0
T3	625	0	0	0
T5	0	8	0	0
T8	0	4	0	0
T9	0	2	0	0
T12	443	0	0	0
T13	17092	5	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	4	0	0
T30	0	1	0	0
T96	0	7	0	0
T119	0	8	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	357	0	0
T1	11840	1	0	0
T2	15507	1	0	0
T3	625	0	0	0
T5	0	8	0	0
T8	0	4	0	0
T9	0	2	0	0
T12	443	0	0	0
T13	17092	5	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	4	0	0
T30	0	1	0	0
T96	0	7	0	0
T119	0	8	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	17960	0	0
T1	11840	36	0	0
T2	15507	58	0	0
T3	625	0	0	0
T5	0	2612	0	0
T8	0	159	0	0
T9	0	95	0	0
T12	443	0	0	0
T13	17092	315	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	89	0	0
T30	0	9	0	0
T96	0	178	0	0
T119	0	283	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8510753	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	313	0	0
T1	11840	1	0	0
T2	15507	1	0	0
T3	625	0	0	0
T5	0	4	0	0
T8	0	4	0	0
T12	443	0	0	0
T13	17092	5	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	3	0	0
T30	0	1	0	0
T96	0	7	0	0
T119	0	8	0	0
T122	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T15
1	Covered	T6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T1,T2,T15

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T1,T2,T15

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T1,T2,T5

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T15
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T15

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T44,T46,T83
1	0	Covered	T1,T90,T116

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T8
0	1	Covered	T2,T5,T8
1	0	Covered	T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T5,T8
1	-	Covered	T2,T5,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T15
DetectSt	168	Covered	T1,T2,T5
IdleSt	163	Covered	T6,T1,T2
StableSt	191	Covered	T2,T5,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T5
DebounceSt->IdleSt	163	Covered	T15,T83,T105
DetectSt->IdleSt	186	Covered	T1,T44,T46
DetectSt->StableSt	191	Covered	T2,T5,T8
IdleSt->DebounceSt	148	Covered	T1,T2,T15
StableSt->IdleSt	206	Covered	T2,T5,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T15
0	1	Covered	T1,T2,T15
0	0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T15
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T15
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T5
DebounceSt	-	0	1	0	-	-	-	Covered	T15,T83,T105
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T15
DetectSt	-	-	-	-	1	-	-	Covered	T1,T44,T46
DetectSt	-	-	-	-	0	1	-	Covered	T2,T5,T8
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T5
StableSt	-	-	-	-	-	-	1	Covered	T2,T5,T8
StableSt	-	-	-	-	-	-	0	Covered	T2,T5,T8
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9144370	2811	0	0
CntIncr_A	9144370	97644	0	0
CntNoWrap_A	9144370	8505644	0	0
DetectStDropOut_A	9144370	366	0	0
DetectedOut_A	9144370	73965	0	0
DetectedPulseOut_A	9144370	869	0	0
DisabledIdleSt_A	9144370	8064151	0	0
DisabledNoDetection_A	9144370	8066266	0	0
EnterDebounceSt_A	9144370	1428	0	0
EnterDetectSt_A	9144370	1384	0	0
EnterStableSt_A	9144370	869	0	0
PulseIsPulse_A	9144370	869	0	0
StayInStableSt	9144370	73003	0	0
gen_high_event_sva.HighLevelEvent_A	9144370	8510753	0	0
gen_high_level_sva.HighLevelEvent_A	9144370	8510753	0	0
gen_not_sticky_sva.StableStDropOut_A	9144370	775	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	2811	0	0
T1	11840	8	0	0
T2	15507	10	0	0
T3	625	0	0	0
T5	0	24	0	0
T8	0	56	0	0
T9	0	14	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	6	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T44	0	22	0	0
T46	0	16	0	0
T82	0	44	0	0
T83	0	13	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	97644	0	0
T1	11840	287	0	0
T2	15507	460	0	0
T3	625	0	0	0
T5	0	708	0	0
T8	0	1792	0	0
T9	0	441	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	1800	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T44	0	642	0	0
T46	0	464	0	0
T82	0	2002	0	0
T83	0	2268	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8505644	0	0
T1	11840	11419	0	0
T2	15507	15072	0	0
T6	507	106	0	0
T12	443	42	0	0
T13	17092	16645	0	0
T14	494	93	0	0
T15	16466	16059	0	0
T16	515	114	0	0
T17	422	21	0	0
T18	672	271	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	366	0	0
T40	34038	0	0	0
T44	5569	11	0	0
T45	594	0	0	0
T46	0	8	0	0
T75	488	0	0	0
T83	0	4	0	0
T98	0	8	0	0
T101	0	30	0	0
T102	0	23	0	0
T104	0	6	0	0
T105	0	2	0	0
T106	0	5	0	0
T182	612	0	0	0
T183	17244	0	0	0
T184	35234	0	0	0
T185	423	0	0	0
T224	0	23	0	0
T225	521	0	0	0
T226	404	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	73965	0	0
T2	15507	189	0	0
T3	625	0	0	0
T4	22800	0	0	0
T5	0	2512	0	0
T8	0	2224	0	0
T9	0	222	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T82	0	2307	0	0
T89	0	3252	0	0
T91	0	2015	0	0
T210	0	1357	0	0
T228	0	1902	0	0
T229	0	1460	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	869	0	0
T2	15507	5	0	0
T3	625	0	0	0
T4	22800	0	0	0
T5	0	12	0	0
T8	0	28	0	0
T9	0	7	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T82	0	22	0	0
T89	0	27	0	0
T91	0	15	0	0
T210	0	19	0	0
T228	0	22	0	0
T229	0	15	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8064151	0	0
T1	11840	7669	0	0
T2	15507	9769	0	0
T6	507	106	0	0
T12	443	42	0	0
T13	17092	16645	0	0
T14	494	93	0	0
T15	16466	2014	0	0
T16	515	114	0	0
T17	422	21	0	0
T18	672	271	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8066266	0	0
T1	11840	7671	0	0
T2	15507	9771	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	2014	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	1428	0	0
T1	11840	4	0	0
T2	15507	5	0	0
T3	625	0	0	0
T5	0	12	0	0
T8	0	28	0	0
T9	0	7	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	6	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T44	0	11	0	0
T46	0	8	0	0
T82	0	22	0	0
T83	0	9	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	1384	0	0
T1	11840	4	0	0
T2	15507	5	0	0
T3	625	0	0	0
T5	0	12	0	0
T8	0	28	0	0
T9	0	7	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T44	0	11	0	0
T46	0	8	0	0
T82	0	22	0	0
T83	0	4	0	0
T89	0	27	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	869	0	0
T2	15507	5	0	0
T3	625	0	0	0
T4	22800	0	0	0
T5	0	12	0	0
T8	0	28	0	0
T9	0	7	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T82	0	22	0	0
T89	0	27	0	0
T91	0	15	0	0
T210	0	19	0	0
T228	0	22	0	0
T229	0	15	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	869	0	0
T2	15507	5	0	0
T3	625	0	0	0
T4	22800	0	0	0
T5	0	12	0	0
T8	0	28	0	0
T9	0	7	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T82	0	22	0	0
T89	0	27	0	0
T91	0	15	0	0
T210	0	19	0	0
T228	0	22	0	0
T229	0	15	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	73003	0	0
T2	15507	183	0	0
T3	625	0	0	0
T4	22800	0	0	0
T5	0	2499	0	0
T8	0	2192	0	0
T9	0	214	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T82	0	2285	0	0
T89	0	3224	0	0
T91	0	1997	0	0
T210	0	1333	0	0
T228	0	1877	0	0
T229	0	1442	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8510753	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8510753	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	775	0	0
T2	15507	4	0	0
T3	625	0	0	0
T4	22800	0	0	0
T5	0	11	0	0
T8	0	24	0	0
T9	0	6	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T82	0	22	0	0
T89	0	26	0	0
T91	0	12	0	0
T210	0	14	0	0
T228	0	19	0	0
T229	0	12	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T13
1	Covered	T6,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T13
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T2,T13,T4

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T1,T2	VC_COV_UNR
1	Covered	T2,T13,T4

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T2,T13,T4

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T13,T4
1	0	Covered	T1,T2,T13
1	1	Covered	T2,T13,T4

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T13,T4
0	1	Covered	T34,T96,T119
1	0	Covered	T56,T57

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T13,T4
0	1	Covered	T2,T13,T4
1	0	Covered	T56

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T13,T4
1	-	Covered	T2,T13,T4

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T13,T4
DetectSt	168	Covered	T2,T13,T4
IdleSt	163	Covered	T6,T1,T2
StableSt	191	Covered	T2,T13,T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T13,T4
DebounceSt->IdleSt	163	Covered	T34,T24,T58
DetectSt->IdleSt	186	Covered	T34,T96,T119
DetectSt->StableSt	191	Covered	T2,T13,T4
IdleSt->DebounceSt	148	Covered	T2,T13,T4
StableSt->IdleSt	206	Covered	T2,T13,T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T13,T4
0	1	Covered	T2,T13,T4
0	0	Excluded	T6,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T13,T4
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T13,T4
IdleSt	0	-	-	-	-	-	-	Covered	T6,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T13,T4
DebounceSt	-	0	1	0	-	-	-	Covered	T34,T24,T58
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T13,T4
DetectSt	-	-	-	-	1	-	-	Covered	T34,T96,T119
DetectSt	-	-	-	-	0	1	-	Covered	T2,T13,T4
DetectSt	-	-	-	-	0	0	-	Covered	T2,T13,T4
StableSt	-	-	-	-	-	-	1	Covered	T2,T13,T4
StableSt	-	-	-	-	-	-	0	Covered	T2,T13,T4
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9144370	877	0	0
CntIncr_A	9144370	47414	0	0
CntNoWrap_A	9144370	8507578	0	0
DetectStDropOut_A	9144370	71	0	0
DetectedOut_A	9144370	14836	0	0
DetectedPulseOut_A	9144370	341	0	0
DisabledIdleSt_A	9144370	8133491	0	0
DisabledNoDetection_A	9144370	8135126	0	0
EnterDebounceSt_A	9144370	461	0	0
EnterDetectSt_A	9144370	416	0	0
EnterStableSt_A	9144370	341	0	0
PulseIsPulse_A	9144370	341	0	0
StayInStableSt	9144370	14465	0	0
gen_high_level_sva.HighLevelEvent_A	9144370	8510753	0	0
gen_not_sticky_sva.StableStDropOut_A	9144370	309	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	877	0	0
T2	15507	2	0	0
T3	625	0	0	0
T4	22800	4	0	0
T5	0	2	0	0
T8	0	6	0	0
T9	0	2	0	0
T12	443	0	0	0
T13	17092	2	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	7	0	0
T30	0	2	0	0
T34	0	7	0	0
T58	0	5	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	47414	0	0
T2	15507	58	0	0
T3	625	0	0	0
T4	22800	212	0	0
T5	0	60	0	0
T8	0	237	0	0
T9	0	58	0	0
T12	443	0	0	0
T13	17092	139	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	173	0	0
T30	0	121	0	0
T34	0	531	0	0
T58	0	226	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8507578	0	0
T1	11840	11427	0	0
T2	15507	15080	0	0
T6	507	106	0	0
T12	443	42	0	0
T13	17092	16643	0	0
T14	494	93	0	0
T15	16466	16065	0	0
T16	515	114	0	0
T17	422	21	0	0
T18	672	271	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	71	0	0
T24	247596	0	0	0
T29	502	0	0	0
T34	14374	3	0	0
T58	16125	0	0	0
T64	0	6	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T77	527	0	0	0
T85	0	1	0	0
T96	0	2	0	0
T119	0	4	0	0
T145	0	6	0	0
T149	0	13	0	0
T230	0	13	0	0
T231	0	1	0	0
T232	0	7	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	14836	0	0
T2	15507	73	0	0
T3	625	0	0	0
T4	22800	72	0	0
T5	0	329	0	0
T8	0	155	0	0
T9	0	76	0	0
T12	443	0	0	0
T13	17092	29	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	25	0	0
T30	0	64	0	0
T58	0	17	0	0
T122	0	38	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	341	0	0
T2	15507	1	0	0
T3	625	0	0	0
T4	22800	2	0	0
T5	0	1	0	0
T8	0	3	0	0
T9	0	1	0	0
T12	443	0	0	0
T13	17092	1	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	3	0	0
T30	0	1	0	0
T58	0	2	0	0
T122	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8133491	0	0
T1	11840	11427	0	0
T2	15507	14894	0	0
T6	507	106	0	0
T12	443	42	0	0
T13	17092	12085	0	0
T14	494	93	0	0
T15	16466	16065	0	0
T16	515	114	0	0
T17	422	21	0	0
T18	672	271	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8135126	0	0
T1	11840	11430	0	0
T2	15507	14897	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	12085	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	461	0	0
T2	15507	1	0	0
T3	625	0	0	0
T4	22800	2	0	0
T5	0	1	0	0
T8	0	3	0	0
T9	0	1	0	0
T12	443	0	0	0
T13	17092	1	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	4	0	0
T30	0	1	0	0
T34	0	4	0	0
T58	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	416	0	0
T2	15507	1	0	0
T3	625	0	0	0
T4	22800	2	0	0
T5	0	1	0	0
T8	0	3	0	0
T9	0	1	0	0
T12	443	0	0	0
T13	17092	1	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	3	0	0
T30	0	1	0	0
T34	0	3	0	0
T58	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	341	0	0
T2	15507	1	0	0
T3	625	0	0	0
T4	22800	2	0	0
T5	0	1	0	0
T8	0	3	0	0
T9	0	1	0	0
T12	443	0	0	0
T13	17092	1	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	3	0	0
T30	0	1	0	0
T58	0	2	0	0
T122	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	341	0	0
T2	15507	1	0	0
T3	625	0	0	0
T4	22800	2	0	0
T5	0	1	0	0
T8	0	3	0	0
T9	0	1	0	0
T12	443	0	0	0
T13	17092	1	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	3	0	0
T30	0	1	0	0
T58	0	2	0	0
T122	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	14465	0	0
T2	15507	72	0	0
T3	625	0	0	0
T4	22800	70	0	0
T5	0	328	0	0
T8	0	150	0	0
T9	0	75	0	0
T12	443	0	0	0
T13	17092	28	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	22	0	0
T30	0	63	0	0
T58	0	15	0	0
T122	0	37	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8510753	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	309	0	0
T2	15507	1	0	0
T3	625	0	0	0
T4	22800	2	0	0
T5	0	1	0	0
T8	0	1	0	0
T9	0	1	0	0
T12	443	0	0	0
T13	17092	1	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	3	0	0
T30	0	1	0	0
T58	0	2	0	0
T122	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T15
1	Covered	T6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T1,T2,T15

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T1,T2,T15

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T1,T2,T15

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T15
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T15

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T15
0	1	Covered	T44,T46,T83
1	0	Covered	T90,T229,T222

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T15
0	1	Covered	T1,T2,T15
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T15
1	-	Covered	T1,T2,T15

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T15
DetectSt	168	Covered	T1,T2,T15
IdleSt	163	Covered	T6,T1,T2
StableSt	191	Covered	T1,T2,T15

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T15
DebounceSt->IdleSt	163	Covered	T15,T83,T105
DetectSt->IdleSt	186	Covered	T44,T46,T83
DetectSt->StableSt	191	Covered	T1,T2,T15
IdleSt->DebounceSt	148	Covered	T1,T2,T15
StableSt->IdleSt	206	Covered	T1,T2,T15

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T15
0	1	Covered	T1,T2,T15
0	0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T15
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T15
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T15
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T15
DebounceSt	-	0	1	0	-	-	-	Covered	T15,T83,T105
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T15
DetectSt	-	-	-	-	1	-	-	Covered	T44,T46,T83
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T15
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T15
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T15
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T15
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9144370	3396	0	0
CntIncr_A	9144370	117016	0	0
CntNoWrap_A	9144370	8505059	0	0
DetectStDropOut_A	9144370	557	0	0
DetectedOut_A	9144370	84377	0	0
DetectedPulseOut_A	9144370	943	0	0
DisabledIdleSt_A	9144370	8054971	0	0
DisabledNoDetection_A	9144370	8057064	0	0
EnterDebounceSt_A	9144370	1721	0	0
EnterDetectSt_A	9144370	1676	0	0
EnterStableSt_A	9144370	943	0	0
PulseIsPulse_A	9144370	943	0	0
StayInStableSt	9144370	83320	0	0
gen_high_event_sva.HighLevelEvent_A	9144370	8510753	0	0
gen_high_level_sva.HighLevelEvent_A	9144370	8510753	0	0
gen_not_sticky_sva.StableStDropOut_A	9144370	829	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	3396	0	0
T1	11840	46	0	0
T2	15507	24	0	0
T3	625	0	0	0
T5	0	64	0	0
T8	0	22	0	0
T9	0	52	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	9	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T44	0	26	0	0
T46	0	48	0	0
T82	0	24	0	0
T83	0	24	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	117016	0	0
T1	11840	1380	0	0
T2	15507	900	0	0
T3	625	0	0	0
T5	0	2112	0	0
T8	0	957	0	0
T9	0	1274	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	2425	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T44	0	760	0	0
T46	0	1416	0	0
T82	0	1056	0	0
T83	0	3792	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8505059	0	0
T1	11840	11381	0	0
T2	15507	15058	0	0
T6	507	106	0	0
T12	443	42	0	0
T13	17092	16645	0	0
T14	494	93	0	0
T15	16466	16056	0	0
T16	515	114	0	0
T17	422	21	0	0
T18	672	271	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	557	0	0
T40	34038	0	0	0
T44	5569	13	0	0
T45	594	0	0	0
T46	0	24	0	0
T75	488	0	0	0
T83	0	9	0	0
T90	0	2	0	0
T98	0	26	0	0
T101	0	22	0	0
T102	0	23	0	0
T104	0	12	0	0
T105	0	13	0	0
T182	612	0	0	0
T183	17244	0	0	0
T184	35234	0	0	0
T185	423	0	0	0
T225	521	0	0	0
T226	404	0	0	0
T229	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	84377	0	0
T1	11840	1208	0	0
T2	15507	737	0	0
T3	625	0	0	0
T5	0	5561	0	0
T8	0	692	0	0
T9	0	2042	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	233	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T82	0	425	0	0
T89	0	2585	0	0
T91	0	856	0	0
T228	0	391	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	943	0	0
T1	11840	23	0	0
T2	15507	12	0	0
T3	625	0	0	0
T5	0	32	0	0
T8	0	11	0	0
T9	0	26	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	1	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T82	0	12	0	0
T89	0	25	0	0
T91	0	7	0	0
T228	0	9	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8054971	0	0
T1	11840	6705	0	0
T2	15507	9469	0	0
T6	507	106	0	0
T12	443	42	0	0
T13	17092	16645	0	0
T14	494	93	0	0
T15	16466	2014	0	0
T16	515	114	0	0
T17	422	21	0	0
T18	672	271	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8057064	0	0
T1	11840	6706	0	0
T2	15507	9470	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	2014	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	1721	0	0
T1	11840	23	0	0
T2	15507	12	0	0
T3	625	0	0	0
T5	0	32	0	0
T8	0	11	0	0
T9	0	26	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	8	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T44	0	13	0	0
T46	0	24	0	0
T82	0	12	0	0
T83	0	15	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	1676	0	0
T1	11840	23	0	0
T2	15507	12	0	0
T3	625	0	0	0
T5	0	32	0	0
T8	0	11	0	0
T9	0	26	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	1	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T44	0	13	0	0
T46	0	24	0	0
T82	0	12	0	0
T83	0	9	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	943	0	0
T1	11840	23	0	0
T2	15507	12	0	0
T3	625	0	0	0
T5	0	32	0	0
T8	0	11	0	0
T9	0	26	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	1	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T82	0	12	0	0
T89	0	25	0	0
T91	0	7	0	0
T228	0	9	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	943	0	0
T1	11840	23	0	0
T2	15507	12	0	0
T3	625	0	0	0
T5	0	32	0	0
T8	0	11	0	0
T9	0	26	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	1	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T82	0	12	0	0
T89	0	25	0	0
T91	0	7	0	0
T228	0	9	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	83320	0	0
T1	11840	1184	0	0
T2	15507	723	0	0
T3	625	0	0	0
T5	0	5528	0	0
T8	0	679	0	0
T9	0	2012	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	232	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T82	0	413	0	0
T89	0	2559	0	0
T91	0	848	0	0
T228	0	380	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8510753	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8510753	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	829	0	0
T1	11840	22	0	0
T2	15507	10	0	0
T3	625	0	0	0
T5	0	31	0	0
T8	0	9	0	0
T9	0	22	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	1	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T82	0	12	0	0
T89	0	24	0	0
T91	0	6	0	0
T228	0	7	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T13
1	Covered	T6,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T13
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T1,T2,T13

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T1,T2	VC_COV_UNR
1	Covered	T1,T2,T13

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T1,T2,T13

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T13
0	1	Covered	T24,T40,T99
1	0	Covered	T56,T57

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T13
0	1	Covered	T2,T13,T4
1	0	Covered	T5

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T13
1	-	Covered	T2,T13,T4

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T13
DetectSt	168	Covered	T1,T2,T13
IdleSt	163	Covered	T6,T1,T2
StableSt	191	Covered	T1,T2,T13

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T13
DebounceSt->IdleSt	163	Covered	T4,T9,T24
DetectSt->IdleSt	186	Covered	T24,T40,T99
DetectSt->StableSt	191	Covered	T1,T2,T13
IdleSt->DebounceSt	148	Covered	T1,T2,T13
StableSt->IdleSt	206	Covered	T1,T2,T13

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T13
0	1	Covered	T1,T2,T13
0	0	Excluded	T6,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T13
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T13
IdleSt	0	-	-	-	-	-	-	Covered	T6,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T13
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T9,T24
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T13
DetectSt	-	-	-	-	1	-	-	Covered	T24,T40,T99
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T13
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T13
StableSt	-	-	-	-	-	-	1	Covered	T2,T13,T4
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T13
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9144370	985	0	0
CntIncr_A	9144370	49391	0	0
CntNoWrap_A	9144370	8507470	0	0
DetectStDropOut_A	9144370	49	0	0
DetectedOut_A	9144370	22733	0	0
DetectedPulseOut_A	9144370	418	0	0
DisabledIdleSt_A	9144370	8108864	0	0
DisabledNoDetection_A	9144370	8110468	0	0
EnterDebounceSt_A	9144370	514	0	0
EnterDetectSt_A	9144370	472	0	0
EnterStableSt_A	9144370	418	0	0
PulseIsPulse_A	9144370	418	0	0
StayInStableSt	9144370	22276	0	0
gen_high_level_sva.HighLevelEvent_A	9144370	8510753	0	0
gen_not_sticky_sva.StableStDropOut_A	9144370	374	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	985	0	0
T1	11840	2	0	0
T2	15507	2	0	0
T3	625	0	0	0
T4	0	17	0	0
T5	0	14	0	0
T8	0	2	0	0
T9	0	7	0	0
T12	443	0	0	0
T13	17092	12	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	7	0	0
T34	0	8	0	0
T58	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	49391	0	0
T1	11840	66	0	0
T2	15507	64	0	0
T3	625	0	0	0
T4	0	993	0	0
T5	0	511	0	0
T8	0	80	0	0
T9	0	251	0	0
T12	443	0	0	0
T13	17092	900	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	198	0	0
T34	0	356	0	0
T58	0	183	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8507470	0	0
T1	11840	11425	0	0
T2	15507	15080	0	0
T6	507	106	0	0
T12	443	42	0	0
T13	17092	16633	0	0
T14	494	93	0	0
T15	16466	16065	0	0
T16	515	114	0	0
T17	422	21	0	0
T18	672	271	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	49	0	0
T24	247596	3	0	0
T25	1657	0	0	0
T40	0	7	0	0
T58	16125	0	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0
T99	0	9	0	0
T157	0	4	0	0
T233	0	6	0	0
T234	0	3	0	0
T235	0	4	0	0
T236	0	2	0	0
T237	0	6	0	0
T238	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	22733	0	0
T1	11840	57	0	0
T2	15507	67	0	0
T3	625	0	0	0
T4	0	240	0	0
T5	0	2214	0	0
T8	0	51	0	0
T9	0	185	0	0
T12	443	0	0	0
T13	17092	110	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T30	0	86	0	0
T34	0	248	0	0
T58	0	163	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	418	0	0
T1	11840	1	0	0
T2	15507	1	0	0
T3	625	0	0	0
T4	0	8	0	0
T5	0	7	0	0
T8	0	1	0	0
T9	0	3	0	0
T12	443	0	0	0
T13	17092	6	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T30	0	1	0	0
T34	0	4	0	0
T58	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8108864	0	0
T1	11840	10220	0	0
T2	15507	14347	0	0
T6	507	106	0	0
T12	443	42	0	0
T13	17092	12085	0	0
T14	494	93	0	0
T15	16466	15832	0	0
T16	515	114	0	0
T17	422	21	0	0
T18	672	271	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8110468	0	0
T1	11840	10222	0	0
T2	15507	14349	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	12085	0	0
T14	494	94	0	0
T15	16466	15833	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	514	0	0
T1	11840	1	0	0
T2	15507	1	0	0
T3	625	0	0	0
T4	0	9	0	0
T5	0	7	0	0
T8	0	1	0	0
T9	0	4	0	0
T12	443	0	0	0
T13	17092	6	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	4	0	0
T34	0	4	0	0
T58	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	472	0	0
T1	11840	1	0	0
T2	15507	1	0	0
T3	625	0	0	0
T4	0	8	0	0
T5	0	7	0	0
T8	0	1	0	0
T9	0	3	0	0
T12	443	0	0	0
T13	17092	6	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	3	0	0
T34	0	4	0	0
T58	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	418	0	0
T1	11840	1	0	0
T2	15507	1	0	0
T3	625	0	0	0
T4	0	8	0	0
T5	0	7	0	0
T8	0	1	0	0
T9	0	3	0	0
T12	443	0	0	0
T13	17092	6	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T30	0	1	0	0
T34	0	4	0	0
T58	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	418	0	0
T1	11840	1	0	0
T2	15507	1	0	0
T3	625	0	0	0
T4	0	8	0	0
T5	0	7	0	0
T8	0	1	0	0
T9	0	3	0	0
T12	443	0	0	0
T13	17092	6	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T30	0	1	0	0
T34	0	4	0	0
T58	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	22276	0	0
T1	11840	55	0	0
T2	15507	66	0	0
T3	625	0	0	0
T4	0	232	0	0
T5	0	2207	0	0
T8	0	50	0	0
T9	0	180	0	0
T12	443	0	0	0
T13	17092	104	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T30	0	85	0	0
T34	0	244	0	0
T58	0	160	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8510753	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	374	0	0
T2	15507	1	0	0
T3	625	0	0	0
T4	22800	8	0	0
T5	0	4	0	0
T8	0	1	0	0
T9	0	1	0	0
T12	443	0	0	0
T13	17092	6	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T30	0	1	0	0
T34	0	4	0	0
T58	0	3	0	0
T96	0	11	0	0