Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T15
1	Covered	T6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T1,T2,T15

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T1,T2,T15

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T1,T2,T15

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T15
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T15

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T15
0	1	Covered	T1,T44,T46
1	0	Covered	T1,T90,T222

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T15,T5
0	1	Covered	T2,T15,T5
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T15,T5
1	-	Covered	T2,T15,T5

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T15
DetectSt	168	Covered	T1,T2,T15
IdleSt	163	Covered	T6,T1,T2
StableSt	191	Covered	T2,T15,T5

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T15
DebounceSt->IdleSt	163	Covered	T15,T83,T105
DetectSt->IdleSt	186	Covered	T1,T44,T46
DetectSt->StableSt	191	Covered	T2,T15,T5
IdleSt->DebounceSt	148	Covered	T1,T2,T15
StableSt->IdleSt	206	Covered	T2,T15,T5

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T15
0	1	Covered	T1,T2,T15
0	0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T15
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T15
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T15
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T15
DebounceSt	-	0	1	0	-	-	-	Covered	T15,T83,T105
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T15
DetectSt	-	-	-	-	1	-	-	Covered	T1,T44,T46
DetectSt	-	-	-	-	0	1	-	Covered	T2,T15,T5
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T15
StableSt	-	-	-	-	-	-	1	Covered	T2,T15,T5
StableSt	-	-	-	-	-	-	0	Covered	T2,T15,T5
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9144370	3107	0	0
CntIncr_A	9144370	107893	0	0
CntNoWrap_A	9144370	8505348	0	0
DetectStDropOut_A	9144370	454	0	0
DetectedOut_A	9144370	74353	0	0
DetectedPulseOut_A	9144370	946	0	0
DisabledIdleSt_A	9144370	8065625	0	0
DisabledNoDetection_A	9144370	8067727	0	0
EnterDebounceSt_A	9144370	1577	0	0
EnterDetectSt_A	9144370	1530	0	0
EnterStableSt_A	9144370	946	0	0
PulseIsPulse_A	9144370	946	0	0
StayInStableSt	9144370	73301	0	0
gen_high_event_sva.HighLevelEvent_A	9144370	8510753	0	0
gen_high_level_sva.HighLevelEvent_A	9144370	8510753	0	0
gen_not_sticky_sva.StableStDropOut_A	9144370	840	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	3107	0	0
T1	11840	54	0	0
T2	15507	58	0	0
T3	625	0	0	0
T5	0	26	0	0
T8	0	52	0	0
T9	0	40	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	22	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T44	0	48	0	0
T46	0	48	0	0
T82	0	4	0	0
T83	0	24	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	107893	0	0
T1	11840	1936	0	0
T2	15507	2726	0	0
T3	625	0	0	0
T5	0	1001	0	0
T8	0	1976	0	0
T9	0	1380	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	4878	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T44	0	1416	0	0
T46	0	1421	0	0
T82	0	164	0	0
T83	0	3792	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8505348	0	0
T1	11840	11373	0	0
T2	15507	15024	0	0
T6	507	106	0	0
T12	443	42	0	0
T13	17092	16645	0	0
T14	494	93	0	0
T15	16466	16043	0	0
T16	515	114	0	0
T17	422	21	0	0
T18	672	271	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	454	0	0
T1	11840	15	0	0
T2	15507	0	0	0
T3	625	0	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T44	0	24	0	0
T46	0	24	0	0
T83	0	9	0	0
T90	0	5	0	0
T98	0	10	0	0
T101	0	13	0	0
T102	0	33	0	0
T104	0	3	0	0
T222	0	10	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	74353	0	0
T2	15507	1997	0	0
T3	625	0	0	0
T4	22800	0	0	0
T5	0	743	0	0
T8	0	1856	0	0
T9	0	679	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	1468	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T82	0	82	0	0
T89	0	1653	0	0
T91	0	657	0	0
T228	0	634	0	0
T229	0	1204	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	946	0	0
T2	15507	29	0	0
T3	625	0	0	0
T4	22800	0	0	0
T5	0	13	0	0
T8	0	26	0	0
T9	0	20	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	6	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T82	0	2	0	0
T89	0	13	0	0
T91	0	8	0	0
T228	0	9	0	0
T229	0	12	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8065625	0	0
T1	11840	7670	0	0
T2	15507	8058	0	0
T6	507	106	0	0
T12	443	42	0	0
T13	17092	16645	0	0
T14	494	93	0	0
T15	16466	2014	0	0
T16	515	114	0	0
T17	422	21	0	0
T18	672	271	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8067727	0	0
T1	11840	7672	0	0
T2	15507	8058	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	2014	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	1577	0	0
T1	11840	27	0	0
T2	15507	29	0	0
T3	625	0	0	0
T5	0	13	0	0
T8	0	26	0	0
T9	0	20	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	16	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T44	0	24	0	0
T46	0	24	0	0
T82	0	2	0	0
T83	0	15	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	1530	0	0
T1	11840	27	0	0
T2	15507	29	0	0
T3	625	0	0	0
T5	0	13	0	0
T8	0	26	0	0
T9	0	20	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	6	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T44	0	24	0	0
T46	0	24	0	0
T82	0	2	0	0
T83	0	9	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	946	0	0
T2	15507	29	0	0
T3	625	0	0	0
T4	22800	0	0	0
T5	0	13	0	0
T8	0	26	0	0
T9	0	20	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	6	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T82	0	2	0	0
T89	0	13	0	0
T91	0	8	0	0
T228	0	9	0	0
T229	0	12	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	946	0	0
T2	15507	29	0	0
T3	625	0	0	0
T4	22800	0	0	0
T5	0	13	0	0
T8	0	26	0	0
T9	0	20	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	6	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T82	0	2	0	0
T89	0	13	0	0
T91	0	8	0	0
T228	0	9	0	0
T229	0	12	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	73301	0	0
T2	15507	1965	0	0
T3	625	0	0	0
T4	22800	0	0	0
T5	0	729	0	0
T8	0	1826	0	0
T9	0	656	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	1462	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T82	0	80	0	0
T89	0	1639	0	0
T91	0	648	0	0
T228	0	623	0	0
T229	0	1191	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8510753	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8510753	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	840	0	0
T2	15507	26	0	0
T3	625	0	0	0
T4	22800	0	0	0
T5	0	12	0	0
T8	0	22	0	0
T9	0	17	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	6	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T82	0	2	0	0
T89	0	12	0	0
T91	0	7	0	0
T228	0	7	0	0
T229	0	11	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T13
1	Covered	T6,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T13
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T2,T13,T4

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T1,T2	VC_COV_UNR
1	Covered	T2,T13,T4

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T2,T13,T4

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T13,T15
1	0	Covered	T1,T2,T13
1	1	Covered	T2,T13,T4

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T13,T4
0	1	Covered	T13,T4,T96
1	0	Covered	T56,T57

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T8
0	1	Covered	T2,T8,T9
1	0	Covered	T87

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T5,T8
1	-	Covered	T2,T8,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T13,T4
DetectSt	168	Covered	T2,T13,T4
IdleSt	163	Covered	T6,T1,T2
StableSt	191	Covered	T2,T5,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T13,T4
DebounceSt->IdleSt	163	Covered	T9,T34,T58
DetectSt->IdleSt	186	Covered	T13,T4,T96
DetectSt->StableSt	191	Covered	T2,T5,T8
IdleSt->DebounceSt	148	Covered	T2,T13,T4
StableSt->IdleSt	206	Covered	T2,T5,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T13,T4
0	1	Covered	T2,T13,T4
0	0	Excluded	T6,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T13,T4
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T13,T4
IdleSt	0	-	-	-	-	-	-	Covered	T6,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T56,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T13,T4
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T34,T58
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T13,T4
DetectSt	-	-	-	-	1	-	-	Covered	T13,T4,T96
DetectSt	-	-	-	-	0	1	-	Covered	T2,T5,T8
DetectSt	-	-	-	-	0	0	-	Covered	T2,T13,T4
StableSt	-	-	-	-	-	-	1	Covered	T2,T8,T9
StableSt	-	-	-	-	-	-	0	Covered	T2,T5,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9144370	941	0	0
CntIncr_A	9144370	52354	0	0
CntNoWrap_A	9144370	8507514	0	0
DetectStDropOut_A	9144370	83	0	0
DetectedOut_A	9144370	16001	0	0
DetectedPulseOut_A	9144370	360	0	0
DisabledIdleSt_A	9144370	8128625	0	0
DisabledNoDetection_A	9144370	8130245	0	0
EnterDebounceSt_A	9144370	494	0	0
EnterDetectSt_A	9144370	448	0	0
EnterStableSt_A	9144370	360	0	0
PulseIsPulse_A	9144370	360	0	0
StayInStableSt	9144370	15617	0	0
gen_high_level_sva.HighLevelEvent_A	9144370	8510753	0	0
gen_not_sticky_sva.StableStDropOut_A	9144370	333	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	941	0	0
T2	15507	6	0	0
T3	625	0	0	0
T4	22800	20	0	0
T5	0	2	0	0
T8	0	6	0	0
T9	0	5	0	0
T12	443	0	0	0
T13	17092	6	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	10	0	0
T30	0	2	0	0
T34	0	9	0	0
T58	0	5	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	52354	0	0
T2	15507	264	0	0
T3	625	0	0	0
T4	22800	1430	0	0
T5	0	62	0	0
T8	0	261	0	0
T9	0	180	0	0
T12	443	0	0	0
T13	17092	504	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	225	0	0
T30	0	159	0	0
T34	0	538	0	0
T58	0	160	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8507514	0	0
T1	11840	11427	0	0
T2	15507	15076	0	0
T6	507	106	0	0
T12	443	42	0	0
T13	17092	16639	0	0
T14	494	93	0	0
T15	16466	16065	0	0
T16	515	114	0	0
T17	422	21	0	0
T18	672	271	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	83	0	0
T3	625	0	0	0
T4	22800	10	0	0
T13	17092	3	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T36	0	16	0	0
T40	0	2	0	0
T50	800	0	0	0
T51	422	0	0	0
T96	0	3	0	0
T107	0	4	0	0
T239	0	2	0	0
T240	0	3	0	0
T241	0	4	0	0
T242	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	16001	0	0
T2	15507	129	0	0
T3	625	0	0	0
T4	22800	0	0	0
T5	0	325	0	0
T8	0	133	0	0
T9	0	125	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	81	0	0
T30	0	26	0	0
T34	0	145	0	0
T58	0	82	0	0
T119	0	30	0	0
T122	0	119	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	360	0	0
T2	15507	3	0	0
T3	625	0	0	0
T4	22800	0	0	0
T5	0	1	0	0
T8	0	3	0	0
T9	0	2	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	5	0	0
T30	0	1	0	0
T34	0	4	0	0
T58	0	2	0	0
T119	0	3	0	0
T122	0	6	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8128625	0	0
T1	11840	11427	0	0
T2	15507	13088	0	0
T6	507	106	0	0
T12	443	42	0	0
T13	17092	12085	0	0
T14	494	93	0	0
T15	16466	14597	0	0
T16	515	114	0	0
T17	422	21	0	0
T18	672	271	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8130245	0	0
T1	11840	11430	0	0
T2	15507	13089	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	12085	0	0
T14	494	94	0	0
T15	16466	14598	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	494	0	0
T2	15507	3	0	0
T3	625	0	0	0
T4	22800	10	0	0
T5	0	1	0	0
T8	0	3	0	0
T9	0	3	0	0
T12	443	0	0	0
T13	17092	3	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	5	0	0
T30	0	1	0	0
T34	0	5	0	0
T58	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	448	0	0
T2	15507	3	0	0
T3	625	0	0	0
T4	22800	10	0	0
T5	0	1	0	0
T8	0	3	0	0
T9	0	2	0	0
T12	443	0	0	0
T13	17092	3	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	5	0	0
T30	0	1	0	0
T34	0	4	0	0
T58	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	360	0	0
T2	15507	3	0	0
T3	625	0	0	0
T4	22800	0	0	0
T5	0	1	0	0
T8	0	3	0	0
T9	0	2	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	5	0	0
T30	0	1	0	0
T34	0	4	0	0
T58	0	2	0	0
T119	0	3	0	0
T122	0	6	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	360	0	0
T2	15507	3	0	0
T3	625	0	0	0
T4	22800	0	0	0
T5	0	1	0	0
T8	0	3	0	0
T9	0	2	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	5	0	0
T30	0	1	0	0
T34	0	4	0	0
T58	0	2	0	0
T119	0	3	0	0
T122	0	6	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	15617	0	0
T2	15507	126	0	0
T3	625	0	0	0
T4	22800	0	0	0
T5	0	323	0	0
T8	0	130	0	0
T9	0	123	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	76	0	0
T30	0	25	0	0
T34	0	141	0	0
T58	0	80	0	0
T119	0	27	0	0
T122	0	113	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	8510753	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9144370	333	0	0
T2	15507	3	0	0
T3	625	0	0	0
T4	22800	0	0	0
T8	0	3	0	0
T9	0	2	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	5	0	0
T30	0	1	0	0
T34	0	4	0	0
T40	0	4	0	0
T58	0	2	0	0
T119	0	3	0	0
T122	0	6	0	0