Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1030591197	10559	0	0
auto_block_debounce_ctl_rd_A	1030591197	1770	0	0
auto_block_out_ctl_rd_A	1030591197	2455	0	0
com_det_ctl_0_rd_A	1030591197	3622	0	0
com_det_ctl_1_rd_A	1030591197	3474	0	0
com_det_ctl_2_rd_A	1030591197	3555	0	0
com_det_ctl_3_rd_A	1030591197	3714	0	0
com_out_ctl_0_rd_A	1030591197	4299	0	0
com_out_ctl_1_rd_A	1030591197	4222	0	0
com_out_ctl_2_rd_A	1030591197	4173	0	0
com_out_ctl_3_rd_A	1030591197	4133	0	0
com_pre_det_ctl_0_rd_A	1030591197	1382	0	0
com_pre_det_ctl_1_rd_A	1030591197	1424	0	0
com_pre_det_ctl_2_rd_A	1030591197	1312	0	0
com_pre_det_ctl_3_rd_A	1030591197	1466	0	0
com_pre_sel_ctl_0_rd_A	1030591197	4304	0	0
com_pre_sel_ctl_1_rd_A	1030591197	4294	0	0
com_pre_sel_ctl_2_rd_A	1030591197	4313	0	0
com_pre_sel_ctl_3_rd_A	1030591197	4266	0	0
com_sel_ctl_0_rd_A	1030591197	4417	0	0
com_sel_ctl_1_rd_A	1030591197	4480	0	0
com_sel_ctl_2_rd_A	1030591197	4332	0	0
com_sel_ctl_3_rd_A	1030591197	4453	0	0
ec_rst_ctl_rd_A	1030591197	2264	0	0
intr_enable_rd_A	1030591197	1701	0	0
key_intr_ctl_rd_A	1030591197	3925	0	0
key_intr_debounce_ctl_rd_A	1030591197	1450	0	0
key_invert_ctl_rd_A	1030591197	5009	0	0
pin_allowed_ctl_rd_A	1030591197	5986	0	0
pin_out_ctl_rd_A	1030591197	4520	0	0
pin_out_value_rd_A	1030591197	4799	0	0
regwen_rd_A	1030591197	1506	0	0
ulp_ac_debounce_ctl_rd_A	1030591197	1413	0	0
ulp_ctl_rd_A	1030591197	1374	0	0
ulp_lid_debounce_ctl_rd_A	1030591197	1534	0	0
ulp_pwrb_debounce_ctl_rd_A	1030591197	1548	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	10559	0	0
T24	125431	15	0	0
T25	46039	0	0	0
T30	0	5	0	0
T40	0	5	0	0
T58	733708	0	0	0
T64	0	8	0	0
T65	53904	0	0	0
T66	240308	0	0	0
T67	327297	0	0	0
T68	20688	0	0	0
T69	32170	0	0	0
T70	251101	0	0	0
T71	194914	0	0	0
T84	0	13	0	0
T85	0	4	0	0
T120	0	2	0	0
T123	0	12	0	0
T149	0	16	0	0
T274	0	9	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1770	0	0
T39	89592	0	0	0
T40	401928	32	0	0
T45	145798	0	0	0
T46	267202	0	0	0
T47	502880	0	0	0
T84	0	29	0	0
T85	0	15	0	0
T182	147066	0	0	0
T183	422505	0	0	0
T184	510902	0	0	0
T185	103584	0	0	0
T186	261096	0	0	0
T273	0	15	0	0
T275	0	1	0	0
T276	0	7	0	0
T277	0	8	0	0
T278	0	1	0	0
T279	0	18	0	0
T280	0	22	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	2455	0	0
T39	89592	0	0	0
T40	401928	26	0	0
T45	145798	0	0	0
T46	267202	0	0	0
T47	502880	0	0	0
T84	0	52	0	0
T85	0	20	0	0
T182	147066	0	0	0
T183	422505	0	0	0
T184	510902	0	0	0
T185	103584	0	0	0
T186	261096	0	0	0
T273	0	6	0	0
T275	0	8	0	0
T276	0	3	0	0
T277	0	14	0	0
T278	0	10	0	0
T279	0	4	0	0
T280	0	18	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	3622	0	0
T4	114000	64	0	0
T5	729542	36	0	0
T7	35760	0	0	0
T8	328574	0	0	0
T34	0	42	0	0
T40	0	135	0	0
T50	196035	0	0	0
T51	12690	0	0	0
T52	152113	0	0	0
T53	144608	0	0	0
T54	201350	0	0	0
T55	217120	0	0	0
T58	0	55	0	0
T84	0	28	0	0
T90	0	15	0	0
T97	0	29	0	0
T184	0	64	0	0
T228	0	29	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	3474	0	0
T4	114000	62	0	0
T5	729542	50	0	0
T7	35760	0	0	0
T8	328574	0	0	0
T34	0	36	0	0
T40	0	111	0	0
T50	196035	0	0	0
T51	12690	0	0	0
T52	152113	0	0	0
T53	144608	0	0	0
T54	201350	0	0	0
T55	217120	0	0	0
T58	0	68	0	0
T84	0	3	0	0
T90	0	35	0	0
T97	0	22	0	0
T184	0	49	0	0
T228	0	31	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	3555	0	0
T4	114000	61	0	0
T5	729542	32	0	0
T7	35760	0	0	0
T8	328574	0	0	0
T34	0	33	0	0
T40	0	132	0	0
T50	196035	0	0	0
T51	12690	0	0	0
T52	152113	0	0	0
T53	144608	0	0	0
T54	201350	0	0	0
T55	217120	0	0	0
T58	0	67	0	0
T84	0	31	0	0
T90	0	30	0	0
T97	0	31	0	0
T184	0	54	0	0
T228	0	58	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	3714	0	0
T4	114000	74	0	0
T5	729542	63	0	0
T7	35760	0	0	0
T8	328574	0	0	0
T34	0	40	0	0
T40	0	130	0	0
T50	196035	0	0	0
T51	12690	0	0	0
T52	152113	0	0	0
T53	144608	0	0	0
T54	201350	0	0	0
T55	217120	0	0	0
T58	0	69	0	0
T84	0	3	0	0
T90	0	22	0	0
T97	0	39	0	0
T184	0	63	0	0
T228	0	16	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	4299	0	0
T4	114000	77	0	0
T5	729542	44	0	0
T7	35760	0	0	0
T8	328574	0	0	0
T34	0	52	0	0
T40	0	137	0	0
T50	196035	0	0	0
T51	12690	0	0	0
T52	152113	0	0	0
T53	144608	0	0	0
T54	201350	0	0	0
T55	217120	0	0	0
T58	0	78	0	0
T84	0	11	0	0
T90	0	36	0	0
T97	0	25	0	0
T184	0	75	0	0
T228	0	45	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	4222	0	0
T4	114000	77	0	0
T5	729542	79	0	0
T7	35760	0	0	0
T8	328574	0	0	0
T34	0	51	0	0
T40	0	147	0	0
T50	196035	0	0	0
T51	12690	0	0	0
T52	152113	0	0	0
T53	144608	0	0	0
T54	201350	0	0	0
T55	217120	0	0	0
T58	0	70	0	0
T84	0	21	0	0
T90	0	41	0	0
T97	0	40	0	0
T184	0	63	0	0
T228	0	40	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	4173	0	0
T4	114000	64	0	0
T5	729542	60	0	0
T7	35760	0	0	0
T8	328574	0	0	0
T34	0	36	0	0
T40	0	94	0	0
T50	196035	0	0	0
T51	12690	0	0	0
T52	152113	0	0	0
T53	144608	0	0	0
T54	201350	0	0	0
T55	217120	0	0	0
T58	0	94	0	0
T84	0	10	0	0
T90	0	53	0	0
T97	0	61	0	0
T184	0	59	0	0
T228	0	37	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	4133	0	0
T4	114000	65	0	0
T5	729542	53	0	0
T7	35760	0	0	0
T8	328574	0	0	0
T34	0	47	0	0
T40	0	121	0	0
T50	196035	0	0	0
T51	12690	0	0	0
T52	152113	0	0	0
T53	144608	0	0	0
T54	201350	0	0	0
T55	217120	0	0	0
T58	0	75	0	0
T84	0	15	0	0
T90	0	26	0	0
T97	0	53	0	0
T184	0	47	0	0
T228	0	29	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1382	0	0
T39	89592	0	0	0
T40	401928	15	0	0
T45	145798	0	0	0
T46	267202	0	0	0
T47	502880	0	0	0
T84	0	29	0	0
T85	0	21	0	0
T145	0	6	0	0
T161	0	12	0	0
T166	0	30	0	0
T177	0	14	0	0
T182	147066	0	0	0
T183	422505	0	0	0
T184	510902	0	0	0
T185	103584	0	0	0
T186	261096	0	0	0
T212	0	11	0	0
T280	0	10	0	0
T281	0	21	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1424	0	0
T39	89592	0	0	0
T40	401928	14	0	0
T45	145798	0	0	0
T46	267202	0	0	0
T47	502880	0	0	0
T84	0	16	0	0
T85	0	25	0	0
T145	0	16	0	0
T161	0	1	0	0
T166	0	5	0	0
T177	0	18	0	0
T182	147066	0	0	0
T183	422505	0	0	0
T184	510902	0	0	0
T185	103584	0	0	0
T186	261096	0	0	0
T212	0	1	0	0
T280	0	13	0	0
T281	0	12	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1312	0	0
T39	89592	0	0	0
T40	401928	10	0	0
T45	145798	0	0	0
T46	267202	0	0	0
T47	502880	0	0	0
T84	0	21	0	0
T85	0	19	0	0
T145	0	4	0	0
T161	0	5	0	0
T166	0	13	0	0
T177	0	11	0	0
T182	147066	0	0	0
T183	422505	0	0	0
T184	510902	0	0	0
T185	103584	0	0	0
T186	261096	0	0	0
T212	0	6	0	0
T280	0	28	0	0
T281	0	28	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1466	0	0
T39	89592	0	0	0
T40	401928	6	0	0
T45	145798	0	0	0
T46	267202	0	0	0
T47	502880	0	0	0
T84	0	25	0	0
T85	0	15	0	0
T145	0	21	0	0
T161	0	16	0	0
T166	0	25	0	0
T177	0	16	0	0
T182	147066	0	0	0
T183	422505	0	0	0
T184	510902	0	0	0
T185	103584	0	0	0
T186	261096	0	0	0
T212	0	7	0	0
T280	0	21	0	0
T281	0	9	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	4304	0	0
T4	114000	59	0	0
T5	729542	39	0	0
T7	35760	0	0	0
T8	328574	0	0	0
T34	0	68	0	0
T40	0	182	0	0
T50	196035	0	0	0
T51	12690	0	0	0
T52	152113	0	0	0
T53	144608	0	0	0
T54	201350	0	0	0
T55	217120	0	0	0
T58	0	96	0	0
T84	0	28	0	0
T90	0	33	0	0
T97	0	32	0	0
T184	0	61	0	0
T228	0	21	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	4294	0	0
T4	114000	73	0	0
T5	729542	64	0	0
T7	35760	0	0	0
T8	328574	0	0	0
T34	0	35	0	0
T40	0	145	0	0
T50	196035	0	0	0
T51	12690	0	0	0
T52	152113	0	0	0
T53	144608	0	0	0
T54	201350	0	0	0
T55	217120	0	0	0
T58	0	70	0	0
T84	0	26	0	0
T90	0	45	0	0
T97	0	32	0	0
T184	0	61	0	0
T228	0	67	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	4313	0	0
T4	114000	72	0	0
T5	729542	40	0	0
T7	35760	0	0	0
T8	328574	0	0	0
T34	0	41	0	0
T40	0	171	0	0
T50	196035	0	0	0
T51	12690	0	0	0
T52	152113	0	0	0
T53	144608	0	0	0
T54	201350	0	0	0
T55	217120	0	0	0
T58	0	57	0	0
T84	0	26	0	0
T90	0	28	0	0
T97	0	46	0	0
T184	0	71	0	0
T228	0	37	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	4266	0	0
T4	114000	90	0	0
T5	729542	43	0	0
T7	35760	0	0	0
T8	328574	0	0	0
T34	0	57	0	0
T40	0	156	0	0
T50	196035	0	0	0
T51	12690	0	0	0
T52	152113	0	0	0
T53	144608	0	0	0
T54	201350	0	0	0
T55	217120	0	0	0
T58	0	76	0	0
T84	0	18	0	0
T90	0	8	0	0
T97	0	23	0	0
T184	0	91	0	0
T228	0	25	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	4417	0	0
T4	114000	81	0	0
T5	729542	48	0	0
T7	35760	0	0	0
T8	328574	0	0	0
T34	0	35	0	0
T40	0	156	0	0
T50	196035	0	0	0
T51	12690	0	0	0
T52	152113	0	0	0
T53	144608	0	0	0
T54	201350	0	0	0
T55	217120	0	0	0
T58	0	74	0	0
T84	0	19	0	0
T90	0	28	0	0
T97	0	54	0	0
T184	0	52	0	0
T228	0	36	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	4480	0	0
T4	114000	77	0	0
T5	729542	32	0	0
T7	35760	0	0	0
T8	328574	0	0	0
T34	0	34	0	0
T40	0	162	0	0
T50	196035	0	0	0
T51	12690	0	0	0
T52	152113	0	0	0
T53	144608	0	0	0
T54	201350	0	0	0
T55	217120	0	0	0
T58	0	64	0	0
T84	0	17	0	0
T90	0	22	0	0
T97	0	29	0	0
T184	0	88	0	0
T228	0	43	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	4332	0	0
T4	114000	55	0	0
T5	729542	56	0	0
T7	35760	0	0	0
T8	328574	0	0	0
T34	0	30	0	0
T40	0	158	0	0
T50	196035	0	0	0
T51	12690	0	0	0
T52	152113	0	0	0
T53	144608	0	0	0
T54	201350	0	0	0
T55	217120	0	0	0
T58	0	74	0	0
T84	0	11	0	0
T90	0	16	0	0
T97	0	63	0	0
T184	0	79	0	0
T228	0	28	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	4453	0	0
T4	114000	54	0	0
T5	729542	33	0	0
T7	35760	0	0	0
T8	328574	0	0	0
T34	0	58	0	0
T40	0	144	0	0
T50	196035	0	0	0
T51	12690	0	0	0
T52	152113	0	0	0
T53	144608	0	0	0
T54	201350	0	0	0
T55	217120	0	0	0
T58	0	89	0	0
T84	0	14	0	0
T90	0	36	0	0
T97	0	25	0	0
T184	0	83	0	0
T228	0	37	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	2264	0	0
T4	114000	38	0	0
T5	729542	10	0	0
T7	35760	0	0	0
T8	328574	0	0	0
T34	0	9	0	0
T40	0	72	0	0
T46	0	8	0	0
T50	196035	0	0	0
T51	12690	0	0	0
T52	152113	0	0	0
T53	144608	0	0	0
T54	201350	0	0	0
T55	217120	0	0	0
T58	0	14	0	0
T59	0	10	0	0
T90	0	8	0	0
T151	0	2	0	0
T184	0	63	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1701	0	0
T5	729542	0	0	0
T7	35760	0	0	0
T8	328574	0	0	0
T9	101454	0	0	0
T10	63583	0	0	0
T27	246139	0	0	0
T40	0	13	0	0
T52	152113	27	0	0
T53	144608	0	0	0
T54	201350	0	0	0
T55	217120	0	0	0
T84	0	9	0	0
T85	0	88	0	0
T145	0	16	0	0
T161	0	4	0	0
T166	0	16	0	0
T177	0	17	0	0
T280	0	36	0	0
T281	0	9	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	3925	0	0
T26	59387	0	0	0
T40	0	13	0	0
T42	77836	0	0	0
T43	46844	0	0	0
T74	238418	0	0	0
T80	297100	2	0	0
T84	0	49	0	0
T85	0	28	0	0
T96	935779	0	0	0
T119	144431	0	0	0
T159	0	7	0	0
T161	0	24	0	0
T162	0	10	0	0
T173	27762	0	0	0
T174	214227	0	0	0
T175	0	1	0	0
T176	0	4	0	0
T280	0	15	0	0
T282	28932	0	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1450	0	0
T39	89592	0	0	0
T40	401928	8	0	0
T45	145798	0	0	0
T46	267202	0	0	0
T47	502880	0	0	0
T84	0	25	0	0
T85	0	21	0	0
T145	0	9	0	0
T161	0	21	0	0
T166	0	11	0	0
T177	0	1	0	0
T182	147066	0	0	0
T183	422505	0	0	0
T184	510902	0	0	0
T185	103584	0	0	0
T186	261096	0	0	0
T212	0	5	0	0
T280	0	19	0	0
T281	0	30	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	5009	0	0
T3	309450	0	0	0
T4	114000	0	0	0
T14	69321	58	0	0
T15	411670	0	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T40	0	11	0	0
T50	196035	0	0	0
T51	12690	0	0	0
T52	152113	0	0	0
T74	0	91	0	0
T84	0	75	0	0
T85	0	90	0	0
T145	0	35	0	0
T161	0	59	0	0
T280	0	7	0	0
T283	0	74	0	0
T284	0	61	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	5986	0	0
T24	125431	0	0	0
T29	218516	69	0	0
T40	0	17	0	0
T58	733708	0	0	0
T59	0	63	0	0
T65	53904	0	0	0
T66	240308	0	0	0
T67	327297	0	0	0
T68	20688	0	0	0
T69	32170	0	0	0
T70	251101	37	0	0
T77	57961	0	0	0
T84	0	38	0	0
T85	0	169	0	0
T161	0	50	0	0
T280	0	169	0	0
T285	0	48	0	0
T286	0	51	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	4520	0	0
T24	125431	0	0	0
T29	218516	60	0	0
T40	0	19	0	0
T58	733708	0	0	0
T59	0	53	0	0
T65	53904	0	0	0
T66	240308	0	0	0
T67	327297	0	0	0
T68	20688	0	0	0
T69	32170	0	0	0
T70	251101	38	0	0
T77	57961	0	0	0
T84	0	42	0	0
T85	0	130	0	0
T161	0	49	0	0
T280	0	131	0	0
T285	0	70	0	0
T286	0	54	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	4799	0	0
T24	125431	0	0	0
T29	218516	71	0	0
T40	0	9	0	0
T58	733708	0	0	0
T59	0	55	0	0
T65	53904	0	0	0
T66	240308	0	0	0
T67	327297	0	0	0
T68	20688	0	0	0
T69	32170	0	0	0
T70	251101	48	0	0
T77	57961	0	0	0
T84	0	58	0	0
T85	0	127	0	0
T161	0	40	0	0
T280	0	169	0	0
T285	0	40	0	0
T286	0	71	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1506	0	0
T39	89592	0	0	0
T40	401928	8	0	0
T45	145798	0	0	0
T46	267202	0	0	0
T47	502880	0	0	0
T84	0	21	0	0
T85	0	22	0	0
T145	0	5	0	0
T161	0	10	0	0
T166	0	9	0	0
T177	0	18	0	0
T182	147066	0	0	0
T183	422505	0	0	0
T184	510902	0	0	0
T185	103584	0	0	0
T186	261096	0	0	0
T212	0	5	0	0
T280	0	14	0	0
T281	0	2	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1413	0	0
T25	46039	11	0	0
T26	0	4	0	0
T30	103602	0	0	0
T38	113958	0	0	0
T40	0	11	0	0
T59	0	3	0	0
T62	0	5	0	0
T72	139901	0	0	0
T78	251153	0	0	0
T79	131107	0	0	0
T84	0	42	0	0
T85	0	23	0	0
T93	0	4	0	0
T131	0	8	0	0
T172	106178	0	0	0
T280	0	21	0	0
T287	131088	0	0	0
T288	228624	0	0	0
T289	66917	0	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1374	0	0
T25	46039	21	0	0
T26	0	4	0	0
T30	103602	0	0	0
T38	113958	0	0	0
T40	0	5	0	0
T62	0	10	0	0
T72	139901	0	0	0
T78	251153	0	0	0
T79	131107	0	0	0
T84	0	27	0	0
T85	0	25	0	0
T93	0	5	0	0
T131	0	4	0	0
T172	106178	0	0	0
T280	0	25	0	0
T287	131088	0	0	0
T288	228624	0	0	0
T289	66917	0	0	0
T290	0	4	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1534	0	0
T25	46039	12	0	0
T26	0	4	0	0
T30	103602	0	0	0
T38	113958	0	0	0
T40	0	7	0	0
T59	0	6	0	0
T62	0	13	0	0
T72	139901	0	0	0
T78	251153	0	0	0
T79	131107	0	0	0
T84	0	20	0	0
T85	0	15	0	0
T93	0	2	0	0
T131	0	14	0	0
T172	106178	0	0	0
T280	0	30	0	0
T287	131088	0	0	0
T288	228624	0	0	0
T289	66917	0	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1548	0	0
T25	46039	2	0	0
T26	0	5	0	0
T30	103602	0	0	0
T38	113958	0	0	0
T40	0	18	0	0
T59	0	3	0	0
T62	0	6	0	0
T72	139901	0	0	0
T78	251153	0	0	0
T79	131107	0	0	0
T84	0	15	0	0
T85	0	21	0	0
T93	0	9	0	0
T131	0	8	0	0
T172	106178	0	0	0
T280	0	19	0	0
T287	131088	0	0	0
T288	228624	0	0	0
T289	66917	0	0	0