Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.52 98.77 96.78 100.00 95.51 98.23 99.52 93.86


Total test records in report: 910
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html

T595 /workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.2756616383 Mar 12 02:50:44 PM PDT 24 Mar 12 02:50:50 PM PDT 24 3834506328 ps
T596 /workspace/coverage/default/19.sysrst_ctrl_stress_all.1284010878 Mar 12 02:50:00 PM PDT 24 Mar 12 02:50:04 PM PDT 24 9225408650 ps
T597 /workspace/coverage/default/3.sysrst_ctrl_alert_test.1622115714 Mar 12 02:48:58 PM PDT 24 Mar 12 02:49:02 PM PDT 24 2018854627 ps
T598 /workspace/coverage/default/23.sysrst_ctrl_in_out_inverted.3953552616 Mar 12 02:50:10 PM PDT 24 Mar 12 02:50:17 PM PDT 24 2480621009 ps
T599 /workspace/coverage/default/13.sysrst_ctrl_stress_all.1918885343 Mar 12 02:49:44 PM PDT 24 Mar 12 02:49:48 PM PDT 24 6722967636 ps
T600 /workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.3811653436 Mar 12 02:49:49 PM PDT 24 Mar 12 02:49:53 PM PDT 24 2479061243 ps
T601 /workspace/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.402740079 Mar 12 02:50:01 PM PDT 24 Mar 12 02:50:06 PM PDT 24 2711586580 ps
T602 /workspace/coverage/default/47.sysrst_ctrl_alert_test.2932595864 Mar 12 02:51:24 PM PDT 24 Mar 12 02:51:27 PM PDT 24 2030175205 ps
T603 /workspace/coverage/default/0.sysrst_ctrl_alert_test.2606928147 Mar 12 02:48:43 PM PDT 24 Mar 12 02:48:45 PM PDT 24 2029444510 ps
T604 /workspace/coverage/default/8.sysrst_ctrl_smoke.970702785 Mar 12 02:49:21 PM PDT 24 Mar 12 02:49:23 PM PDT 24 2126866529 ps
T605 /workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.854873910 Mar 12 02:48:42 PM PDT 24 Mar 12 02:48:51 PM PDT 24 3039430856 ps
T354 /workspace/coverage/default/27.sysrst_ctrl_stress_all.2223602898 Mar 12 02:50:24 PM PDT 24 Mar 12 02:51:36 PM PDT 24 59242458598 ps
T606 /workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.1650428447 Mar 12 02:51:22 PM PDT 24 Mar 12 02:52:22 PM PDT 24 21006068028 ps
T607 /workspace/coverage/default/48.sysrst_ctrl_combo_detect.3880356996 Mar 12 02:51:28 PM PDT 24 Mar 12 02:57:43 PM PDT 24 137989451812 ps
T608 /workspace/coverage/default/37.sysrst_ctrl_smoke.2288859532 Mar 12 02:50:45 PM PDT 24 Mar 12 02:50:48 PM PDT 24 2122334452 ps
T609 /workspace/coverage/default/15.sysrst_ctrl_smoke.1405073970 Mar 12 02:49:42 PM PDT 24 Mar 12 02:49:44 PM PDT 24 2151972667 ps
T610 /workspace/coverage/default/31.sysrst_ctrl_smoke.2375085378 Mar 12 02:50:36 PM PDT 24 Mar 12 02:50:38 PM PDT 24 2128823941 ps
T611 /workspace/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.1008913875 Mar 12 02:50:07 PM PDT 24 Mar 12 02:55:53 PM PDT 24 125469739282 ps
T612 /workspace/coverage/default/5.sysrst_ctrl_pin_access_test.2711564318 Mar 12 02:49:05 PM PDT 24 Mar 12 02:49:08 PM PDT 24 2252522073 ps
T220 /workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.3698696955 Mar 12 02:49:33 PM PDT 24 Mar 12 02:50:45 PM PDT 24 53839688492 ps
T613 /workspace/coverage/default/42.sysrst_ctrl_combo_detect.4033694135 Mar 12 02:51:03 PM PDT 24 Mar 12 02:51:21 PM PDT 24 63015153971 ps
T614 /workspace/coverage/default/43.sysrst_ctrl_edge_detect.359421987 Mar 12 02:51:11 PM PDT 24 Mar 12 02:51:20 PM PDT 24 4389147345 ps
T615 /workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.3823842785 Mar 12 02:49:46 PM PDT 24 Mar 12 02:49:48 PM PDT 24 3037808530 ps
T616 /workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.422352839 Mar 12 02:51:24 PM PDT 24 Mar 12 02:51:32 PM PDT 24 2759400830 ps
T617 /workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.3972655129 Mar 12 02:49:03 PM PDT 24 Mar 12 02:49:05 PM PDT 24 2636314915 ps
T618 /workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.18391602 Mar 12 02:50:14 PM PDT 24 Mar 12 02:50:16 PM PDT 24 2857636396 ps
T619 /workspace/coverage/default/21.sysrst_ctrl_pin_access_test.3402450746 Mar 12 02:50:06 PM PDT 24 Mar 12 02:50:11 PM PDT 24 2021246619 ps
T620 /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.2829401981 Mar 12 02:48:59 PM PDT 24 Mar 12 02:49:06 PM PDT 24 2250703427 ps
T621 /workspace/coverage/default/8.sysrst_ctrl_pin_access_test.3005964475 Mar 12 02:49:29 PM PDT 24 Mar 12 02:49:31 PM PDT 24 2234298418 ps
T622 /workspace/coverage/default/2.sysrst_ctrl_combo_detect.1000891227 Mar 12 02:48:49 PM PDT 24 Mar 12 02:49:34 PM PDT 24 101444296931 ps
T623 /workspace/coverage/default/13.sysrst_ctrl_alert_test.1598644364 Mar 12 02:49:41 PM PDT 24 Mar 12 02:49:46 PM PDT 24 2015324128 ps
T624 /workspace/coverage/default/12.sysrst_ctrl_smoke.3333485660 Mar 12 02:49:36 PM PDT 24 Mar 12 02:49:42 PM PDT 24 2111804943 ps
T625 /workspace/coverage/default/35.sysrst_ctrl_smoke.3064283164 Mar 12 02:50:48 PM PDT 24 Mar 12 02:50:55 PM PDT 24 2112862561 ps
T626 /workspace/coverage/default/5.sysrst_ctrl_alert_test.1836579341 Mar 12 02:49:15 PM PDT 24 Mar 12 02:49:21 PM PDT 24 2011007890 ps
T627 /workspace/coverage/default/38.sysrst_ctrl_smoke.3670216090 Mar 12 02:50:54 PM PDT 24 Mar 12 02:50:57 PM PDT 24 2120551182 ps
T628 /workspace/coverage/default/29.sysrst_ctrl_edge_detect.2870412246 Mar 12 02:50:26 PM PDT 24 Mar 12 02:50:33 PM PDT 24 2971689332 ps
T629 /workspace/coverage/default/16.sysrst_ctrl_stress_all.1709082602 Mar 12 02:49:49 PM PDT 24 Mar 12 02:50:17 PM PDT 24 10497735129 ps
T630 /workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.4124719197 Mar 12 02:49:57 PM PDT 24 Mar 12 02:50:01 PM PDT 24 2475288206 ps
T631 /workspace/coverage/default/20.sysrst_ctrl_pin_override_test.3695254290 Mar 12 02:50:03 PM PDT 24 Mar 12 02:50:11 PM PDT 24 2512624675 ps
T632 /workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.3409167755 Mar 12 02:51:18 PM PDT 24 Mar 12 02:51:21 PM PDT 24 3978250851 ps
T189 /workspace/coverage/default/2.sysrst_ctrl_edge_detect.1438252125 Mar 12 02:48:56 PM PDT 24 Mar 12 02:48:59 PM PDT 24 3220225120 ps
T192 /workspace/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.3691878229 Mar 12 02:50:55 PM PDT 24 Mar 12 02:50:59 PM PDT 24 4740491524 ps
T193 /workspace/coverage/default/10.sysrst_ctrl_pin_override_test.3459687750 Mar 12 02:49:27 PM PDT 24 Mar 12 02:49:31 PM PDT 24 2519622973 ps
T194 /workspace/coverage/default/21.sysrst_ctrl_auto_blk_key_output.1972784981 Mar 12 02:50:04 PM PDT 24 Mar 12 02:50:15 PM PDT 24 3699399375 ps
T195 /workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.3333645581 Mar 12 02:50:17 PM PDT 24 Mar 12 02:50:23 PM PDT 24 3678022947 ps
T196 /workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.4019296616 Mar 12 02:49:51 PM PDT 24 Mar 12 02:52:05 PM PDT 24 308035674395 ps
T156 /workspace/coverage/default/16.sysrst_ctrl_edge_detect.3658735259 Mar 12 02:49:50 PM PDT 24 Mar 12 02:49:52 PM PDT 24 5068559982 ps
T92 /workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.1521154452 Mar 12 02:51:25 PM PDT 24 Mar 12 02:53:49 PM PDT 24 53874350692 ps
T197 /workspace/coverage/default/1.sysrst_ctrl_auto_blk_key_output.3375566793 Mar 12 02:48:45 PM PDT 24 Mar 12 02:48:48 PM PDT 24 3516933115 ps
T198 /workspace/coverage/default/27.sysrst_ctrl_smoke.1318129797 Mar 12 02:50:17 PM PDT 24 Mar 12 02:50:21 PM PDT 24 2112270291 ps
T633 /workspace/coverage/default/3.sysrst_ctrl_edge_detect.4255114299 Mar 12 02:49:02 PM PDT 24 Mar 12 02:49:09 PM PDT 24 4686709388 ps
T127 /workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.220685763 Mar 12 02:50:02 PM PDT 24 Mar 12 02:50:05 PM PDT 24 6985714858 ps
T634 /workspace/coverage/default/44.sysrst_ctrl_pin_access_test.1682527065 Mar 12 02:51:14 PM PDT 24 Mar 12 02:51:20 PM PDT 24 2227831787 ps
T635 /workspace/coverage/default/29.sysrst_ctrl_alert_test.35008437 Mar 12 02:50:25 PM PDT 24 Mar 12 02:50:26 PM PDT 24 2049652010 ps
T636 /workspace/coverage/default/38.sysrst_ctrl_pin_access_test.3189158629 Mar 12 02:51:02 PM PDT 24 Mar 12 02:51:09 PM PDT 24 2235787389 ps
T336 /workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.133023326 Mar 12 02:50:56 PM PDT 24 Mar 12 02:51:49 PM PDT 24 78737367461 ps
T637 /workspace/coverage/default/6.sysrst_ctrl_pin_override_test.1037117092 Mar 12 02:49:10 PM PDT 24 Mar 12 02:49:17 PM PDT 24 2510295136 ps
T348 /workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.755382659 Mar 12 02:51:18 PM PDT 24 Mar 12 02:51:44 PM PDT 24 51053383582 ps
T638 /workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.3887731620 Mar 12 02:51:04 PM PDT 24 Mar 12 02:51:07 PM PDT 24 2629152274 ps
T146 /workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.4029596214 Mar 12 02:49:15 PM PDT 24 Mar 12 02:49:27 PM PDT 24 18602616106 ps
T639 /workspace/coverage/default/40.sysrst_ctrl_pin_override_test.2610987537 Mar 12 02:50:55 PM PDT 24 Mar 12 02:51:03 PM PDT 24 2511939407 ps
T640 /workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.2235655454 Mar 12 02:50:24 PM PDT 24 Mar 12 02:50:34 PM PDT 24 3638218200 ps
T641 /workspace/coverage/default/4.sysrst_ctrl_edge_detect.1240454935 Mar 12 02:49:08 PM PDT 24 Mar 12 02:49:12 PM PDT 24 3698382098 ps
T642 /workspace/coverage/default/46.sysrst_ctrl_smoke.1181795725 Mar 12 02:51:17 PM PDT 24 Mar 12 02:51:19 PM PDT 24 2130796377 ps
T643 /workspace/coverage/default/18.sysrst_ctrl_alert_test.3565189782 Mar 12 02:49:58 PM PDT 24 Mar 12 02:50:04 PM PDT 24 2012499429 ps
T644 /workspace/coverage/default/49.sysrst_ctrl_alert_test.2912274421 Mar 12 02:51:25 PM PDT 24 Mar 12 02:51:29 PM PDT 24 2020817907 ps
T645 /workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.1893649837 Mar 12 02:49:05 PM PDT 24 Mar 12 02:52:25 PM PDT 24 150526687106 ps
T646 /workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.886783343 Mar 12 02:49:43 PM PDT 24 Mar 12 02:49:47 PM PDT 24 2619133255 ps
T647 /workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.766957738 Mar 12 02:49:48 PM PDT 24 Mar 12 02:49:57 PM PDT 24 2612736371 ps
T648 /workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.4236769586 Mar 12 02:51:33 PM PDT 24 Mar 12 02:51:57 PM PDT 24 35858056742 ps
T649 /workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.496947595 Mar 12 02:51:34 PM PDT 24 Mar 12 02:51:56 PM PDT 24 29602455609 ps
T110 /workspace/coverage/default/35.sysrst_ctrl_stress_all.1296624098 Mar 12 02:50:48 PM PDT 24 Mar 12 02:51:32 PM PDT 24 15605204542 ps
T650 /workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.3490594525 Mar 12 02:51:07 PM PDT 24 Mar 12 02:51:15 PM PDT 24 10630659724 ps
T651 /workspace/coverage/default/23.sysrst_ctrl_edge_detect.2420852096 Mar 12 02:50:07 PM PDT 24 Mar 12 02:50:08 PM PDT 24 2716999771 ps
T652 /workspace/coverage/default/37.sysrst_ctrl_combo_detect.2385853127 Mar 12 02:50:46 PM PDT 24 Mar 12 02:51:41 PM PDT 24 151653564238 ps
T653 /workspace/coverage/default/47.sysrst_ctrl_edge_detect.1451971491 Mar 12 02:51:22 PM PDT 24 Mar 12 02:51:30 PM PDT 24 2468750471 ps
T654 /workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.1619153914 Mar 12 02:50:46 PM PDT 24 Mar 12 02:50:49 PM PDT 24 3767650182 ps
T655 /workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.4280865909 Mar 12 02:50:50 PM PDT 24 Mar 12 02:51:49 PM PDT 24 24333092822 ps
T656 /workspace/coverage/default/33.sysrst_ctrl_edge_detect.1284430833 Mar 12 02:50:43 PM PDT 24 Mar 12 02:50:45 PM PDT 24 2601777575 ps
T657 /workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.2942445288 Mar 12 02:49:47 PM PDT 24 Mar 12 02:49:52 PM PDT 24 2614325997 ps
T658 /workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.3564345216 Mar 12 02:49:56 PM PDT 24 Mar 12 02:49:59 PM PDT 24 3456682357 ps
T659 /workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.1027895959 Mar 12 02:50:04 PM PDT 24 Mar 12 02:50:08 PM PDT 24 2635087849 ps
T660 /workspace/coverage/default/43.sysrst_ctrl_alert_test.958058666 Mar 12 02:51:11 PM PDT 24 Mar 12 02:51:14 PM PDT 24 2017825891 ps
T661 /workspace/coverage/default/1.sysrst_ctrl_combo_detect.335975735 Mar 12 02:48:53 PM PDT 24 Mar 12 02:50:33 PM PDT 24 147710217476 ps
T136 /workspace/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.1212839671 Mar 12 02:50:07 PM PDT 24 Mar 12 02:51:47 PM PDT 24 2080131864671 ps
T247 /workspace/coverage/default/3.sysrst_ctrl_sec_cm.2638873703 Mar 12 02:48:57 PM PDT 24 Mar 12 02:49:26 PM PDT 24 42100193076 ps
T360 /workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.746291415 Mar 12 02:51:17 PM PDT 24 Mar 12 02:52:09 PM PDT 24 66078039802 ps
T662 /workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.3764616732 Mar 12 02:50:00 PM PDT 24 Mar 12 02:50:21 PM PDT 24 29606082444 ps
T663 /workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.797544043 Mar 12 02:51:23 PM PDT 24 Mar 12 02:51:48 PM PDT 24 13601257446 ps
T291 /workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.2496095781 Mar 12 02:50:38 PM PDT 24 Mar 12 02:51:16 PM PDT 24 13854640737 ps
T664 /workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.3505871567 Mar 12 02:51:41 PM PDT 24 Mar 12 02:55:34 PM PDT 24 87729044124 ps
T157 /workspace/coverage/default/11.sysrst_ctrl_stress_all.2993430026 Mar 12 02:49:37 PM PDT 24 Mar 12 02:51:46 PM PDT 24 897011048614 ps
T665 /workspace/coverage/default/11.sysrst_ctrl_alert_test.3724845973 Mar 12 02:49:35 PM PDT 24 Mar 12 02:49:37 PM PDT 24 2057023936 ps
T666 /workspace/coverage/default/17.sysrst_ctrl_pin_access_test.2845093821 Mar 12 02:49:54 PM PDT 24 Mar 12 02:49:56 PM PDT 24 2190384681 ps
T128 /workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.497735652 Mar 12 02:51:24 PM PDT 24 Mar 12 02:51:28 PM PDT 24 10522930661 ps
T667 /workspace/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.4187679024 Mar 12 02:50:44 PM PDT 24 Mar 12 02:50:52 PM PDT 24 2839192221 ps
T668 /workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.36957893 Mar 12 02:50:39 PM PDT 24 Mar 12 02:50:42 PM PDT 24 2483541687 ps
T669 /workspace/coverage/default/22.sysrst_ctrl_combo_detect.3621867616 Mar 12 02:50:14 PM PDT 24 Mar 12 02:50:45 PM PDT 24 24733172878 ps
T670 /workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.2867059964 Mar 12 02:49:40 PM PDT 24 Mar 12 02:49:45 PM PDT 24 3649643825 ps
T671 /workspace/coverage/default/21.sysrst_ctrl_smoke.2434191682 Mar 12 02:50:06 PM PDT 24 Mar 12 02:50:08 PM PDT 24 2146649193 ps
T672 /workspace/coverage/default/46.sysrst_ctrl_pin_access_test.3024259428 Mar 12 02:51:17 PM PDT 24 Mar 12 02:51:19 PM PDT 24 2104078662 ps
T673 /workspace/coverage/default/24.sysrst_ctrl_stress_all.3507932370 Mar 12 02:50:08 PM PDT 24 Mar 12 02:53:59 PM PDT 24 168806555655 ps
T674 /workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.3956226972 Mar 12 02:50:11 PM PDT 24 Mar 12 02:50:16 PM PDT 24 2452691174 ps
T675 /workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.3577492322 Mar 12 02:49:05 PM PDT 24 Mar 12 02:49:14 PM PDT 24 3049342663 ps
T56 /workspace/coverage/default/1.sysrst_ctrl_feature_disable.2564331267 Mar 12 02:48:54 PM PDT 24 Mar 12 02:50:36 PM PDT 24 39539510004 ps
T676 /workspace/coverage/default/18.sysrst_ctrl_combo_detect.41541749 Mar 12 02:49:58 PM PDT 24 Mar 12 02:50:33 PM PDT 24 56181100893 ps
T168 /workspace/coverage/default/42.sysrst_ctrl_edge_detect.11163155 Mar 12 02:51:05 PM PDT 24 Mar 12 02:51:16 PM PDT 24 5173096827 ps
T677 /workspace/coverage/default/1.sysrst_ctrl_stress_all.542749608 Mar 12 02:48:49 PM PDT 24 Mar 12 02:55:38 PM PDT 24 152956383495 ps
T678 /workspace/coverage/default/24.sysrst_ctrl_edge_detect.2130457643 Mar 12 02:50:09 PM PDT 24 Mar 12 02:50:16 PM PDT 24 3252739887 ps
T679 /workspace/coverage/default/33.sysrst_ctrl_pin_override_test.1621800534 Mar 12 02:50:40 PM PDT 24 Mar 12 02:50:44 PM PDT 24 2519528303 ps
T680 /workspace/coverage/default/6.sysrst_ctrl_pin_access_test.711824555 Mar 12 02:49:13 PM PDT 24 Mar 12 02:49:18 PM PDT 24 2019597798 ps
T213 /workspace/coverage/default/13.sysrst_ctrl_edge_detect.2460644132 Mar 12 02:49:44 PM PDT 24 Mar 12 02:49:56 PM PDT 24 4391775504 ps
T337 /workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.1440177785 Mar 12 02:51:33 PM PDT 24 Mar 12 02:53:16 PM PDT 24 138315159255 ps
T681 /workspace/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.1511440691 Mar 12 02:50:09 PM PDT 24 Mar 12 02:54:44 PM PDT 24 108222667356 ps
T682 /workspace/coverage/default/29.sysrst_ctrl_smoke.3713776438 Mar 12 02:50:23 PM PDT 24 Mar 12 02:50:25 PM PDT 24 2126672545 ps
T683 /workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.3660487512 Mar 12 02:51:04 PM PDT 24 Mar 12 02:51:12 PM PDT 24 6206415600 ps
T684 /workspace/coverage/default/38.sysrst_ctrl_combo_detect.1057155383 Mar 12 02:50:57 PM PDT 24 Mar 12 02:52:34 PM PDT 24 90947221803 ps
T237 /workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.1807058447 Mar 12 02:50:09 PM PDT 24 Mar 12 02:54:04 PM PDT 24 2541713293187 ps
T685 /workspace/coverage/default/46.sysrst_ctrl_pin_override_test.1427168050 Mar 12 02:51:21 PM PDT 24 Mar 12 02:51:24 PM PDT 24 2548007867 ps
T686 /workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.640995941 Mar 12 02:51:07 PM PDT 24 Mar 12 02:51:15 PM PDT 24 3022296160 ps
T687 /workspace/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.829688738 Mar 12 02:50:06 PM PDT 24 Mar 12 02:50:16 PM PDT 24 3527367454 ps
T688 /workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.580719646 Mar 12 02:51:30 PM PDT 24 Mar 12 02:52:29 PM PDT 24 23580436780 ps
T689 /workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.62168347 Mar 12 02:49:55 PM PDT 24 Mar 12 02:54:19 PM PDT 24 93963934388 ps
T690 /workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.888002869 Mar 12 02:51:10 PM PDT 24 Mar 12 02:51:18 PM PDT 24 2612940438 ps
T691 /workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.4069576565 Mar 12 02:50:55 PM PDT 24 Mar 12 02:50:59 PM PDT 24 2712453043 ps
T692 /workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.839308834 Mar 12 02:49:48 PM PDT 24 Mar 12 02:49:52 PM PDT 24 2626924972 ps
T693 /workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.1256577819 Mar 12 02:51:44 PM PDT 24 Mar 12 02:51:59 PM PDT 24 76118412811 ps
T694 /workspace/coverage/default/19.sysrst_ctrl_smoke.1051626493 Mar 12 02:49:58 PM PDT 24 Mar 12 02:50:01 PM PDT 24 2121710537 ps
T695 /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.1947944382 Mar 12 02:49:02 PM PDT 24 Mar 12 02:49:04 PM PDT 24 2272494442 ps
T696 /workspace/coverage/default/48.sysrst_ctrl_pin_access_test.2071769110 Mar 12 02:51:28 PM PDT 24 Mar 12 02:51:35 PM PDT 24 2049292267 ps
T355 /workspace/coverage/default/34.sysrst_ctrl_combo_detect.1080044794 Mar 12 02:50:40 PM PDT 24 Mar 12 02:51:15 PM PDT 24 43179982713 ps
T697 /workspace/coverage/default/13.sysrst_ctrl_pin_override_test.3288656722 Mar 12 02:49:39 PM PDT 24 Mar 12 02:49:47 PM PDT 24 2510490471 ps
T698 /workspace/coverage/default/36.sysrst_ctrl_smoke.1225473915 Mar 12 02:50:51 PM PDT 24 Mar 12 02:50:57 PM PDT 24 2111150510 ps
T699 /workspace/coverage/default/40.sysrst_ctrl_alert_test.750910998 Mar 12 02:50:55 PM PDT 24 Mar 12 02:50:58 PM PDT 24 2035909076 ps
T700 /workspace/coverage/default/11.sysrst_ctrl_in_out_inverted.1589935544 Mar 12 02:49:35 PM PDT 24 Mar 12 02:49:38 PM PDT 24 2476749502 ps
T701 /workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.1044667104 Mar 12 02:49:58 PM PDT 24 Mar 12 02:54:04 PM PDT 24 1257423826840 ps
T347 /workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.942644120 Mar 12 02:51:30 PM PDT 24 Mar 12 02:52:46 PM PDT 24 150394834382 ps
T702 /workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.2062416839 Mar 12 02:51:08 PM PDT 24 Mar 12 02:51:15 PM PDT 24 2435884655 ps
T190 /workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.250091426 Mar 12 02:49:57 PM PDT 24 Mar 12 02:51:23 PM PDT 24 38092590413 ps
T703 /workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.2999412504 Mar 12 02:51:36 PM PDT 24 Mar 12 02:51:59 PM PDT 24 59098600448 ps
T704 /workspace/coverage/default/29.sysrst_ctrl_pin_override_test.4231510677 Mar 12 02:50:26 PM PDT 24 Mar 12 02:50:30 PM PDT 24 2521315473 ps
T705 /workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.2882931417 Mar 12 02:48:56 PM PDT 24 Mar 12 02:50:10 PM PDT 24 376366294624 ps
T706 /workspace/coverage/default/42.sysrst_ctrl_pin_access_test.480278207 Mar 12 02:51:04 PM PDT 24 Mar 12 02:51:05 PM PDT 24 2150433735 ps
T707 /workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.721194684 Mar 12 02:51:31 PM PDT 24 Mar 12 02:51:49 PM PDT 24 26096286681 ps
T708 /workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.3813448268 Mar 12 02:51:17 PM PDT 24 Mar 12 02:54:44 PM PDT 24 319619476011 ps
T709 /workspace/coverage/default/7.sysrst_ctrl_smoke.3759660464 Mar 12 02:49:14 PM PDT 24 Mar 12 02:49:16 PM PDT 24 2131029652 ps
T710 /workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.2648224546 Mar 12 02:49:36 PM PDT 24 Mar 12 02:49:46 PM PDT 24 3588409084 ps
T238 /workspace/coverage/default/5.sysrst_ctrl_combo_detect.3235703983 Mar 12 02:49:09 PM PDT 24 Mar 12 02:50:10 PM PDT 24 83996722346 ps
T711 /workspace/coverage/default/48.sysrst_ctrl_pin_override_test.1771511638 Mar 12 02:51:27 PM PDT 24 Mar 12 02:51:34 PM PDT 24 2513259682 ps
T712 /workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.2695924699 Mar 12 02:49:50 PM PDT 24 Mar 12 02:49:53 PM PDT 24 3857425501 ps
T248 /workspace/coverage/default/0.sysrst_ctrl_sec_cm.1171541562 Mar 12 02:48:45 PM PDT 24 Mar 12 02:49:07 PM PDT 24 42164288780 ps
T713 /workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.2881428568 Mar 12 02:50:38 PM PDT 24 Mar 12 02:52:02 PM PDT 24 64351578420 ps
T221 /workspace/coverage/default/32.sysrst_ctrl_edge_detect.1674455814 Mar 12 02:50:39 PM PDT 24 Mar 12 02:50:47 PM PDT 24 2809226086 ps
T714 /workspace/coverage/default/20.sysrst_ctrl_edge_detect.2957433054 Mar 12 02:50:03 PM PDT 24 Mar 12 02:50:06 PM PDT 24 4115844552 ps
T356 /workspace/coverage/default/9.sysrst_ctrl_combo_detect.3812168978 Mar 12 02:49:37 PM PDT 24 Mar 12 02:55:37 PM PDT 24 129233268560 ps
T715 /workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.2562091302 Mar 12 02:50:50 PM PDT 24 Mar 12 02:50:58 PM PDT 24 2467293006 ps
T158 /workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.75679869 Mar 12 02:50:50 PM PDT 24 Mar 12 02:51:38 PM PDT 24 35118832782 ps
T716 /workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.2703628479 Mar 12 02:49:37 PM PDT 24 Mar 12 02:49:42 PM PDT 24 2475621324 ps
T201 /workspace/coverage/default/6.sysrst_ctrl_edge_detect.609831260 Mar 12 02:49:10 PM PDT 24 Mar 12 02:49:13 PM PDT 24 3416179329 ps
T717 /workspace/coverage/default/48.sysrst_ctrl_alert_test.2834773460 Mar 12 02:51:29 PM PDT 24 Mar 12 02:51:31 PM PDT 24 2042574038 ps
T718 /workspace/coverage/default/24.sysrst_ctrl_pin_access_test.53156935 Mar 12 02:50:06 PM PDT 24 Mar 12 02:50:09 PM PDT 24 2244469118 ps
T338 /workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.4094410744 Mar 12 02:51:43 PM PDT 24 Mar 12 02:52:58 PM PDT 24 127353895528 ps
T719 /workspace/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.3076263335 Mar 12 02:48:56 PM PDT 24 Mar 12 02:49:04 PM PDT 24 2612169487 ps
T267 /workspace/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.1165028513 Mar 12 02:48:51 PM PDT 24 Mar 12 02:49:07 PM PDT 24 28081767892 ps
T720 /workspace/coverage/default/4.sysrst_ctrl_pin_access_test.1496881589 Mar 12 02:49:02 PM PDT 24 Mar 12 02:49:04 PM PDT 24 2256349053 ps
T721 /workspace/coverage/default/30.sysrst_ctrl_pin_access_test.2351054727 Mar 12 02:50:31 PM PDT 24 Mar 12 02:50:37 PM PDT 24 2149148011 ps
T722 /workspace/coverage/default/26.sysrst_ctrl_pin_access_test.2726859944 Mar 12 02:50:14 PM PDT 24 Mar 12 02:50:16 PM PDT 24 2244033182 ps
T723 /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.3352295532 Mar 12 02:48:50 PM PDT 24 Mar 12 02:48:53 PM PDT 24 2473284274 ps
T724 /workspace/coverage/default/35.sysrst_ctrl_pin_access_test.645797540 Mar 12 02:50:48 PM PDT 24 Mar 12 02:50:52 PM PDT 24 2174285243 ps
T57 /workspace/coverage/default/0.sysrst_ctrl_feature_disable.2257668774 Mar 12 02:48:42 PM PDT 24 Mar 12 02:50:20 PM PDT 24 40162752358 ps
T725 /workspace/coverage/default/25.sysrst_ctrl_smoke.4204481692 Mar 12 02:50:08 PM PDT 24 Mar 12 02:50:10 PM PDT 24 2185051816 ps
T726 /workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.249202425 Mar 12 02:48:55 PM PDT 24 Mar 12 02:49:06 PM PDT 24 50839740723 ps
T147 /workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.3735898142 Mar 12 02:51:25 PM PDT 24 Mar 12 02:51:29 PM PDT 24 6914859109 ps
T191 /workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.289109792 Mar 12 02:49:22 PM PDT 24 Mar 12 02:50:09 PM PDT 24 36068651315 ps
T727 /workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.3969659912 Mar 12 02:50:16 PM PDT 24 Mar 12 02:50:18 PM PDT 24 2636827376 ps
T728 /workspace/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.1978736539 Mar 12 02:49:29 PM PDT 24 Mar 12 02:49:33 PM PDT 24 2616083124 ps
T268 /workspace/coverage/default/1.sysrst_ctrl_sec_cm.2453242092 Mar 12 02:48:51 PM PDT 24 Mar 12 02:49:51 PM PDT 24 22012072352 ps
T729 /workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.3274204345 Mar 12 02:51:11 PM PDT 24 Mar 12 02:51:18 PM PDT 24 2445145566 ps
T730 /workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.3530254418 Mar 12 02:51:05 PM PDT 24 Mar 12 02:51:15 PM PDT 24 3106367194 ps
T731 /workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.472497735 Mar 12 02:49:55 PM PDT 24 Mar 12 02:49:58 PM PDT 24 2472312384 ps
T732 /workspace/coverage/default/30.sysrst_ctrl_smoke.2953906039 Mar 12 02:50:33 PM PDT 24 Mar 12 02:50:40 PM PDT 24 2112224844 ps
T733 /workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.1931191587 Mar 12 02:49:01 PM PDT 24 Mar 12 02:49:05 PM PDT 24 2464908355 ps
T363 /workspace/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.3984694737 Mar 12 02:49:34 PM PDT 24 Mar 12 02:51:55 PM PDT 24 51786583298 ps
T734 /workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.4057814396 Mar 12 02:50:43 PM PDT 24 Mar 12 02:50:53 PM PDT 24 3162117131 ps
T735 /workspace/coverage/default/28.sysrst_ctrl_in_out_inverted.1044608575 Mar 12 02:50:22 PM PDT 24 Mar 12 02:50:24 PM PDT 24 2493131760 ps
T736 /workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.3505532854 Mar 12 02:49:56 PM PDT 24 Mar 12 02:49:58 PM PDT 24 3203317447 ps
T737 /workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.876450382 Mar 12 02:50:06 PM PDT 24 Mar 12 02:50:18 PM PDT 24 4320992238 ps
T738 /workspace/coverage/default/12.sysrst_ctrl_pin_override_test.1781195071 Mar 12 02:49:46 PM PDT 24 Mar 12 02:49:49 PM PDT 24 2540755493 ps
T739 /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1531470423 Mar 12 02:48:57 PM PDT 24 Mar 12 02:48:59 PM PDT 24 2271058520 ps
T740 /workspace/coverage/default/0.sysrst_ctrl_pin_access_test.3120186451 Mar 12 02:48:44 PM PDT 24 Mar 12 02:48:46 PM PDT 24 2099333381 ps
T171 /workspace/coverage/default/42.sysrst_ctrl_stress_all.902348920 Mar 12 02:51:05 PM PDT 24 Mar 12 02:51:09 PM PDT 24 9409475721 ps
T741 /workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.923111663 Mar 12 02:50:17 PM PDT 24 Mar 12 02:50:24 PM PDT 24 2465691617 ps
T742 /workspace/coverage/default/3.sysrst_ctrl_pin_override_test.4167567398 Mar 12 02:49:03 PM PDT 24 Mar 12 02:49:11 PM PDT 24 2508296918 ps
T292 /workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.882820080 Mar 12 02:50:23 PM PDT 24 Mar 12 02:51:24 PM PDT 24 24314372156 ps
T743 /workspace/coverage/default/21.sysrst_ctrl_alert_test.1733873186 Mar 12 02:50:01 PM PDT 24 Mar 12 02:50:03 PM PDT 24 2067611034 ps
T744 /workspace/coverage/default/4.sysrst_ctrl_smoke.3518644186 Mar 12 02:48:57 PM PDT 24 Mar 12 02:48:59 PM PDT 24 2125975958 ps
T745 /workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.196846957 Mar 12 02:49:50 PM PDT 24 Mar 12 02:51:04 PM PDT 24 96212854923 ps
T746 /workspace/coverage/default/22.sysrst_ctrl_pin_access_test.2093129290 Mar 12 02:50:06 PM PDT 24 Mar 12 02:50:13 PM PDT 24 2108190812 ps
T747 /workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.867535334 Mar 12 02:51:11 PM PDT 24 Mar 12 02:51:15 PM PDT 24 4306447249 ps
T748 /workspace/coverage/default/21.sysrst_ctrl_combo_detect.1799337624 Mar 12 02:50:02 PM PDT 24 Mar 12 02:55:27 PM PDT 24 130883423395 ps
T749 /workspace/coverage/default/22.sysrst_ctrl_smoke.3497819579 Mar 12 02:50:07 PM PDT 24 Mar 12 02:50:14 PM PDT 24 2111300573 ps
T750 /workspace/coverage/default/13.sysrst_ctrl_auto_blk_key_output.4069606480 Mar 12 02:49:41 PM PDT 24 Mar 12 02:49:49 PM PDT 24 3003654341 ps
T751 /workspace/coverage/default/34.sysrst_ctrl_alert_test.3509225743 Mar 12 02:50:44 PM PDT 24 Mar 12 02:50:49 PM PDT 24 2010600303 ps
T752 /workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.3025156391 Mar 12 02:51:12 PM PDT 24 Mar 12 02:51:20 PM PDT 24 5096650118 ps
T753 /workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.254496421 Mar 12 02:49:24 PM PDT 24 Mar 12 02:49:28 PM PDT 24 5374278260 ps
T754 /workspace/coverage/default/1.sysrst_ctrl_edge_detect.1866408550 Mar 12 02:48:50 PM PDT 24 Mar 12 02:48:53 PM PDT 24 4215953294 ps
T755 /workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.387103190 Mar 12 02:50:08 PM PDT 24 Mar 12 02:50:12 PM PDT 24 4476298662 ps
T756 /workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.3997465651 Mar 12 02:50:21 PM PDT 24 Mar 12 02:50:29 PM PDT 24 2614093157 ps
T757 /workspace/coverage/default/28.sysrst_ctrl_ultra_low_pwr.1095808427 Mar 12 02:50:23 PM PDT 24 Mar 12 02:50:30 PM PDT 24 7884280996 ps
T364 /workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.2061623308 Mar 12 02:51:42 PM PDT 24 Mar 12 02:55:36 PM PDT 24 85142270930 ps
T758 /workspace/coverage/default/17.sysrst_ctrl_pin_override_test.1775331878 Mar 12 02:49:52 PM PDT 24 Mar 12 02:49:54 PM PDT 24 2525289074 ps
T759 /workspace/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.2515063359 Mar 12 02:49:34 PM PDT 24 Mar 12 02:51:13 PM PDT 24 43352649677 ps
T760 /workspace/coverage/default/38.sysrst_ctrl_alert_test.616596955 Mar 12 02:50:58 PM PDT 24 Mar 12 02:51:02 PM PDT 24 2016429023 ps
T761 /workspace/coverage/default/29.sysrst_ctrl_stress_all.1005338051 Mar 12 02:50:27 PM PDT 24 Mar 12 02:50:44 PM PDT 24 7062672214 ps
T762 /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3079759208 Mar 12 02:49:02 PM PDT 24 Mar 12 02:49:03 PM PDT 24 2622130505 ps
T269 /workspace/coverage/default/2.sysrst_ctrl_sec_cm.2850038933 Mar 12 02:48:55 PM PDT 24 Mar 12 02:49:17 PM PDT 24 42156598576 ps
T763 /workspace/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.1012501036 Mar 12 02:48:48 PM PDT 24 Mar 12 02:48:55 PM PDT 24 4109525224 ps
T764 /workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.610844682 Mar 12 02:51:16 PM PDT 24 Mar 12 02:51:29 PM PDT 24 4788941024 ps
T765 /workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.1302217530 Mar 12 02:50:37 PM PDT 24 Mar 12 02:50:38 PM PDT 24 4869324764 ps
T766 /workspace/coverage/default/14.sysrst_ctrl_pin_access_test.3877377564 Mar 12 02:49:49 PM PDT 24 Mar 12 02:49:52 PM PDT 24 2159719021 ps
T767 /workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.3792881757 Mar 12 02:48:57 PM PDT 24 Mar 12 02:49:02 PM PDT 24 3252153261 ps
T768 /workspace/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.3972129702 Mar 12 02:49:44 PM PDT 24 Mar 12 02:49:51 PM PDT 24 2608108497 ps
T769 /workspace/coverage/default/35.sysrst_ctrl_ultra_low_pwr.838340368 Mar 12 02:50:46 PM PDT 24 Mar 12 02:50:53 PM PDT 24 3376059230 ps
T770 /workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.2913564648 Mar 12 02:50:15 PM PDT 24 Mar 12 02:52:32 PM PDT 24 2782306586006 ps
T771 /workspace/coverage/default/42.sysrst_ctrl_smoke.113710084 Mar 12 02:51:03 PM PDT 24 Mar 12 02:51:05 PM PDT 24 2121217830 ps
T772 /workspace/coverage/default/36.sysrst_ctrl_edge_detect.2406327412 Mar 12 02:50:55 PM PDT 24 Mar 12 02:50:58 PM PDT 24 3769625232 ps
T773 /workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.4229435894 Mar 12 02:51:37 PM PDT 24 Mar 12 02:51:58 PM PDT 24 30100051870 ps
T774 /workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.2123344810 Mar 12 02:51:32 PM PDT 24 Mar 12 02:52:16 PM PDT 24 63037499618 ps
T775 /workspace/coverage/default/20.sysrst_ctrl_alert_test.4230663483 Mar 12 02:50:03 PM PDT 24 Mar 12 02:50:06 PM PDT 24 2053316752 ps
T776 /workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.557680140 Mar 12 02:50:01 PM PDT 24 Mar 12 02:50:04 PM PDT 24 2630427156 ps
T777 /workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.3578801645 Mar 12 02:51:04 PM PDT 24 Mar 12 02:51:07 PM PDT 24 10449032959 ps
T778 /workspace/coverage/default/18.sysrst_ctrl_edge_detect.2714812387 Mar 12 02:49:56 PM PDT 24 Mar 12 02:49:59 PM PDT 24 4481976257 ps
T779 /workspace/coverage/default/16.sysrst_ctrl_combo_detect.4259404108 Mar 12 02:49:49 PM PDT 24 Mar 12 02:52:16 PM PDT 24 54856021018 ps
T780 /workspace/coverage/default/28.sysrst_ctrl_edge_detect.3256484531 Mar 12 02:50:22 PM PDT 24 Mar 12 02:50:32 PM PDT 24 4138947958 ps
T781 /workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.2471780220 Mar 12 02:51:07 PM PDT 24 Mar 12 02:51:17 PM PDT 24 3441709265 ps
T782 /workspace/coverage/default/35.sysrst_ctrl_combo_detect.1292177345 Mar 12 02:50:55 PM PDT 24 Mar 12 02:58:03 PM PDT 24 159840993376 ps
T783 /workspace/coverage/default/49.sysrst_ctrl_combo_detect.4238663114 Mar 12 02:51:26 PM PDT 24 Mar 12 02:54:30 PM PDT 24 129540912544 ps
T129 /workspace/coverage/default/36.sysrst_ctrl_ultra_low_pwr.2409159799 Mar 12 02:50:55 PM PDT 24 Mar 12 02:51:03 PM PDT 24 7504749508 ps
T784 /workspace/coverage/default/8.sysrst_ctrl_combo_detect.420972311 Mar 12 02:49:29 PM PDT 24 Mar 12 02:49:43 PM PDT 24 28795627127 ps
T785 /workspace/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.1175568706 Mar 12 02:50:23 PM PDT 24 Mar 12 02:51:18 PM PDT 24 79959130792 ps
T786 /workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.27081514 Mar 12 02:48:55 PM PDT 24 Mar 12 02:49:01 PM PDT 24 2461980001 ps
T787 /workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.513948298 Mar 12 02:48:42 PM PDT 24 Mar 12 02:48:50 PM PDT 24 2453962424 ps
T130 /workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.1825998242 Mar 12 02:49:40 PM PDT 24 Mar 12 02:49:47 PM PDT 24 2795318823408 ps
T788 /workspace/coverage/default/45.sysrst_ctrl_pin_override_test.1947205061 Mar 12 02:51:13 PM PDT 24 Mar 12 02:51:17 PM PDT 24 2523155973 ps
T789 /workspace/coverage/default/17.sysrst_ctrl_alert_test.1756960735 Mar 12 02:49:56 PM PDT 24 Mar 12 02:50:02 PM PDT 24 2007886556 ps
T31 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.1519625329 Mar 12 01:04:44 PM PDT 24 Mar 12 01:04:48 PM PDT 24 2154062150 ps
T32 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.2181300939 Mar 12 01:05:00 PM PDT 24 Mar 12 01:05:06 PM PDT 24 2038103157 ps
T790 /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.1964327399 Mar 12 01:05:00 PM PDT 24 Mar 12 01:05:07 PM PDT 24 2013418913 ps
T33 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.662020406 Mar 12 01:04:43 PM PDT 24 Mar 12 01:07:40 PM PDT 24 71873915501 ps
T791 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.2936821005 Mar 12 01:04:56 PM PDT 24 Mar 12 01:05:03 PM PDT 24 2014836113 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%