Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.46	91.46	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	91.46	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.46	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	7	55	88.71

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	7	24	77.42	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1955

1

T1

5

T2

43

T4

6

auto[1]

617

1

T2

21

T7

10

T8

4

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1884

1

T1

3

T2

50

T32

12

auto[1]

688

1

T1

2

T2

14

T4

6

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1903

1

T1

3

T2

64

T4

4

auto[1]

669

1

T1

2

T4

2

T7

10

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1859

1

T2

58

T32

9

T7

9

auto[1]

713

1

T1

5

T2

6

T4

6

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2369

1

T1

5

T2

64

T4

6

auto[1]

203

1

T12

17

T42

20

T72

6

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2445

1

T1

5

T2

56

T4

6

auto[1]

127

1

T2

8

T12

5

T42

8

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2358

1

T1

5

T2

35

T4

6

auto[1]

214

1

T2

29

T32

3

T42

12

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2404

1

T1

5

T2

48

T4

6

auto[1]

168

1

T2

16

T55

1

T72

6

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2353

1

T1

5

T2

58

T4

6

auto[1]

219

1

T2

6

T12

5

T42

2

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1870

1

T2

41

T4

2

T32

9

auto[1]

702

1

T1

5

T2

23

T4

4

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	7	24	77.42	7
Automatically Generated Cross Bins	31	7	24	77.42	7
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	1004	1			T1	5		T4	6		T7	10
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	65	1			T12	10		T72	6		T242	4
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	63	1			T12	2		T74	1		T132	1
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	36	1			T371	14		T85	3		T372	2
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	63	1			T55	1		T72	3		T250	12
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	5	1			T74	1		T80	4		-	-
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	8	1			T373	2		T374	2		T81	3
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	9	1			T249	2		T375	4		T367	3
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	80	1			T2	15		T32	3		T74	1
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	26	1			T42	12		T94	3		T376	1
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	46	1			T2	6		T243	6		T177	3
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	1	1			T373	1		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	13	1			T2	8		T94	2		T377	3
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	2	1			T378	2		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	7	1			T248	6		T371	1		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	42	1			T180	6		T360	2		T379	3
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	14	1			T12	5		T42	6		T177	1
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	9	1			T74	1		T371	4		T372	3
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	7	1			T42	2		T249	3		T380	2
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	18	1			T2	8		T85	2		T381	8
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	5	1			T72	3		T380	2		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[1]	1	1			T320	1		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	17	1			T249	2		T197	4		T382	6
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	1	1			T383	1		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

64

1

T74

1

T132

1

T243

6

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

68

1

T2

8

T27

1

T90

9

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

65

1

T2

15

T211

4

T217

22

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

116

1

T12

10

T249

2

T291

11

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

50

1

T313

3

T384

4

T255

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

70

1

T1

3

T32

3

T11

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

37

1

T52

3

T74

1

T96

5

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

114

1

T11

11

T42

2

T249

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

64

1

T7

6

T8

2

T72

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

78

1

T211

6

T247

7

T40

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

40

1

T211

6

T45

1

T250

6

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

56

1

T11

6

T74

1

T251

8

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

24

1

T8

1

T52

5

T128

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

38

1

T42

6

T177

1

T166

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

12

1

T11

4

T35

1

T40

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

122

1

T2

8

T248

6

T242

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

45

1

T78

5

T83

7

T300

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

83

1

T42

12

T83

6

T300

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

29

1

T247

5

T217

4

T97

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

100

1

T12

2

T247

4

T300

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

36

1

T2

6

T83

5

T136

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

24

1

T4

4

T376

1

T380

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

24

1

T8

1

T35

4

T247

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

42

1

T55

1

T45

3

T74

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

29

1

T7

3

T359

3

T167

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

23

1

T72

6

T300

2

T131

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

20

1

T10

3

T72

3

T92

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

32

1

T4

2

T371

7

T167

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

26

1

T7

1

T52

8

T83

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

8

1

T1

2

T358

4

T265

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

3

1

T40

1

T385

1

T363

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded