Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

990

1

T1

19

T19

10

T30

10

auto[1]

1019

1

T1

21

T19

10

T30

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

491

1

T1

12

T19

6

T30

5

from_0to1

486

1

T1

12

T19

6

T30

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1013

1

T1

25

T19

10

T30

11

auto[1]

996

1

T1

15

T19

10

T30

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

995

1

T1

17

T19

7

T30

13

auto[1]

1014

1

T1

23

T19

13

T30

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

74

1

T1

1

T19

3

T43

1

auto[0]

from_1to0

auto[0]

auto[1]

54

1

T1

3

T43

1

T210

1

auto[0]

from_1to0

auto[1]

auto[0]

53

1

T1

1

T19

1

T30

1

auto[0]

from_1to0

auto[1]

auto[1]

59

1

T43

1

T65

1

T396

1

auto[0]

from_0to1

auto[0]

auto[0]

58

1

T1

2

T30

3

T43

1

auto[0]

from_0to1

auto[0]

auto[1]

57

1

T30

1

T67

1

T69

1

auto[0]

from_0to1

auto[1]

auto[0]

62

1

T1

1

T43

1

T67

2

auto[0]

from_0to1

auto[1]

auto[1]

57

1

T1

2

T19

2

T30

1

auto[1]

from_1to0

auto[0]

auto[0]

67

1

T1

2

T69

3

T210

2

auto[1]

from_1to0

auto[0]

auto[1]

56

1

T1

3

T19

1

T30

1

auto[1]

from_1to0

auto[1]

auto[0]

60

1

T1

1

T30

2

T43

1

auto[1]

from_1to0

auto[1]

auto[1]

68

1

T1

1

T19

1

T30

1

auto[1]

from_0to1

auto[0]

auto[0]

55

1

T1

2

T19

1

T302

1

auto[1]

from_0to1

auto[0]

auto[1]

71

1

T1

1

T19

2

T210

3

auto[1]

from_0to1

auto[1]

auto[0]

70

1

T1

3

T67

1

T69

1

auto[1]

from_0to1

auto[1]

auto[1]

56

1

T1

1

T19

1

T43

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

998

1

T1

22

T19

12

T30

8

auto[1]

1011

1

T1

18

T19

8

T30

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

497

1

T1

10

T19

4

T30

6

from_0to1

494

1

T1

10

T19

3

T30

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1022

1

T1

23

T19

10

T30

13

auto[1]

987

1

T1

17

T19

10

T30

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1008

1

T1

19

T19

12

T30

7

auto[1]

1001

1

T1

21

T19

8

T30

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

67

1

T1

2

T30

1

T43

3

auto[0]

from_1to0

auto[0]

auto[1]

58

1

T1

1

T19

1

T67

1

auto[0]

from_1to0

auto[1]

auto[0]

60

1

T1

1

T19

1

T67

1

auto[0]

from_1to0

auto[1]

auto[1]

72

1

T1

1

T19

1

T30

1

auto[0]

from_0to1

auto[0]

auto[0]

68

1

T1

2

T19

1

T43

2

auto[0]

from_0to1

auto[0]

auto[1]

56

1

T30

3

T67

1

T65

3

auto[0]

from_0to1

auto[1]

auto[0]

67

1

T1

1

T67

1

T208

1

auto[0]

from_0to1

auto[1]

auto[1]

54

1

T1

1

T19

1

T67

1

auto[1]

from_1to0

auto[0]

auto[0]

65

1

T1

1

T30

2

T69

1

auto[1]

from_1to0

auto[0]

auto[1]

67

1

T1

1

T19

1

T30

1

auto[1]

from_1to0

auto[1]

auto[0]

60

1

T1

3

T65

1

T229

1

auto[1]

from_1to0

auto[1]

auto[1]

48

1

T30

1

T67

1

T210

1

auto[1]

from_0to1

auto[0]

auto[0]

52

1

T1

1

T43

1

T69

1

auto[1]

from_0to1

auto[0]

auto[1]

73

1

T1

3

T30

2

T69

1

auto[1]

from_0to1

auto[1]

auto[0]

65

1

T1

1

T19

1

T208

1

auto[1]

from_0to1

auto[1]

auto[1]

59

1

T1

1

T30

1

T43

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1035

1

T1

20

T19

10

T30

12

auto[1]

974

1

T1

20

T19

10

T30

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

486

1

T1

9

T19

5

T30

4

from_0to1

489

1

T1

9

T19

5

T30

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

996

1

T1

19

T19

10

T30

9

auto[1]

1013

1

T1

21

T19

10

T30

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1028

1

T1

23

T19

11

T30

10

auto[1]

981

1

T1

17

T19

9

T30

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

62

1

T30

1

T43

1

T67

1

auto[0]

from_1to0

auto[0]

auto[1]

59

1

T1

1

T69

1

T210

1

auto[0]

from_1to0

auto[1]

auto[0]

77

1

T1

1

T19

2

T43

1

auto[0]

from_1to0

auto[1]

auto[1]

59

1

T1

2

T30

1

T67

1

auto[0]

from_0to1

auto[0]

auto[0]

55

1

T1

1

T67

1

T69

2

auto[0]

from_0to1

auto[0]

auto[1]

48

1

T19

1

T30

2

T43

2

auto[0]

from_0to1

auto[1]

auto[0]

59

1

T1

3

T30

1

T302

2

auto[0]

from_0to1

auto[1]

auto[1]

72

1

T1

1

T19

1

T67

1

auto[1]

from_1to0

auto[0]

auto[0]

46

1

T43

1

T67

1

T40

1

auto[1]

from_1to0

auto[0]

auto[1]

58

1

T1

1

T43

1

T210

1

auto[1]

from_1to0

auto[1]

auto[0]

68

1

T1

3

T19

2

T30

1

auto[1]

from_1to0

auto[1]

auto[1]

57

1

T1

1

T19

1

T30

1

auto[1]

from_0to1

auto[0]

auto[0]

77

1

T1

3

T19

1

T43

1

auto[1]

from_0to1

auto[0]

auto[1]

63

1

T30

1

T43

1

T67

1

auto[1]

from_0to1

auto[1]

auto[0]

57

1

T19

1

T30

1

T43

1

auto[1]

from_0to1

auto[1]

auto[1]

58

1

T1

1

T19

1

T302

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1010

1

T1

18

T19

10

T30

13

auto[1]

999

1

T1

22

T19

10

T30

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

466

1

T1

9

T19

3

T30

4

from_0to1

466

1

T1

9

T19

4

T30

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1023

1

T1

26

T19

16

T30

8

auto[1]

986

1

T1

14

T19

4

T30

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1011

1

T1

19

T19

8

T30

9

auto[1]

998

1

T1

21

T19

12

T30

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

67

1

T1

1

T30

1

T69

1

auto[0]

from_1to0

auto[0]

auto[1]

56

1

T1

1

T19

2

T67

2

auto[0]

from_1to0

auto[1]

auto[0]

53

1

T1

1

T43

1

T208

2

auto[0]

from_1to0

auto[1]

auto[1]

59

1

T30

1

T302

1

T210

2

auto[0]

from_0to1

auto[0]

auto[0]

56

1

T43

1

T302

1

T396

1

auto[0]

from_0to1

auto[0]

auto[1]

67

1

T1

1

T19

3

T69

1

auto[0]

from_0to1

auto[1]

auto[0]

54

1

T208

1

T210

1

T65

1

auto[0]

from_0to1

auto[1]

auto[1]

54

1

T1

2

T30

2

T43

1

auto[1]

from_1to0

auto[0]

auto[0]

57

1

T19

1

T67

1

T302

1

auto[1]

from_1to0

auto[0]

auto[1]

63

1

T1

4

T69

1

T302

2

auto[1]

from_1to0

auto[1]

auto[0]

58

1

T30

1

T302

1

T208

1

auto[1]

from_1to0

auto[1]

auto[1]

53

1

T1

2

T30

1

T43

2

auto[1]

from_0to1

auto[0]

auto[0]

52

1

T1

3

T30

1

T43

1

auto[1]

from_0to1

auto[0]

auto[1]

63

1

T1

1

T43

1

T67

1

auto[1]

from_0to1

auto[1]

auto[0]

61

1

T30

1

T67

1

T210

1

auto[1]

from_0to1

auto[1]

auto[1]

59

1

T1

2

T19

1

T30

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

993

1

T1

19

T19

12

T30

13

auto[1]

1016

1

T1

21

T19

8

T30

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

494

1

T1

7

T19

5

T30

4

from_0to1

494

1

T1

8

T19

6

T30

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1025

1

T1

18

T19

10

T30

7

auto[1]

984

1

T1

22

T19

10

T30

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1023

1

T1

22

T19

11

T30

11

auto[1]

986

1

T1

18

T19

9

T30

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

64

1

T1

2

T19

1

T30

1

auto[0]

from_1to0

auto[0]

auto[1]

67

1

T67

1

T69

2

T302

2

auto[0]

from_1to0

auto[1]

auto[0]

65

1

T1

1

T19

1

T30

1

auto[0]

from_1to0

auto[1]

auto[1]

54

1

T1

1

T302

1

T65

1

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T1

2

T30

1

T67

1

auto[0]

from_0to1

auto[0]

auto[1]

79

1

T1

1

T19

2

T43

1

auto[0]

from_0to1

auto[1]

auto[0]

62

1

T19

1

T30

1

T43

1

auto[0]

from_0to1

auto[1]

auto[1]

43

1

T19

2

T43

1

T69

2

auto[1]

from_1to0

auto[0]

auto[0]

56

1

T1

1

T43

1

T67

1

auto[1]

from_1to0

auto[0]

auto[1]

59

1

T1

1

T43

1

T67

1

auto[1]

from_1to0

auto[1]

auto[0]

60

1

T1

1

T19

3

T30

1

auto[1]

from_1to0

auto[1]

auto[1]

69

1

T30

1

T67

1

T69

1

auto[1]

from_0to1

auto[0]

auto[0]

54

1

T19

1

T43

1

T302

1

auto[1]

from_0to1

auto[0]

auto[1]

60

1

T30

1

T67

1

T69

2

auto[1]

from_0to1

auto[1]

auto[0]

73

1

T1

3

T43

1

T69

1

auto[1]

from_0to1

auto[1]

auto[1]

60

1

T1

2

T30

1

T302

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1006

1

T1

17

T19

13

T30

11

auto[1]

1003

1

T1

23

T19

7

T30

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

475

1

T1

12

T19

5

T30

6

from_0to1

482

1

T1

12

T19

4

T30

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1005

1

T1

18

T19

8

T30

5

auto[1]

1004

1

T1

22

T19

12

T30

15

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

960

1

T1

21

T19

6

T30

10

auto[1]

1049

1

T1

19

T19

14

T30

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

66

1

T1

1

T30

1

T43

1

auto[0]

from_1to0

auto[0]

auto[1]

61

1

T1

2

T19

1

T67

1

auto[0]

from_1to0

auto[1]

auto[0]

58

1

T1

2

T19

1

T30

2

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T1

1

T19

1

T43

1

auto[0]

from_0to1

auto[0]

auto[0]

60

1

T19

1

T43

2

T67

1

auto[0]

from_0to1

auto[0]

auto[1]

53

1

T1

1

T19

1

T67

1

auto[0]

from_0to1

auto[1]

auto[0]

73

1

T1

4

T30

2

T43

1

auto[0]

from_0to1

auto[1]

auto[1]

54

1

T30

3

T67

1

T69

2

auto[1]

from_1to0

auto[0]

auto[0]

45

1

T1

1

T69

2

T104

1

auto[1]

from_1to0

auto[0]

auto[1]

68

1

T1

2

T30

1

T67

2

auto[1]

from_1to0

auto[1]

auto[0]

57

1

T1

1

T19

1

T302

1

auto[1]

from_1to0

auto[1]

auto[1]

58

1

T1

2

T19

1

T30

2

auto[1]

from_0to1

auto[0]

auto[0]

56

1

T1

2

T67

1

T69

1

auto[1]

from_0to1

auto[0]

auto[1]

73

1

T1

2

T19

1

T302

1

auto[1]

from_0to1

auto[1]

auto[0]

46

1

T1

1

T19

1

T30

1

auto[1]

from_0to1

auto[1]

auto[1]

67

1

T1

2

T30

1

T69

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1000

1

T1

27

T19

13

T30

11

auto[1]

1009

1

T1

13

T19

7

T30

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

481

1

T1

11

T19

3

T30

5

from_0to1

475

1

T1

11

T19

4

T30

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

990

1

T1

16

T19

12

T30

8

auto[1]

1019

1

T1

24

T19

8

T30

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

972

1

T1

18

T19

15

T30

13

auto[1]

1037

1

T1

22

T19

5

T30

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

58

1

T43

1

T69

2

T208

1

auto[0]

from_1to0

auto[0]

auto[1]

62

1

T1

3

T43

1

T67

1

auto[0]

from_1to0

auto[1]

auto[0]

66

1

T1

1

T19

1

T67

1

auto[0]

from_1to0

auto[1]

auto[1]

66

1

T1

3

T19

1

T30

2

auto[0]

from_0to1

auto[0]

auto[0]

58

1

T1

3

T19

4

T30

1

auto[0]

from_0to1

auto[0]

auto[1]

59

1

T1

3

T67

1

T302

1

auto[0]

from_0to1

auto[1]

auto[0]

56

1

T1

1

T30

1

T302

1

auto[0]

from_0to1

auto[1]

auto[1]

59

1

T1

2

T30

1

T69

1

auto[1]

from_1to0

auto[0]

auto[0]

58

1

T1

1

T30

1

T67

2

auto[1]

from_1to0

auto[0]

auto[1]

57

1

T43

1

T69

1

T302

1

auto[1]

from_1to0

auto[1]

auto[0]

60

1

T1

1

T19

1

T30

1

auto[1]

from_1to0

auto[1]

auto[1]

54

1

T1

2

T30

1

T43

2

auto[1]

from_0to1

auto[0]

auto[0]

44

1

T30

1

T43

1

T40

1

auto[1]

from_0to1

auto[0]

auto[1]

70

1

T30

1

T43

3

T302

1

auto[1]

from_0to1

auto[1]

auto[0]

69

1

T1

1

T43

1

T67

2

auto[1]

from_0to1

auto[1]

auto[1]

60

1

T1

1

T67

1

T302

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

986

1

T1

21

T19

10

T30

8

auto[1]

1023

1

T1

19

T19

10

T30

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

463

1

T1

9

T19

4

T30

7

from_0to1

473

1

T1

10

T19

4

T30

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1015

1

T1

20

T19

11

T30

10

auto[1]

994

1

T1

20

T19

9

T30

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

995

1

T1

20

T19

11

T30

9

auto[1]

1014

1

T1

20

T19

9

T30

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

51

1

T19

2

T43

2

T210

1

auto[0]

from_1to0

auto[0]

auto[1]

69

1

T1

1

T19

1

T30

1

auto[0]

from_1to0

auto[1]

auto[0]

55

1

T1

3

T43

1

T67

1

auto[0]

from_1to0

auto[1]

auto[1]

50

1

T19

1

T30

2

T302

1

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T1

2

T30

1

T43

1

auto[0]

from_0to1

auto[0]

auto[1]

61

1

T1

2

T30

1

T43

1

auto[0]

from_0to1

auto[1]

auto[0]

54

1

T1

1

T30

1

T67

3

auto[0]

from_0to1

auto[1]

auto[1]

58

1

T1

2

T30

1

T69

1

auto[1]

from_1to0

auto[0]

auto[0]

51

1

T30

1

T43

1

T67

3

auto[1]

from_1to0

auto[0]

auto[1]

64

1

T1

3

T30

2

T43

2

auto[1]

from_1to0

auto[1]

auto[0]

62

1

T302

1

T210

3

T106

1

auto[1]

from_1to0

auto[1]

auto[1]

61

1

T1

2

T30

1

T67

1

auto[1]

from_0to1

auto[0]

auto[0]

69

1

T1

1

T19

3

T30

1

auto[1]

from_0to1

auto[0]

auto[1]

63

1

T30

1

T302

2

T210

1

auto[1]

from_0to1

auto[1]

auto[0]

52

1

T1

1

T19

1

T30

1

auto[1]

from_0to1

auto[1]

auto[1]

53

1

T1

1

T43

1

T210

2