Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	157428	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

120811

1

T5

1

T6

8

T1

345

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	146535	1			T5	2		T6	8		T1	471
values[0x0]	65684	1			T6	4		T1	137		T13	6
values[0x1]	66020	1			T5	1		T6	6		T1	137

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	127580	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

150659

1

T5

1

T6

11

T1

417

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	848	1			T4	7		T43	2		T12	13
valid_sources[0x01]	895	1			T19	1		T4	2		T8	5
valid_sources[0x02]	1161	1			T19	1		T43	2		T8	1
valid_sources[0x03]	1100	1			T1	24		T15	1		T4	2
valid_sources[0x04]	991	1			T4	3		T29	1		T67	12
valid_sources[0x05]	1097	1			T8	4		T68	2		T11	3
valid_sources[0x06]	1010	1			T1	12		T15	1		T4	6
valid_sources[0x07]	1066	1			T51	1		T43	2		T8	5
valid_sources[0x08]	828	1			T4	1		T43	1		T8	2
valid_sources[0x09]	1795	1			T4	2		T43	1		T8	2
valid_sources[0x0a]	1897	1			T4	2		T43	4		T8	2
valid_sources[0x0b]	1428	1			T19	2		T43	1		T8	1
valid_sources[0x0c]	763	1			T1	8		T8	2		T68	1
valid_sources[0x0d]	911	1			T1	27		T4	2		T43	3
valid_sources[0x0e]	1268	1			T4	1		T43	3		T8	2
valid_sources[0x0f]	728	1			T4	2		T43	1		T10	5
valid_sources[0x10]	892	1			T4	2		T8	1		T10	1
valid_sources[0x11]	852	1			T4	2		T43	3		T66	3
valid_sources[0x12]	1047	1			T1	7		T4	1		T8	2
valid_sources[0x13]	973	1			T19	2		T43	1		T68	1
valid_sources[0x14]	1038	1			T4	4		T43	1		T66	1
valid_sources[0x15]	766	1			T4	4		T29	1		T30	1
valid_sources[0x16]	959	1			T4	3		T43	1		T66	1
valid_sources[0x17]	737	1			T4	2		T29	2		T43	2
valid_sources[0x18]	1549	1			T4	3		T32	853		T29	1
valid_sources[0x19]	1804	1			T14	5		T4	3		T43	1
valid_sources[0x1a]	2263	1			T19	1		T30	1		T8	1
valid_sources[0x1b]	1001	1			T19	4		T43	1		T8	9
valid_sources[0x1c]	1042	1			T4	1		T29	1		T8	4
valid_sources[0x1d]	833	1			T17	2		T4	1		T43	1
valid_sources[0x1e]	922	1			T4	4		T43	1		T8	1
valid_sources[0x1f]	961	1			T43	1		T8	3		T12	3
valid_sources[0x20]	1151	1			T4	2		T43	3		T8	8
valid_sources[0x21]	1016	1			T4	6		T43	3		T8	3
valid_sources[0x22]	987	1			T4	1		T43	2		T8	3
valid_sources[0x23]	1004	1			T4	1		T43	2		T31	1
valid_sources[0x24]	850	1			T4	1		T43	2		T8	1
valid_sources[0x25]	901	1			T17	1		T4	3		T43	2
valid_sources[0x26]	2128	1			T4	3		T43	3		T8	1
valid_sources[0x27]	1023	1			T1	9		T4	1		T43	4
valid_sources[0x28]	764	1			T4	2		T43	1		T8	5
valid_sources[0x29]	1404	1			T4	1		T43	1		T66	3
valid_sources[0x2a]	1125	1			T4	5		T43	1		T67	16
valid_sources[0x2b]	935	1			T4	5		T30	1		T43	3
valid_sources[0x2c]	1027	1			T1	16		T19	2		T43	2
valid_sources[0x2d]	1203	1			T1	32		T4	2		T29	1
valid_sources[0x2e]	817	1			T16	2		T17	3		T19	3
valid_sources[0x2f]	919	1			T4	2		T43	3		T66	2
valid_sources[0x30]	1340	1			T1	57		T19	2		T4	1
valid_sources[0x31]	843	1			T3	1		T43	2		T66	2
valid_sources[0x32]	922	1			T17	1		T4	5		T30	1
valid_sources[0x33]	781	1			T17	1		T4	4		T43	2
valid_sources[0x34]	978	1			T4	3		T8	1		T68	1
valid_sources[0x35]	919	1			T4	2		T8	3		T35	2
valid_sources[0x36]	1520	1			T1	1		T3	1		T4	6
valid_sources[0x37]	979	1			T43	2		T8	1		T12	25
valid_sources[0x38]	749	1			T43	2		T8	2		T10	8
valid_sources[0x39]	1013	1			T1	13		T19	4		T4	2
valid_sources[0x3a]	982	1			T1	32		T4	1		T8	1
valid_sources[0x3b]	753	1			T15	3		T4	2		T8	1
valid_sources[0x3c]	1214	1			T4	3		T43	2		T66	1
valid_sources[0x3d]	1051	1			T1	9		T16	2		T19	2
valid_sources[0x3e]	891	1			T19	2		T4	2		T29	2
valid_sources[0x3f]	836	1			T1	3		T3	3		T66	2
valid_sources[0x40]	1665	1			T19	1		T4	2		T302	1
valid_sources[0x41]	2082	1			T3	1		T4	3		T43	1
valid_sources[0x42]	1039	1			T4	1		T29	1		T10	3
valid_sources[0x43]	961	1			T1	1		T4	4		T29	3
valid_sources[0x44]	1270	1			T4	1		T43	2		T66	1
valid_sources[0x45]	889	1			T1	1		T4	1		T43	1
valid_sources[0x46]	1374	1			T30	5		T43	1		T8	4
valid_sources[0x47]	1103	1			T4	2		T30	1		T8	3
valid_sources[0x48]	1502	1			T19	1		T4	1		T8	2
valid_sources[0x49]	974	1			T15	1		T8	2		T10	6
valid_sources[0x4a]	872	1			T19	2		T4	8		T43	2
valid_sources[0x4b]	869	1			T4	1		T10	9		T70	2
valid_sources[0x4c]	1018	1			T1	3		T4	4		T8	1
valid_sources[0x4d]	786	1			T3	1		T19	1		T4	2
valid_sources[0x4e]	918	1			T4	1		T43	2		T67	3
valid_sources[0x4f]	827	1			T4	8		T10	3		T11	5
valid_sources[0x50]	984	1			T4	3		T29	1		T43	1
valid_sources[0x51]	716	1			T19	1		T4	1		T43	1
valid_sources[0x52]	1293	1			T4	7		T43	2		T31	1
valid_sources[0x53]	1180	1			T1	8		T4	1		T43	2
valid_sources[0x54]	1263	1			T1	24		T43	3		T8	1
valid_sources[0x55]	1092	1			T1	9		T8	1		T10	9
valid_sources[0x56]	1105	1			T17	1		T30	4		T43	3
valid_sources[0x57]	1183	1			T43	4		T8	1		T12	4
valid_sources[0x58]	1062	1			T8	2		T302	5		T12	2
valid_sources[0x59]	1247	1			T30	1		T43	1		T8	1
valid_sources[0x5a]	891	1			T51	2		T4	2		T30	5
valid_sources[0x5b]	1002	1			T19	1		T4	5		T43	1
valid_sources[0x5c]	902	1			T43	3		T8	2		T12	6
valid_sources[0x5d]	1100	1			T5	3		T4	5		T29	1
valid_sources[0x5e]	898	1			T4	4		T30	3		T69	13
valid_sources[0x5f]	821	1			T1	6		T19	2		T4	1
valid_sources[0x60]	845	1			T19	1		T4	4		T43	4
valid_sources[0x61]	2040	1			T4	1		T30	1		T43	1
valid_sources[0x62]	989	1			T43	2		T66	1		T8	1
valid_sources[0x63]	966	1			T1	29		T29	1		T8	3
valid_sources[0x64]	913	1			T4	1		T43	8		T8	4
valid_sources[0x65]	1887	1			T43	2		T8	2		T303	1
valid_sources[0x66]	1384	1			T16	1		T19	1		T4	1
valid_sources[0x67]	746	1			T17	1		T43	2		T8	1
valid_sources[0x68]	1080	1			T3	1		T19	2		T4	4
valid_sources[0x69]	902	1			T3	1		T19	4		T4	3
valid_sources[0x6a]	743	1			T19	1		T4	2		T28	45
valid_sources[0x6b]	1409	1			T19	1		T66	1		T8	1
valid_sources[0x6c]	875	1			T4	2		T43	1		T8	1
valid_sources[0x6d]	953	1			T1	10		T30	12		T43	2
valid_sources[0x6e]	904	1			T29	1		T8	4		T62	1
valid_sources[0x6f]	875	1			T43	1		T8	3		T11	3
valid_sources[0x70]	1133	1			T43	3		T8	5		T11	14
valid_sources[0x71]	969	1			T4	1		T30	7		T43	3
valid_sources[0x72]	751	1			T4	1		T43	2		T66	1
valid_sources[0x73]	814	1			T4	1		T43	3		T8	4
valid_sources[0x74]	954	1			T1	9		T3	2		T19	1
valid_sources[0x75]	1015	1			T4	1		T43	3		T8	3
valid_sources[0x76]	857	1			T17	1		T30	1		T66	1
valid_sources[0x77]	790	1			T4	1		T29	3		T8	4
valid_sources[0x78]	1069	1			T43	3		T31	1		T62	1
valid_sources[0x79]	2189	1			T4	2		T43	1		T8	1
valid_sources[0x7a]	1163	1			T1	22		T43	3		T8	1
valid_sources[0x7b]	889	1			T51	3		T4	4		T43	2
valid_sources[0x7c]	1170	1			T43	1		T66	1		T10	6
valid_sources[0x7d]	1704	1			T4	1		T43	6		T8	2
valid_sources[0x7e]	732	1			T4	4		T8	1		T302	4
valid_sources[0x7f]	1155	1			T4	4		T43	1		T8	1
valid_sources[0x80]	673	1			T4	1		T30	10		T43	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

67035

1

T5

1

T6

4

T1

239

values[0x0]

all_enables

biggest_size

31615

1

T6

2

T1

63

T13

2

values[0x1]

all_enables

biggest_size

22161

1

T6

2

T1

43

T13

2