Group : cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg
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Group : cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
85.71 91.67 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_cgs_wrap[sysrst_ctrl_reg_block] 91.67 1 100 1 64 64




Group Instance : tl_intg_err_cgs_wrap[sysrst_ctrl_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
91.67 1 100 1 64 64




Summary for Group Instance tl_intg_err_cgs_wrap[sysrst_ctrl_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 14 2 12 91.67


Variables for Group Instance tl_intg_err_cgs_wrap[sysrst_ctrl_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_is_mem 2 1 1 50.00 100 0 0 2
cp_num_cmd_err_bits 4 1 3 75.00 100 1 1 0
cp_num_data_err_bits 4 0 4 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0


Summary for Variable cp_is_mem

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_is_mem

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
[auto[1]] 0 0 - - - - - -
auto[0] 292048 0 T5 3 T6 18 T1 747



Summary for Variable cp_num_cmd_err_bits

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 1 3 75.00


User Defined Bins for cp_num_cmd_err_bits

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
values[2] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 291864 1 T5 3 T6 18 T1 747
values[1] 18 1 T271 2 T368 1 T369 2
values[3] 105 1 T271 6 T272 10 T273 3



Summary for Variable cp_num_data_err_bits

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_num_data_err_bits

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 291845 1 T5 3 T6 18 T1 747
values[1] 17 1 T272 3 T368 2 T370 1
values[2] 7 1 T272 1 T273 1 T368 1
values[3] 107 1 T271 3 T272 5 T273 2



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 291758 1 T5 3 T6 18 T1 747
auto[TlIntgErrCmd] 87 1 T271 4 T272 5 T273 4
auto[TlIntgErrData] 106 1 T271 1 T272 6 T273 5
auto[TlIntgErrBoth] 97 1 T271 5 T272 9 T273 1

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