Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1287576960	9202	0	0
auto_block_debounce_ctl_rd_A	1287576960	1235	0	0
auto_block_out_ctl_rd_A	1287576960	1744	0	0
com_det_ctl_0_rd_A	1287576960	3462	0	0
com_det_ctl_1_rd_A	1287576960	3533	0	0
com_det_ctl_2_rd_A	1287576960	3614	0	0
com_det_ctl_3_rd_A	1287576960	3365	0	0
com_out_ctl_0_rd_A	1287576960	3737	0	0
com_out_ctl_1_rd_A	1287576960	3947	0	0
com_out_ctl_2_rd_A	1287576960	4061	0	0
com_out_ctl_3_rd_A	1287576960	4051	0	0
com_pre_det_ctl_0_rd_A	1287576960	832	0	0
com_pre_det_ctl_1_rd_A	1287576960	809	0	0
com_pre_det_ctl_2_rd_A	1287576960	691	0	0
com_pre_det_ctl_3_rd_A	1287576960	815	0	0
com_pre_sel_ctl_0_rd_A	1287576960	4006	0	0
com_pre_sel_ctl_1_rd_A	1287576960	4262	0	0
com_pre_sel_ctl_2_rd_A	1287576960	4086	0	0
com_pre_sel_ctl_3_rd_A	1287576960	3858	0	0
com_sel_ctl_0_rd_A	1287576960	4121	0	0
com_sel_ctl_1_rd_A	1287576960	3958	0	0
com_sel_ctl_2_rd_A	1287576960	4123	0	0
com_sel_ctl_3_rd_A	1287576960	4030	0	0
ec_rst_ctl_rd_A	1287576960	2020	0	0
intr_enable_rd_A	1287576960	1068	0	0
key_intr_ctl_rd_A	1287576960	2539	0	0
key_intr_debounce_ctl_rd_A	1287576960	824	0	0
key_invert_ctl_rd_A	1287576960	6032	0	0
pin_allowed_ctl_rd_A	1287576960	5046	0	0
pin_out_ctl_rd_A	1287576960	4107	0	0
pin_out_value_rd_A	1287576960	4132	0	0
regwen_rd_A	1287576960	778	0	0
ulp_ac_debounce_ctl_rd_A	1287576960	850	0	0
ulp_ctl_rd_A	1287576960	938	0	0
ulp_lid_debounce_ctl_rd_A	1287576960	884	0	0
ulp_pwrb_debounce_ctl_rd_A	1287576960	826	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1287576960	9202	0	0
T1	431126	8	0	0
T2	811897	0	0	0
T3	203995	0	0	0
T8	0	9	0	0
T13	98944	0	0	0
T14	247856	0	0	0
T15	54755	0	0	0
T16	66927	0	0	0
T17	159599	0	0	0
T18	405747	0	0	0
T19	125914	0	0	0
T27	0	8	0	0
T40	0	10	0	0
T43	0	14	0	0
T60	0	10	0	0
T109	0	3	0	0
T110	0	22	0	0
T112	0	9	0	0
T114	0	6	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1287576960	1235	0	0
T42	283614	0	0	0
T45	763966	19	0	0
T46	54003	0	0	0
T47	49383	0	0	0
T64	245068	0	0	0
T71	638282	0	0	0
T72	488356	0	0	0
T109	0	12	0	0
T174	0	16	0	0
T193	0	13	0	0
T231	0	13	0	0
T244	195179	0	0	0
T245	59798	0	0	0
T259	160964	0	0	0
T295	0	10	0	0
T296	0	6	0	0
T297	0	9	0	0
T298	0	5	0	0
T299	0	13	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1287576960	1744	0	0
T42	283614	0	0	0
T45	763966	16	0	0
T46	54003	0	0	0
T47	49383	0	0	0
T64	245068	0	0	0
T71	638282	0	0	0
T72	488356	0	0	0
T109	0	18	0	0
T174	0	6	0	0
T193	0	4	0	0
T231	0	14	0	0
T244	195179	0	0	0
T245	59798	0	0	0
T259	160964	0	0	0
T295	0	8	0	0
T296	0	8	0	0
T297	0	5	0	0
T298	0	11	0	0
T299	0	3	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1287576960	3462	0	0
T11	377771	60	0	0
T12	284261	0	0	0
T35	483382	0	0	0
T37	61891	0	0	0
T45	0	67	0	0
T52	0	56	0	0
T55	0	39	0	0
T62	12971	0	0	0
T63	238850	0	0	0
T70	260868	0	0	0
T78	0	79	0	0
T80	0	54	0	0
T90	0	76	0	0
T211	0	58	0	0
T291	0	30	0	0
T300	0	41	0	0
T301	386635	0	0	0
T302	18437	0	0	0
T303	113089	0	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1287576960	3533	0	0
T11	377771	57	0	0
T12	284261	0	0	0
T35	483382	0	0	0
T37	61891	0	0	0
T45	0	81	0	0
T52	0	43	0	0
T55	0	36	0	0
T62	12971	0	0	0
T63	238850	0	0	0
T70	260868	0	0	0
T78	0	68	0	0
T80	0	50	0	0
T90	0	82	0	0
T211	0	44	0	0
T291	0	38	0	0
T300	0	46	0	0
T301	386635	0	0	0
T302	18437	0	0	0
T303	113089	0	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1287576960	3614	0	0
T11	377771	74	0	0
T12	284261	0	0	0
T35	483382	0	0	0
T37	61891	0	0	0
T45	0	73	0	0
T52	0	38	0	0
T55	0	56	0	0
T62	12971	0	0	0
T63	238850	0	0	0
T70	260868	0	0	0
T78	0	96	0	0
T80	0	70	0	0
T90	0	57	0	0
T211	0	32	0	0
T291	0	26	0	0
T300	0	40	0	0
T301	386635	0	0	0
T302	18437	0	0	0
T303	113089	0	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1287576960	3365	0	0
T11	377771	75	0	0
T12	284261	0	0	0
T35	483382	0	0	0
T37	61891	0	0	0
T45	0	57	0	0
T52	0	45	0	0
T55	0	39	0	0
T62	12971	0	0	0
T63	238850	0	0	0
T70	260868	0	0	0
T78	0	66	0	0
T80	0	60	0	0
T90	0	57	0	0
T211	0	48	0	0
T291	0	50	0	0
T300	0	28	0	0
T301	386635	0	0	0
T302	18437	0	0	0
T303	113089	0	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1287576960	3737	0	0
T11	377771	74	0	0
T12	284261	0	0	0
T35	483382	0	0	0
T37	61891	0	0	0
T45	0	39	0	0
T52	0	47	0	0
T55	0	61	0	0
T62	12971	0	0	0
T63	238850	0	0	0
T70	260868	0	0	0
T78	0	59	0	0
T80	0	58	0	0
T90	0	72	0	0
T211	0	39	0	0
T291	0	35	0	0
T300	0	53	0	0
T301	386635	0	0	0
T302	18437	0	0	0
T303	113089	0	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1287576960	3947	0	0
T11	377771	74	0	0
T12	284261	0	0	0
T35	483382	0	0	0
T37	61891	0	0	0
T45	0	69	0	0
T52	0	35	0	0
T55	0	48	0	0
T62	12971	0	0	0
T63	238850	0	0	0
T70	260868	0	0	0
T78	0	71	0	0
T80	0	66	0	0
T90	0	80	0	0
T211	0	58	0	0
T291	0	37	0	0
T300	0	42	0	0
T301	386635	0	0	0
T302	18437	0	0	0
T303	113089	0	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1287576960	4061	0	0
T11	377771	56	0	0
T12	284261	0	0	0
T35	483382	0	0	0
T37	61891	0	0	0
T45	0	70	0	0
T52	0	39	0	0
T55	0	46	0	0
T62	12971	0	0	0
T63	238850	0	0	0
T70	260868	0	0	0
T78	0	100	0	0
T80	0	70	0	0
T90	0	86	0	0
T211	0	43	0	0
T291	0	74	0	0
T300	0	56	0	0
T301	386635	0	0	0
T302	18437	0	0	0
T303	113089	0	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1287576960	4051	0	0
T11	377771	82	0	0
T12	284261	0	0	0
T35	483382	0	0	0
T37	61891	0	0	0
T45	0	51	0	0
T52	0	39	0	0
T55	0	57	0	0
T62	12971	0	0	0
T63	238850	0	0	0
T70	260868	0	0	0
T78	0	57	0	0
T80	0	57	0	0
T90	0	64	0	0
T211	0	49	0	0
T291	0	41	0	0
T300	0	66	0	0
T301	386635	0	0	0
T302	18437	0	0	0
T303	113089	0	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1287576960	832	0	0
T116	215397	0	0	0
T117	0	11	0	0
T124	0	21	0	0
T139	0	33	0	0
T186	241149	22	0	0
T263	0	31	0	0
T304	289279	2	0	0
T305	0	31	0	0
T306	0	20	0	0
T307	0	16	0	0
T308	0	7	0	0
T309	317682	0	0	0
T310	158540	0	0	0
T311	73283	0	0	0
T312	62484	0	0	0
T313	737565	0	0	0
T314	173526	0	0	0
T315	63299	0	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1287576960	809	0	0
T109	269273	5	0	0
T117	0	29	0	0
T139	0	29	0	0
T174	0	9	0	0
T175	246478	0	0	0
T186	0	29	0	0
T231	157077	0	0	0
T263	0	18	0	0
T304	0	8	0	0
T305	0	24	0	0
T306	0	28	0	0
T307	0	11	0	0
T316	88321	0	0	0
T317	73552	0	0	0
T318	201380	0	0	0
T319	50807	0	0	0
T320	379612	0	0	0
T321	107276	0	0	0
T322	196620	0	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1287576960	691	0	0
T109	269273	7	0	0
T117	0	31	0	0
T139	0	24	0	0
T174	0	13	0	0
T175	246478	0	0	0
T186	0	7	0	0
T231	157077	0	0	0
T263	0	21	0	0
T304	0	1	0	0
T305	0	33	0	0
T306	0	28	0	0
T307	0	12	0	0
T316	88321	0	0	0
T317	73552	0	0	0
T318	201380	0	0	0
T319	50807	0	0	0
T320	379612	0	0	0
T321	107276	0	0	0
T322	196620	0	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1287576960	815	0	0
T109	269273	4	0	0
T117	0	16	0	0
T139	0	30	0	0
T174	0	14	0	0
T175	246478	0	0	0
T186	0	14	0	0
T231	157077	0	0	0
T263	0	3	0	0
T304	0	13	0	0
T305	0	24	0	0
T306	0	26	0	0
T307	0	11	0	0
T316	88321	0	0	0
T317	73552	0	0	0
T318	201380	0	0	0
T319	50807	0	0	0
T320	379612	0	0	0
T321	107276	0	0	0
T322	196620	0	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1287576960	4006	0	0
T11	377771	68	0	0
T12	284261	0	0	0
T35	483382	0	0	0
T37	61891	0	0	0
T45	0	84	0	0
T52	0	21	0	0
T55	0	48	0	0
T62	12971	0	0	0
T63	238850	0	0	0
T70	260868	0	0	0
T78	0	99	0	0
T80	0	65	0	0
T90	0	83	0	0
T211	0	27	0	0
T291	0	54	0	0
T300	0	46	0	0
T301	386635	0	0	0
T302	18437	0	0	0
T303	113089	0	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1287576960	4262	0	0
T11	377771	95	0	0
T12	284261	0	0	0
T35	483382	0	0	0
T37	61891	0	0	0
T45	0	69	0	0
T52	0	39	0	0
T55	0	46	0	0
T62	12971	0	0	0
T63	238850	0	0	0
T70	260868	0	0	0
T78	0	67	0	0
T80	0	58	0	0
T90	0	61	0	0
T211	0	79	0	0
T291	0	46	0	0
T300	0	21	0	0
T301	386635	0	0	0
T302	18437	0	0	0
T303	113089	0	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1287576960	4086	0	0
T11	377771	83	0	0
T12	284261	0	0	0
T35	483382	0	0	0
T37	61891	0	0	0
T45	0	84	0	0
T52	0	41	0	0
T55	0	36	0	0
T62	12971	0	0	0
T63	238850	0	0	0
T70	260868	0	0	0
T78	0	55	0	0
T80	0	38	0	0
T90	0	89	0	0
T211	0	50	0	0
T291	0	44	0	0
T300	0	57	0	0
T301	386635	0	0	0
T302	18437	0	0	0
T303	113089	0	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1287576960	3858	0	0
T11	377771	63	0	0
T12	284261	0	0	0
T35	483382	0	0	0
T37	61891	0	0	0
T45	0	86	0	0
T52	0	22	0	0
T55	0	56	0	0
T62	12971	0	0	0
T63	238850	0	0	0
T70	260868	0	0	0
T78	0	48	0	0
T80	0	51	0	0
T90	0	73	0	0
T211	0	47	0	0
T291	0	33	0	0
T300	0	49	0	0
T301	386635	0	0	0
T302	18437	0	0	0
T303	113089	0	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1287576960	4121	0	0
T11	377771	69	0	0
T12	284261	0	0	0
T35	483382	0	0	0
T37	61891	0	0	0
T45	0	62	0	0
T52	0	30	0	0
T55	0	41	0	0
T62	12971	0	0	0
T63	238850	0	0	0
T70	260868	0	0	0
T78	0	48	0	0
T80	0	70	0	0
T90	0	56	0	0
T211	0	35	0	0
T291	0	46	0	0
T300	0	48	0	0
T301	386635	0	0	0
T302	18437	0	0	0
T303	113089	0	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1287576960	3958	0	0
T11	377771	73	0	0
T12	284261	0	0	0
T35	483382	0	0	0
T37	61891	0	0	0
T45	0	90	0	0
T52	0	54	0	0
T55	0	50	0	0
T62	12971	0	0	0
T63	238850	0	0	0
T70	260868	0	0	0
T78	0	64	0	0
T80	0	44	0	0
T90	0	65	0	0
T211	0	33	0	0
T291	0	17	0	0
T300	0	24	0	0
T301	386635	0	0	0
T302	18437	0	0	0
T303	113089	0	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1287576960	4123	0	0
T11	377771	86	0	0
T12	284261	0	0	0
T35	483382	0	0	0
T37	61891	0	0	0
T45	0	85	0	0
T52	0	24	0	0
T55	0	45	0	0
T62	12971	0	0	0
T63	238850	0	0	0
T70	260868	0	0	0
T78	0	74	0	0
T80	0	51	0	0
T90	0	58	0	0
T211	0	26	0	0
T291	0	46	0	0
T300	0	30	0	0
T301	386635	0	0	0
T302	18437	0	0	0
T303	113089	0	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1287576960	4030	0	0
T11	377771	60	0	0
T12	284261	0	0	0
T35	483382	0	0	0
T37	61891	0	0	0
T45	0	91	0	0
T52	0	32	0	0
T55	0	37	0	0
T62	12971	0	0	0
T63	238850	0	0	0
T70	260868	0	0	0
T78	0	78	0	0
T80	0	67	0	0
T90	0	64	0	0
T211	0	38	0	0
T291	0	50	0	0
T300	0	57	0	0
T301	386635	0	0	0
T302	18437	0	0	0
T303	113089	0	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1287576960	2020	0	0
T4	713961	0	0	0
T11	0	43	0	0
T14	247856	4	0	0
T15	54755	0	0	0
T16	66927	0	0	0
T17	159599	0	0	0
T18	405747	0	0	0
T19	125914	0	0	0
T28	123073	0	0	0
T32	153984	0	0	0
T45	0	18	0	0
T51	197050	0	0	0
T52	0	14	0	0
T55	0	4	0	0
T73	0	7	0	0
T78	0	22	0	0
T89	0	4	0	0
T90	0	32	0	0
T211	0	17	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1287576960	1068	0	0
T109	0	7	0	0
T117	0	29	0	0
T139	0	37	0	0
T174	0	31	0	0
T186	0	115	0	0
T193	616431	13	0	0
T268	214088	0	0	0
T286	232716	0	0	0
T287	245405	0	0	0
T288	208668	0	0	0
T289	48625	0	0	0
T290	238571	0	0	0
T291	431081	0	0	0
T292	211832	0	0	0
T293	61569	0	0	0
T304	0	24	0	0
T305	0	22	0	0
T306	0	29	0	0
T323	0	3	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1287576960	2539	0	0
T75	932290	100	0	0
T109	0	10	0	0
T135	0	7	0	0
T174	0	15	0	0
T184	0	6	0	0
T186	0	36	0	0
T187	0	10	0	0
T193	0	3	0	0
T231	0	2	0	0
T242	218929	0	0	0
T297	303531	0	0	0
T304	0	11	0	0
T324	171115	0	0	0
T325	15323	0	0	0
T326	18324	0	0	0
T327	205479	0	0	0
T328	123385	0	0	0
T329	58976	0	0	0
T330	34936	0	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1287576960	824	0	0
T109	269273	10	0	0
T117	0	24	0	0
T139	0	18	0	0
T174	0	7	0	0
T175	246478	0	0	0
T186	0	20	0	0
T231	157077	0	0	0
T263	0	14	0	0
T304	0	21	0	0
T305	0	34	0	0
T306	0	27	0	0
T307	0	6	0	0
T316	88321	0	0	0
T317	73552	0	0	0
T318	201380	0	0	0
T319	50807	0	0	0
T320	379612	0	0	0
T321	107276	0	0	0
T322	196620	0	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1287576960	6032	0	0
T7	441183	0	0	0
T8	155533	0	0	0
T28	123073	41	0	0
T29	236692	0	0	0
T30	60746	0	0	0
T43	166093	0	0	0
T61	231277	53	0	0
T62	0	71	0	0
T66	128157	0	0	0
T67	58172	0	0	0
T68	250421	0	0	0
T98	0	80	0	0
T109	0	73	0	0
T174	0	332	0	0
T328	0	89	0	0
T331	0	60	0	0
T332	0	66	0	0
T333	0	61	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1287576960	5046	0	0
T4	713961	0	0	0
T7	441183	0	0	0
T19	125914	42	0	0
T28	123073	0	0	0
T29	236692	0	0	0
T30	60746	62	0	0
T32	153984	0	0	0
T43	166093	0	0	0
T51	197050	0	0	0
T66	128157	0	0	0
T67	0	60	0	0
T69	0	98	0	0
T109	0	6	0	0
T210	0	73	0	0
T231	0	58	0	0
T295	0	89	0	0
T302	0	65	0	0
T334	0	86	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1287576960	4107	0	0
T4	713961	0	0	0
T7	441183	0	0	0
T19	125914	59	0	0
T28	123073	0	0	0
T29	236692	0	0	0
T30	60746	71	0	0
T32	153984	0	0	0
T43	166093	0	0	0
T51	197050	0	0	0
T66	128157	0	0	0
T67	0	87	0	0
T69	0	60	0	0
T109	0	1	0	0
T210	0	51	0	0
T231	0	52	0	0
T295	0	76	0	0
T302	0	61	0	0
T334	0	57	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1287576960	4132	0	0
T4	713961	0	0	0
T7	441183	0	0	0
T19	125914	46	0	0
T28	123073	0	0	0
T29	236692	0	0	0
T30	60746	54	0	0
T32	153984	0	0	0
T43	166093	0	0	0
T51	197050	0	0	0
T66	128157	0	0	0
T67	0	69	0	0
T69	0	56	0	0
T109	0	5	0	0
T210	0	62	0	0
T231	0	71	0	0
T295	0	61	0	0
T302	0	61	0	0
T334	0	73	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1287576960	778	0	0
T109	269273	4	0	0
T117	0	14	0	0
T139	0	24	0	0
T174	0	16	0	0
T175	246478	0	0	0
T186	0	25	0	0
T231	157077	0	0	0
T263	0	16	0	0
T304	0	7	0	0
T305	0	29	0	0
T306	0	44	0	0
T307	0	4	0	0
T316	88321	0	0	0
T317	73552	0	0	0
T318	201380	0	0	0
T319	50807	0	0	0
T320	379612	0	0	0
T321	107276	0	0	0
T322	196620	0	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1287576960	850	0	0
T58	65386	13	0	0
T59	63548	0	0	0
T87	0	4	0	0
T94	622122	0	0	0
T109	0	4	0	0
T111	0	1	0	0
T126	245063	0	0	0
T127	119621	0	0	0
T128	877436	0	0	0
T129	108497	0	0	0
T130	245438	0	0	0
T131	150202	0	0	0
T132	578435	0	0	0
T174	0	5	0	0
T186	0	19	0	0
T304	0	9	0	0
T335	0	9	0	0
T336	0	7	0	0
T337	0	8	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1287576960	938	0	0
T58	65386	9	0	0
T59	63548	0	0	0
T87	0	4	0	0
T94	622122	0	0	0
T109	0	6	0	0
T111	0	5	0	0
T126	245063	0	0	0
T127	119621	0	0	0
T128	877436	0	0	0
T129	108497	0	0	0
T130	245438	0	0	0
T131	150202	0	0	0
T132	578435	0	0	0
T174	0	9	0	0
T186	0	16	0	0
T304	0	11	0	0
T335	0	5	0	0
T336	0	3	0	0
T337	0	10	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1287576960	884	0	0
T58	65386	7	0	0
T59	63548	0	0	0
T87	0	1	0	0
T94	622122	0	0	0
T109	0	7	0	0
T111	0	5	0	0
T126	245063	0	0	0
T127	119621	0	0	0
T128	877436	0	0	0
T129	108497	0	0	0
T130	245438	0	0	0
T131	150202	0	0	0
T132	578435	0	0	0
T139	0	26	0	0
T186	0	16	0	0
T304	0	8	0	0
T335	0	6	0	0
T336	0	2	0	0
T338	0	12	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1287576960	826	0	0
T58	65386	6	0	0
T59	63548	0	0	0
T87	0	8	0	0
T94	622122	0	0	0
T109	0	2	0	0
T111	0	3	0	0
T126	245063	0	0	0
T127	119621	0	0	0
T128	877436	0	0	0
T129	108497	0	0	0
T130	245438	0	0	0
T131	150202	0	0	0
T132	578435	0	0	0
T174	0	8	0	0
T186	0	21	0	0
T304	0	3	0	0
T335	0	8	0	0
T336	0	7	0	0
T338	0	6	0	0