Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
89.02	89.02	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	89.02	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
89.02	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	9	53	85.48

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	9	22	70.97	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1998

1

T1

21

T2

1

T3

4

auto[1]

675

1

T1

3

T2

1

T4

6

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1996

1

T1

19

T2

2

T3

4

auto[1]

677

1

T1

5

T4

10

T15

3

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2047

1

T1

21

T4

10

T15

12

auto[1]

626

1

T1

3

T2

2

T3

4

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1970

1

T1

13

T2

2

T4

7

auto[1]

703

1

T1

11

T3

4

T4

7

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2427

1

T1

20

T2

2

T3

4

auto[1]

246

1

T1

4

T45

1

T46

7

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2519

1

T1

23

T2

2

T3

4

auto[1]

154

1

T1

1

T15

3

T45

2

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2424

1

T1

21

T2

2

T3

4

auto[1]

249

1

T1

3

T15

5

T47

3

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2446

1

T1

23

T2

2

T3

4

auto[1]

227

1

T1

1

T23

2

T46

7

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2462

1

T1

16

T2

2

T3

4

auto[1]

211

1

T1

8

T15

2

T45

2

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1988

1

T1

23

T2

2

T3

2

auto[1]

685

1

T1

1

T3

2

T4

8

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	9	22	70.97	9
Automatically Generated Cross Bins	31	9	22	70.97	9
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	*	[auto[1]]	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

994

1

T2

2

T3

2

T4

10

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

103

1

T45

1

T254

6

T98

12

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

84

1

T1

5

T253

7

T270

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

19

1

T1

3

T338

7

T346

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

67

1

T252

7

T347

1

T348

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

26

1

T46

4

T68

1

T69

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

12

1

T255

1

T340

8

T349

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

100

1

T1

3

T15

3

T253

11

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

36

1

T69

1

T253

7

T254

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

20

1

T15

2

T81

1

T333

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

6

1

T253

3

T270

2

T350

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

26

1

T82

3

T351

10

T343

8

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

13

1

T47

3

T254

3

T96

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

35

1

T15

3

T46

7

T352

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

16

1

T256

1

T228

4

T255

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

33

1

T45

2

T330

1

T101

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

29

1

T252

3

T336

2

T330

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

9

1

T1

1

T46

3

T342

5

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

7

1

T69

3

T333

3

T353

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

5

1

T81

1

T337

3

T354

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

2

1

T256

1

T355

1

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

2

1

T343

2

-

-

-

-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

133

1

T27

13

T47

3

T250

9

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

112

1

T1

1

T29

4

T46

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

86

1

T15

3

T27

8

T91

14

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

107

1

T15

2

T69

1

T150

9

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

67

1

T1

3

T11

1

T28

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

52

1

T21

6

T254

4

T333

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

24

1

T150

4

T267

4

T331

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

148

1

T2

1

T28

15

T69

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

68

1

T2

1

T97

3

T356

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

74

1

T27

7

T69

5

T254

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

29

1

T268

4

T344

3

T357

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

72

1

T1

3

T29

1

T334

10

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

39

1

T208

1

T261

5

T101

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

16

1

T3

2

T7

3

T45

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

8

1

T250

3

T107

3

T358

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

99

1

T4

4

T46

4

T250

11

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

65

1

T29

2

T254

3

T96

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

90

1

T21

6

T68

1

T252

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

25

1

T7

2

T127

1

T262

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

123

1

T1

5

T177

8

T331

6

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

32

1

T274

2

T177

7

T351

11

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

37

1

T4

2

T15

3

T7

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

6

1

T306

1

T187

2

T140

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

35

1

T27

7

T29

2

T334

9

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

18

1

T4

1

T28

3

T334

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

25

1

T4

2

T29

2

T98

6

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

6

1

T261

3

T359

1

T360

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

22

1

T305

4

T361

2

T228

4

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

11

1

T4

1

T150

2

T136

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

10

1

T49

2

T95

2

T347

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

5

1

T362

2

T363

1

T280

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded