Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1087

1

T6

9

T2

10

T4

15

auto[1]

1071

1

T6

11

T2

10

T4

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

515

1

T6

6

T2

5

T4

7

from_0to1

514

1

T6

5

T2

5

T4

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1102

1

T6

13

T2

10

T4

9

auto[1]

1056

1

T6

7

T2

10

T4

16

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1059

1

T6

11

T2

12

T4

12

auto[1]

1099

1

T6

9

T2

8

T4

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T6

1

T4

3

T14

1

auto[0]

from_1to0

auto[0]

auto[1]

69

1

T6

1

T54

1

T11

2

auto[0]

from_1to0

auto[1]

auto[0]

57

1

T6

1

T4

1

T11

2

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T4

2

T67

1

T43

2

auto[0]

from_0to1

auto[0]

auto[0]

76

1

T6

2

T14

2

T54

1

auto[0]

from_0to1

auto[0]

auto[1]

71

1

T14

1

T11

1

T67

1

auto[0]

from_0to1

auto[1]

auto[0]

53

1

T2

1

T14

1

T11

2

auto[0]

from_0to1

auto[1]

auto[1]

64

1

T2

1

T54

1

T11

1

auto[1]

from_1to0

auto[0]

auto[0]

67

1

T6

1

T2

1

T14

1

auto[1]

from_1to0

auto[0]

auto[1]

63

1

T2

3

T14

2

T11

1

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T6

1

T2

1

T4

1

auto[1]

from_1to0

auto[1]

auto[1]

68

1

T6

1

T11

1

T56

1

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T6

1

T2

1

T11

2

auto[1]

from_0to1

auto[0]

auto[1]

60

1

T6

1

T4

2

T54

1

auto[1]

from_0to1

auto[1]

auto[0]

57

1

T2

2

T4

2

T54

1

auto[1]

from_0to1

auto[1]

auto[1]

70

1

T6

1

T4

2

T56

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1026

1

T6

11

T2

5

T4

10

auto[1]

1132

1

T6

9

T2

15

T4

15

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

522

1

T6

5

T2

4

T4

7

from_0to1

512

1

T6

4

T2

3

T4

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1027

1

T6

9

T2

8

T4

14

auto[1]

1131

1

T6

11

T2

12

T4

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1089

1

T6

12

T2

8

T4

14

auto[1]

1069

1

T6

8

T2

12

T4

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

56

1

T4

3

T54

1

T67

1

auto[0]

from_1to0

auto[0]

auto[1]

66

1

T6

2

T11

3

T67

1

auto[0]

from_1to0

auto[1]

auto[0]

58

1

T6

1

T2

1

T11

2

auto[0]

from_1to0

auto[1]

auto[1]

60

1

T6

1

T54

1

T43

1

auto[0]

from_0to1

auto[0]

auto[0]

53

1

T4

1

T54

1

T43

1

auto[0]

from_0to1

auto[0]

auto[1]

54

1

T4

2

T54

1

T43

1

auto[0]

from_0to1

auto[1]

auto[0]

62

1

T54

2

T11

3

T56

3

auto[0]

from_0to1

auto[1]

auto[1]

73

1

T6

1

T4

1

T11

1

auto[1]

from_1to0

auto[0]

auto[0]

73

1

T2

1

T14

1

T11

4

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T2

1

T4

1

T14

1

auto[1]

from_1to0

auto[1]

auto[0]

78

1

T6

1

T4

1

T54

1

auto[1]

from_1to0

auto[1]

auto[1]

65

1

T2

1

T4

2

T14

2

auto[1]

from_0to1

auto[0]

auto[0]

79

1

T4

2

T14

1

T11

1

auto[1]

from_0to1

auto[0]

auto[1]

53

1

T4

1

T11

2

T67

1

auto[1]

from_0to1

auto[1]

auto[0]

77

1

T6

3

T2

2

T14

3

auto[1]

from_0to1

auto[1]

auto[1]

61

1

T2

1

T11

1

T56

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1075

1

T6

8

T2

8

T4

14

auto[1]

1083

1

T6

12

T2

12

T4

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

506

1

T6

5

T2

4

T4

8

from_0to1

508

1

T6

4

T2

3

T4

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1063

1

T6

13

T2

17

T4

11

auto[1]

1095

1

T6

7

T2

3

T4

14

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1095

1

T6

6

T2

15

T4

16

auto[1]

1063

1

T6

14

T2

5

T4

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

64

1

T6

1

T4

2

T11

1

auto[0]

from_1to0

auto[0]

auto[1]

60

1

T6

1

T14

1

T67

2

auto[0]

from_1to0

auto[1]

auto[0]

61

1

T4

2

T14

1

T11

1

auto[0]

from_1to0

auto[1]

auto[1]

57

1

T4

1

T14

2

T54

1

auto[0]

from_0to1

auto[0]

auto[0]

64

1

T6

1

T2

1

T4

3

auto[0]

from_0to1

auto[0]

auto[1]

49

1

T14

1

T56

1

T67

1

auto[0]

from_0to1

auto[1]

auto[0]

64

1

T14

1

T54

2

T11

3

auto[0]

from_0to1

auto[1]

auto[1]

73

1

T54

1

T11

2

T56

1

auto[1]

from_1to0

auto[0]

auto[0]

56

1

T6

1

T2

2

T4

1

auto[1]

from_1to0

auto[0]

auto[1]

85

1

T6

2

T14

1

T54

2

auto[1]

from_1to0

auto[1]

auto[0]

59

1

T54

2

T11

2

T43

1

auto[1]

from_1to0

auto[1]

auto[1]

64

1

T2

2

T4

2

T54

2

auto[1]

from_0to1

auto[0]

auto[0]

61

1

T6

1

T2

2

T4

1

auto[1]

from_0to1

auto[0]

auto[1]

59

1

T14

1

T56

1

T67

2

auto[1]

from_0to1

auto[1]

auto[0]

72

1

T4

2

T14

1

T11

1

auto[1]

from_0to1

auto[1]

auto[1]

66

1

T6

2

T4

1

T54

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1079

1

T6

9

T2

12

T4

13

auto[1]

1079

1

T6

11

T2

8

T4

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

518

1

T6

5

T2

6

T4

6

from_0to1

512

1

T6

6

T2

5

T4

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1067

1

T6

8

T2

11

T4

16

auto[1]

1091

1

T6

12

T2

9

T4

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1090

1

T6

9

T2

13

T4

14

auto[1]

1068

1

T6

11

T2

7

T4

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

67

1

T2

1

T4

3

T14

1

auto[0]

from_1to0

auto[0]

auto[1]

62

1

T4

1

T11

3

T56

1

auto[0]

from_1to0

auto[1]

auto[0]

62

1

T2

2

T4

1

T11

1

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T4

1

T14

1

T54

1

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T2

1

T4

2

T56

2

auto[0]

from_0to1

auto[0]

auto[1]

59

1

T6

1

T2

1

T4

1

auto[0]

from_0to1

auto[1]

auto[0]

65

1

T6

2

T2

1

T54

1

auto[0]

from_0to1

auto[1]

auto[1]

71

1

T6

1

T2

1

T14

1

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T2

1

T54

1

T11

1

auto[1]

from_1to0

auto[0]

auto[1]

76

1

T11

3

T56

1

T43

1

auto[1]

from_1to0

auto[1]

auto[0]

68

1

T6

4

T2

2

T11

1

auto[1]

from_1to0

auto[1]

auto[1]

56

1

T6

1

T14

2

T54

2

auto[1]

from_0to1

auto[0]

auto[0]

50

1

T14

1

T11

1

T56

1

auto[1]

from_0to1

auto[0]

auto[1]

76

1

T6

1

T2

1

T4

2

auto[1]

from_0to1

auto[1]

auto[0]

73

1

T6

1

T14

2

T54

2

auto[1]

from_0to1

auto[1]

auto[1]

55

1

T11

2

T56

1

T67

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1061

1

T6

12

T2

11

T4

13

auto[1]

1097

1

T6

8

T2

9

T4

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

529

1

T6

4

T2

4

T4

8

from_0to1

527

1

T6

5

T2

3

T4

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1110

1

T6

10

T2

10

T4

18

auto[1]

1048

1

T6

10

T2

10

T4

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1065

1

T6

7

T2

7

T4

15

auto[1]

1093

1

T6

13

T2

13

T4

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

64

1

T6

1

T4

3

T54

2

auto[0]

from_1to0

auto[0]

auto[1]

56

1

T6

1

T2

2

T14

1

auto[0]

from_1to0

auto[1]

auto[0]

73

1

T2

1

T4

1

T14

1

auto[0]

from_1to0

auto[1]

auto[1]

70

1

T11

1

T67

2

T89

1

auto[0]

from_0to1

auto[0]

auto[0]

70

1

T6

1

T2

1

T4

1

auto[0]

from_0to1

auto[0]

auto[1]

79

1

T6

1

T2

2

T4

1

auto[0]

from_0to1

auto[1]

auto[0]

70

1

T4

1

T54

1

T11

1

auto[0]

from_0to1

auto[1]

auto[1]

65

1

T6

1

T4

1

T14

1

auto[1]

from_1to0

auto[0]

auto[0]

69

1

T6

1

T4

1

T14

1

auto[1]

from_1to0

auto[0]

auto[1]

62

1

T4

3

T11

4

T43

1

auto[1]

from_1to0

auto[1]

auto[0]

65

1

T2

1

T14

1

T11

1

auto[1]

from_1to0

auto[1]

auto[1]

70

1

T6

1

T14

1

T11

2

auto[1]

from_0to1

auto[0]

auto[0]

72

1

T6

1

T4

1

T14

1

auto[1]

from_0to1

auto[0]

auto[1]

58

1

T4

1

T54

1

T11

1

auto[1]

from_0to1

auto[1]

auto[0]

62

1

T4

1

T56

1

T34

1

auto[1]

from_0to1

auto[1]

auto[1]

51

1

T6

1

T14

1

T67

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1015

1

T6

10

T2

11

T4

15

auto[1]

1143

1

T6

10

T2

9

T4

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

532

1

T6

4

T2

4

T4

7

from_0to1

526

1

T6

4

T2

4

T4

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1052

1

T6

9

T2

7

T4

15

auto[1]

1106

1

T6

11

T2

13

T4

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1091

1

T6

8

T2

9

T4

13

auto[1]

1067

1

T6

12

T2

11

T4

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

60

1

T4

2

T54

1

T11

1

auto[0]

from_1to0

auto[0]

auto[1]

59

1

T6

1

T2

1

T4

2

auto[0]

from_1to0

auto[1]

auto[0]

67

1

T2

1

T4

1

T14

1

auto[0]

from_1to0

auto[1]

auto[1]

70

1

T6

2

T4

1

T14

3

auto[0]

from_0to1

auto[0]

auto[0]

68

1

T6

1

T11

2

T56

2

auto[0]

from_0to1

auto[0]

auto[1]

70

1

T2

2

T4

1

T11

1

auto[0]

from_0to1

auto[1]

auto[0]

68

1

T2

1

T4

2

T11

1

auto[0]

from_0to1

auto[1]

auto[1]

62

1

T2

1

T14

1

T54

1

auto[1]

from_1to0

auto[0]

auto[0]

54

1

T54

1

T56

2

T34

1

auto[1]

from_1to0

auto[0]

auto[1]

82

1

T6

1

T4

1

T54

1

auto[1]

from_1to0

auto[1]

auto[0]

67

1

T2

2

T11

3

T56

1

auto[1]

from_1to0

auto[1]

auto[1]

73

1

T14

1

T54

1

T11

2

auto[1]

from_0to1

auto[0]

auto[0]

56

1

T4

1

T54

2

T11

1

auto[1]

from_0to1

auto[0]

auto[1]

63

1

T4

2

T14

2

T54

1

auto[1]

from_0to1

auto[1]

auto[0]

73

1

T6

2

T4

1

T11

1

auto[1]

from_0to1

auto[1]

auto[1]

66

1

T6

1

T14

2

T54

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1034

1

T6

8

T2

4

T4

15

auto[1]

1124

1

T6

12

T2

16

T4

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

516

1

T6

4

T2

5

T4

8

from_0to1

518

1

T6

5

T2

4

T4

8

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1082

1

T6

16

T2

12

T4

15

auto[1]

1076

1

T6

4

T2

8

T4

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1094

1

T6

9

T2

10

T4

12

auto[1]

1064

1

T6

11

T2

10

T4

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

52

1

T6

3

T2

1

T4

1

auto[0]

from_1to0

auto[0]

auto[1]

51

1

T2

1

T4

1

T11

1

auto[0]

from_1to0

auto[1]

auto[0]

70

1

T4

1

T14

1

T11

2

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T4

1

T67

1

T34

3

auto[0]

from_0to1

auto[0]

auto[0]

70

1

T4

1

T67

1

T34

2

auto[0]

from_0to1

auto[0]

auto[1]

67

1

T6

1

T2

1

T4

2

auto[0]

from_0to1

auto[1]

auto[0]

55

1

T2

1

T4

1

T14

1

auto[0]

from_0to1

auto[1]

auto[1]

56

1

T6

1

T4

1

T56

1

auto[1]

from_1to0

auto[0]

auto[0]

78

1

T6

1

T2

1

T14

1

auto[1]

from_1to0

auto[0]

auto[1]

74

1

T2

2

T4

3

T14

1

auto[1]

from_1to0

auto[1]

auto[0]

70

1

T54

1

T11

3

T34

2

auto[1]

from_1to0

auto[1]

auto[1]

57

1

T4

1

T11

2

T43

2

auto[1]

from_0to1

auto[0]

auto[0]

73

1

T6

2

T2

1

T4

1

auto[1]

from_0to1

auto[0]

auto[1]

70

1

T6

1

T2

1

T14

1

auto[1]

from_0to1

auto[1]

auto[0]

64

1

T4

2

T14

1

T54

1

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T14

1

T11

3

T56

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1116

1

T6

7

T2

8

T4

15

auto[1]

1042

1

T6

13

T2

12

T4

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

524

1

T6

3

T2

5

T4

6

from_0to1

529

1

T6

4

T2

5

T4

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1109

1

T6

10

T2

11

T4

8

auto[1]

1049

1

T6

10

T2

9

T4

17

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1072

1

T6

8

T2

12

T4

11

auto[1]

1086

1

T6

12

T2

8

T4

14

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

74

1

T2

1

T4

3

T54

2

auto[0]

from_1to0

auto[0]

auto[1]

74

1

T2

1

T4

1

T14

2

auto[0]

from_1to0

auto[1]

auto[0]

55

1

T14

1

T54

1

T67

1

auto[0]

from_1to0

auto[1]

auto[1]

72

1

T2

1

T4

1

T54

1

auto[0]

from_0to1

auto[0]

auto[0]

64

1

T54

1

T11

1

T67

1

auto[0]

from_0to1

auto[0]

auto[1]

65

1

T54

2

T11

1

T34

2

auto[0]

from_0to1

auto[1]

auto[0]

64

1

T6

1

T2

1

T4

1

auto[0]

from_0to1

auto[1]

auto[1]

67

1

T6

1

T4

2

T54

1

auto[1]

from_1to0

auto[0]

auto[0]

58

1

T14

1

T54

1

T34

3

auto[1]

from_1to0

auto[0]

auto[1]

65

1

T6

1

T11

1

T67

1

auto[1]

from_1to0

auto[1]

auto[0]

69

1

T6

1

T2

2

T4

1

auto[1]

from_1to0

auto[1]

auto[1]

57

1

T6

1

T11

2

T67

2

auto[1]

from_0to1

auto[0]

auto[0]

66

1

T6

1

T14

1

T43

2

auto[1]

from_0to1

auto[0]

auto[1]

77

1

T2

1

T14

1

T11

1

auto[1]

from_0to1

auto[1]

auto[0]

58

1

T2

2

T4

1

T11

2

auto[1]

from_0to1

auto[1]

auto[1]

68

1

T6

1

T2

1

T4

2