Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	158154	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

121273

1

T5

2

T1

340

T6

50

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	143815	1			T5	2		T1	277		T6	62
values[0x0]	67602	1			T1	355		T6	30		T2	52
values[0x1]	68010	1			T1	320		T6	31		T13	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	128232	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

151195

1

T5

2

T1

419

T6

67

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	921	1			T1	3		T6	1		T2	4
valid_sources[0x01]	905	1			T1	3		T2	3		T4	10
valid_sources[0x02]	1115	1			T1	2		T6	1		T2	5
valid_sources[0x03]	983	1			T1	5		T2	2		T4	11
valid_sources[0x04]	946	1			T1	2		T2	2		T4	9
valid_sources[0x05]	1067	1			T1	6		T6	1		T2	1
valid_sources[0x06]	1682	1			T1	4		T2	2		T3	4
valid_sources[0x07]	917	1			T1	7		T2	2		T3	1
valid_sources[0x08]	860	1			T1	5		T3	1		T4	11
valid_sources[0x09]	1067	1			T1	11		T6	1		T2	4
valid_sources[0x0a]	859	1			T1	8		T2	3		T11	3
valid_sources[0x0b]	1049	1			T1	2		T6	1		T2	2
valid_sources[0x0c]	983	1			T1	1		T6	1		T3	3
valid_sources[0x0d]	847	1			T1	3		T2	1		T3	1
valid_sources[0x0e]	1443	1			T2	5		T3	2		T4	10
valid_sources[0x0f]	1022	1			T1	1		T2	3		T3	4
valid_sources[0x10]	1660	1			T1	1		T6	1		T4	2
valid_sources[0x11]	1284	1			T1	5		T3	1		T15	8
valid_sources[0x12]	1684	1			T1	3		T6	1		T13	1
valid_sources[0x13]	944	1			T1	6		T2	2		T3	2
valid_sources[0x14]	980	1			T1	4		T15	1		T7	3
valid_sources[0x15]	863	1			T1	3		T2	1		T3	2
valid_sources[0x16]	1232	1			T1	3		T3	3		T14	1
valid_sources[0x17]	1094	1			T1	7		T2	1		T3	1
valid_sources[0x18]	1139	1			T1	1		T2	3		T4	29
valid_sources[0x19]	1615	1			T1	3		T13	1		T2	2
valid_sources[0x1a]	859	1			T1	3		T13	2		T2	1
valid_sources[0x1b]	847	1			T1	5		T2	1		T3	3
valid_sources[0x1c]	853	1			T1	8		T6	1		T2	4
valid_sources[0x1d]	855	1			T1	5		T6	1		T2	6
valid_sources[0x1e]	1526	1			T1	4		T2	1		T3	1
valid_sources[0x1f]	1389	1			T1	5		T6	2		T2	1
valid_sources[0x20]	1851	1			T1	8		T6	1		T2	1
valid_sources[0x21]	945	1			T1	6		T6	1		T13	4
valid_sources[0x22]	764	1			T1	4		T2	2		T3	3
valid_sources[0x23]	829	1			T1	5		T2	2		T15	4
valid_sources[0x24]	913	1			T2	1		T3	1		T4	9
valid_sources[0x25]	1052	1			T1	3		T2	1		T3	4
valid_sources[0x26]	1735	1			T1	4		T6	1		T2	2
valid_sources[0x27]	1071	1			T1	1		T6	1		T2	2
valid_sources[0x28]	949	1			T1	7		T2	1		T3	1
valid_sources[0x29]	1314	1			T1	2		T2	4		T3	2
valid_sources[0x2a]	1119	1			T1	1		T13	1		T2	3
valid_sources[0x2b]	962	1			T1	5		T6	1		T2	1
valid_sources[0x2c]	883	1			T1	3		T2	1		T3	2
valid_sources[0x2d]	945	1			T1	3		T2	2		T3	1
valid_sources[0x2e]	931	1			T1	4		T6	1		T3	2
valid_sources[0x2f]	2171	1			T1	5		T2	1		T3	1
valid_sources[0x30]	1304	1			T1	6		T6	1		T2	3
valid_sources[0x31]	2374	1			T1	6		T2	1		T4	6
valid_sources[0x32]	948	1			T1	5		T2	3		T15	9
valid_sources[0x33]	942	1			T1	4		T6	2		T13	1
valid_sources[0x34]	1821	1			T1	4		T2	1		T15	2
valid_sources[0x35]	1053	1			T1	5		T2	2		T3	4
valid_sources[0x36]	751	1			T1	10		T3	2		T4	8
valid_sources[0x37]	814	1			T1	4		T6	2		T2	1
valid_sources[0x38]	821	1			T1	7		T4	2		T14	1
valid_sources[0x39]	1880	1			T6	2		T2	2		T3	3
valid_sources[0x3a]	828	1			T1	3		T2	2		T4	3
valid_sources[0x3b]	1063	1			T1	1		T6	2		T2	2
valid_sources[0x3c]	828	1			T1	1		T6	3		T2	2
valid_sources[0x3d]	779	1			T1	4		T6	2		T2	1
valid_sources[0x3e]	1637	1			T1	3		T2	2		T3	3
valid_sources[0x3f]	1917	1			T1	2		T4	12		T14	1
valid_sources[0x40]	1169	1			T1	3		T3	3		T4	8
valid_sources[0x41]	750	1			T1	1		T2	4		T3	1
valid_sources[0x42]	1823	1			T1	2		T3	2		T4	13
valid_sources[0x43]	1482	1			T1	4		T2	4		T3	3
valid_sources[0x44]	966	1			T1	2		T2	3		T3	3
valid_sources[0x45]	837	1			T1	1		T2	2		T3	2
valid_sources[0x46]	899	1			T1	5		T6	1		T2	3
valid_sources[0x47]	908	1			T1	6		T2	2		T15	4
valid_sources[0x48]	1423	1			T1	5		T6	2		T13	1
valid_sources[0x49]	912	1			T1	8		T2	1		T4	7
valid_sources[0x4a]	923	1			T1	2		T6	1		T2	1
valid_sources[0x4b]	1260	1			T1	2		T3	2		T4	29
valid_sources[0x4c]	1258	1			T1	3		T6	1		T2	5
valid_sources[0x4d]	1062	1			T1	6		T2	4		T3	2
valid_sources[0x4e]	817	1			T1	4		T2	1		T3	2
valid_sources[0x4f]	988	1			T1	3		T6	2		T2	1
valid_sources[0x50]	1753	1			T1	5		T2	1		T4	11
valid_sources[0x51]	1439	1			T1	11		T2	1		T3	5
valid_sources[0x52]	1387	1			T1	5		T2	3		T3	1
valid_sources[0x53]	825	1			T1	7		T2	2		T4	1
valid_sources[0x54]	822	1			T2	1		T3	3		T4	25
valid_sources[0x55]	943	1			T1	6		T6	1		T13	1
valid_sources[0x56]	1105	1			T6	1		T2	2		T3	4
valid_sources[0x57]	1564	1			T1	2		T2	1		T3	1
valid_sources[0x58]	1456	1			T1	10		T15	2		T7	3
valid_sources[0x59]	1041	1			T2	3		T3	3		T4	2
valid_sources[0x5a]	1645	1			T1	1		T2	3		T3	2
valid_sources[0x5b]	760	1			T1	3		T13	1		T2	1
valid_sources[0x5c]	830	1			T1	4		T13	1		T2	1
valid_sources[0x5d]	968	1			T1	4		T2	1		T3	2
valid_sources[0x5e]	902	1			T1	8		T2	1		T3	1
valid_sources[0x5f]	2969	1			T1	5		T6	2		T13	2
valid_sources[0x60]	955	1			T1	8		T2	3		T3	2
valid_sources[0x61]	1835	1			T1	3		T6	1		T14	1
valid_sources[0x62]	882	1			T1	3		T3	1		T7	3
valid_sources[0x63]	762	1			T1	3		T2	1		T3	2
valid_sources[0x64]	916	1			T1	1		T2	1		T3	5
valid_sources[0x65]	989	1			T6	1		T2	2		T3	1
valid_sources[0x66]	1064	1			T1	6		T4	7		T15	6
valid_sources[0x67]	1049	1			T1	10		T6	2		T2	3
valid_sources[0x68]	806	1			T1	5		T2	1		T3	1
valid_sources[0x69]	914	1			T1	5		T2	2		T3	1
valid_sources[0x6a]	1121	1			T1	4		T6	2		T13	1
valid_sources[0x6b]	894	1			T1	3		T2	2		T3	2
valid_sources[0x6c]	1115	1			T1	1		T2	2		T15	3
valid_sources[0x6d]	882	1			T1	7		T6	1		T2	1
valid_sources[0x6e]	1177	1			T1	6		T2	2		T3	5
valid_sources[0x6f]	1404	1			T1	1		T2	2		T3	2
valid_sources[0x70]	1132	1			T1	3		T6	2		T2	3
valid_sources[0x71]	1097	1			T1	4		T6	1		T2	2
valid_sources[0x72]	1386	1			T1	4		T6	1		T2	2
valid_sources[0x73]	813	1			T1	1		T3	1		T14	1
valid_sources[0x74]	839	1			T1	5		T3	2		T4	13
valid_sources[0x75]	832	1			T1	1		T2	1		T4	6
valid_sources[0x76]	892	1			T1	3		T2	2		T3	4
valid_sources[0x77]	839	1			T1	4		T2	1		T4	7
valid_sources[0x78]	797	1			T1	6		T6	1		T2	1
valid_sources[0x79]	995	1			T1	4		T6	1		T2	2
valid_sources[0x7a]	905	1			T1	5		T2	1		T3	1
valid_sources[0x7b]	874	1			T1	8		T6	1		T2	1
valid_sources[0x7c]	899	1			T1	2		T2	1		T3	3
valid_sources[0x7d]	948	1			T1	3		T2	3		T3	5
valid_sources[0x7e]	1973	1			T1	2		T13	1		T2	2
valid_sources[0x7f]	966	1			T1	2		T6	1		T2	1
valid_sources[0x80]	2397	1			T1	1		T6	1		T2	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

65090

1

T5

2

T1

136

T6

29

values[0x0]

all_enables

biggest_size

32814

1

T1

139

T6

12

T2

27

values[0x1]

all_enables

biggest_size

23369

1

T1

65

T6

9

T2

21