Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T4,T11,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T4,T11,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T4,T42,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T11,T42
1	0	Covered	T5,T1,T6
1	1	Covered	T4,T11,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T42,T43
0	1	Covered	T105
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T42,T43
0	1	Covered	T4,T42,T43
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T42,T43
1	-	Covered	T4,T42,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T11,T42
DetectSt	168	Covered	T4,T42,T43
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T4,T42,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T42,T43
DebounceSt->IdleSt	163	Covered	T4,T11,T33
DetectSt->IdleSt	186	Covered	T105
DetectSt->StableSt	191	Covered	T4,T42,T43
IdleSt->DebounceSt	148	Covered	T4,T11,T42
StableSt->IdleSt	206	Covered	T4,T42,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T11,T42
0	1	Covered	T4,T11,T42
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T42,T43
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T11,T42
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T77,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T42,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T11,T126
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T11,T42
DetectSt	-	-	-	-	1	-	-	Covered	T105
DetectSt	-	-	-	-	0	1	-	Covered	T4,T42,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T42,T43
StableSt	-	-	-	-	-	-	0	Covered	T4,T42,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9322746	285	0	0
CntIncr_A	9322746	83974	0	0
CntNoWrap_A	9322746	8666050	0	0
DetectStDropOut_A	9322746	1	0	0
DetectedOut_A	9322746	860	0	0
DetectedPulseOut_A	9322746	130	0	0
DisabledIdleSt_A	9322746	8575737	0	0
DisabledNoDetection_A	9322746	8578142	0	0
EnterDebounceSt_A	9322746	158	0	0
EnterDetectSt_A	9322746	131	0	0
EnterStableSt_A	9322746	130	0	0
PulseIsPulse_A	9322746	130	0	0
StayInStableSt	9322746	730	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9322746	6918	0	0
gen_low_level_sva.LowLevelEvent_A	9322746	8668790	0	0
gen_not_sticky_sva.StableStDropOut_A	9322746	130	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	285	0	0
T4	31242	3	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T11	0	1	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T29	0	4	0	0
T33	0	4	0	0
T42	0	6	0	0
T43	0	4	0	0
T44	0	2	0	0
T49	0	2	0	0
T50	0	4	0	0
T51	0	4	0	0
T52	522	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	83974	0	0
T4	31242	65	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T11	0	33	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T29	0	119	0	0
T33	0	5863	0	0
T42	0	131	0	0
T43	0	151	0	0
T44	0	76	0	0
T49	0	43	0	0
T50	0	27906	0	0
T51	0	24790	0	0
T52	522	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8666050	0	0
T1	16004	15584	0	0
T2	8919	4895	0	0
T3	5221	4820	0	0
T4	31242	23130	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11521	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	14731	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	1	0	0
T105	26403	1	0	0
T106	25075	0	0	0
T118	502	0	0	0
T119	666	0	0	0
T120	25521	0	0	0
T121	960023	0	0	0
T122	423	0	0	0
T123	5766	0	0	0
T124	402	0	0	0
T125	693	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	860	0	0
T4	31242	9	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T29	0	16	0	0
T33	0	22	0	0
T42	0	16	0	0
T43	0	16	0	0
T44	0	7	0	0
T49	0	7	0	0
T50	0	13	0	0
T51	0	10	0	0
T52	522	0	0	0
T126	0	8	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	130	0	0
T4	31242	1	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T29	0	2	0	0
T33	0	2	0	0
T42	0	3	0	0
T43	0	2	0	0
T44	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	2	0	0
T52	522	0	0	0
T126	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8575737	0	0
T1	16004	15584	0	0
T2	8919	4895	0	0
T3	5221	4820	0	0
T4	31242	22999	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11521	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	14731	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8578142	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	23029	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	158	0	0
T4	31242	2	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T11	0	1	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T29	0	2	0	0
T33	0	3	0	0
T42	0	3	0	0
T43	0	2	0	0
T44	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	2	0	0
T52	522	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	131	0	0
T4	31242	1	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T29	0	2	0	0
T33	0	2	0	0
T42	0	3	0	0
T43	0	2	0	0
T44	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	2	0	0
T52	522	0	0	0
T126	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	130	0	0
T4	31242	1	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T29	0	2	0	0
T33	0	2	0	0
T42	0	3	0	0
T43	0	2	0	0
T44	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	2	0	0
T52	522	0	0	0
T126	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	130	0	0
T4	31242	1	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T29	0	2	0	0
T33	0	2	0	0
T42	0	3	0	0
T43	0	2	0	0
T44	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	2	0	0
T52	522	0	0	0
T126	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	730	0	0
T4	31242	8	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T29	0	14	0	0
T33	0	20	0	0
T42	0	13	0	0
T43	0	14	0	0
T44	0	6	0	0
T49	0	6	0	0
T50	0	11	0	0
T51	0	8	0	0
T52	522	0	0	0
T126	0	7	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	6918	0	0
T1	16004	30	0	0
T2	8919	19	0	0
T3	5221	8	0	0
T4	31242	70	0	0
T5	422	2	0	0
T6	502	2	0	0
T7	13942	15	0	0
T13	443	7	0	0
T14	505	5	0	0
T15	15149	29	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8668790	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	23163	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	130	0	0
T4	31242	1	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T29	0	2	0	0
T33	0	2	0	0
T42	0	3	0	0
T43	0	2	0	0
T44	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	2	0	0
T52	522	0	0	0
T126	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T8,T9,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T8,T9,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T8,T9,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T12
1	0	Covered	T5,T1,T6
1	1	Covered	T8,T9,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T12
0	1	Covered	T9,T87,T85
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T12
0	1	Unreachable
1	0	Covered	T8,T9,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T9,T12
DetectSt	168	Covered	T8,T9,T12
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T8,T9,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T9,T12
DebounceSt->IdleSt	163	Covered	T71,T72,T73
DetectSt->IdleSt	186	Covered	T9,T87,T85
DetectSt->StableSt	191	Covered	T8,T9,T12
IdleSt->DebounceSt	148	Covered	T8,T9,T12
StableSt->IdleSt	206	Covered	T8,T9,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T9,T12
0	1	Covered	T8,T9,T12
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T12
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T9,T12
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T77,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T9,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T71,T72,T73
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T9,T12
DetectSt	-	-	-	-	1	-	-	Covered	T9,T87,T85
DetectSt	-	-	-	-	0	1	-	Covered	T8,T9,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T9,T12
StableSt	-	-	-	-	-	-	0	Covered	T8,T9,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9322746	194	0	0
CntIncr_A	9322746	159186	0	0
CntNoWrap_A	9322746	8666141	0	0
DetectStDropOut_A	9322746	16	0	0
DetectedOut_A	9322746	861101	0	0
DetectedPulseOut_A	9322746	55	0	0
DisabledIdleSt_A	9322746	6026194	0	0
DisabledNoDetection_A	9322746	6028645	0	0
EnterDebounceSt_A	9322746	125	0	0
EnterDetectSt_A	9322746	71	0	0
EnterStableSt_A	9322746	55	0	0
PulseIsPulse_A	9322746	55	0	0
StayInStableSt	9322746	861046	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9322746	6918	0	0
gen_low_level_sva.LowLevelEvent_A	9322746	8668790	0	0
gen_sticky_sva.StableStDropOut_A	9322746	1369210	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	194	0	0
T8	1228	2	0	0
T9	2071	10	0	0
T10	628	0	0	0
T11	15667	0	0	0
T12	0	6	0	0
T21	29901	0	0	0
T22	489	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T56	507	0	0	0
T57	0	6	0	0
T71	0	4	0	0
T72	0	7	0	0
T73	0	5	0	0
T74	0	2	0	0
T75	0	5	0	0
T76	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	159186	0	0
T8	1228	66	0	0
T9	2071	315	0	0
T10	628	0	0	0
T11	15667	0	0	0
T12	0	282	0	0
T21	29901	0	0	0
T22	489	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T56	507	0	0	0
T57	0	87	0	0
T71	0	280	0	0
T72	0	539	0	0
T73	0	200	0	0
T74	0	91	0	0
T75	0	465	0	0
T76	0	48	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8666141	0	0
T1	16004	15584	0	0
T2	8919	4895	0	0
T3	5221	4820	0	0
T4	31242	23133	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11521	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	14731	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	16	0	0
T9	2071	3	0	0
T10	628	0	0	0
T11	15667	0	0	0
T21	29901	0	0	0
T22	489	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T56	507	0	0	0
T67	502	0	0	0
T85	0	1	0	0
T87	0	1	0	0
T137	0	3	0	0
T138	0	4	0	0
T139	0	1	0	0
T140	0	2	0	0
T141	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	861101	0	0
T8	1228	80	0	0
T9	2071	323	0	0
T10	628	0	0	0
T11	15667	0	0	0
T12	0	607	0	0
T21	29901	0	0	0
T22	489	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T56	507	0	0	0
T57	0	352	0	0
T74	0	419	0	0
T76	0	201	0	0
T83	0	253	0	0
T86	0	558	0	0
T132	0	329	0	0
T133	0	17	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	55	0	0
T8	1228	1	0	0
T9	2071	2	0	0
T10	628	0	0	0
T11	15667	0	0	0
T12	0	3	0	0
T21	29901	0	0	0
T22	489	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T56	507	0	0	0
T57	0	3	0	0
T74	0	1	0	0
T76	0	1	0	0
T83	0	2	0	0
T86	0	2	0	0
T132	0	1	0	0
T133	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	6026194	0	0
T1	16004	15584	0	0
T2	8919	4895	0	0
T3	5221	4820	0	0
T4	31242	23133	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11521	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	14731	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	6028645	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	23163	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	125	0	0
T8	1228	1	0	0
T9	2071	5	0	0
T10	628	0	0	0
T11	15667	0	0	0
T12	0	3	0	0
T21	29901	0	0	0
T22	489	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T56	507	0	0	0
T57	0	3	0	0
T71	0	4	0	0
T72	0	7	0	0
T73	0	5	0	0
T74	0	1	0	0
T75	0	5	0	0
T76	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	71	0	0
T8	1228	1	0	0
T9	2071	5	0	0
T10	628	0	0	0
T11	15667	0	0	0
T12	0	3	0	0
T21	29901	0	0	0
T22	489	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T56	507	0	0	0
T57	0	3	0	0
T74	0	1	0	0
T76	0	1	0	0
T83	0	2	0	0
T86	0	2	0	0
T132	0	1	0	0
T133	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	55	0	0
T8	1228	1	0	0
T9	2071	2	0	0
T10	628	0	0	0
T11	15667	0	0	0
T12	0	3	0	0
T21	29901	0	0	0
T22	489	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T56	507	0	0	0
T57	0	3	0	0
T74	0	1	0	0
T76	0	1	0	0
T83	0	2	0	0
T86	0	2	0	0
T132	0	1	0	0
T133	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	55	0	0
T8	1228	1	0	0
T9	2071	2	0	0
T10	628	0	0	0
T11	15667	0	0	0
T12	0	3	0	0
T21	29901	0	0	0
T22	489	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T56	507	0	0	0
T57	0	3	0	0
T74	0	1	0	0
T76	0	1	0	0
T83	0	2	0	0
T86	0	2	0	0
T132	0	1	0	0
T133	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	861046	0	0
T8	1228	79	0	0
T9	2071	321	0	0
T10	628	0	0	0
T11	15667	0	0	0
T12	0	604	0	0
T21	29901	0	0	0
T22	489	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T56	507	0	0	0
T57	0	349	0	0
T74	0	418	0	0
T76	0	200	0	0
T83	0	251	0	0
T86	0	556	0	0
T132	0	328	0	0
T133	0	16	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	6918	0	0
T1	16004	30	0	0
T2	8919	19	0	0
T3	5221	8	0	0
T4	31242	70	0	0
T5	422	2	0	0
T6	502	2	0	0
T7	13942	15	0	0
T13	443	7	0	0
T14	505	5	0	0
T15	15149	29	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8668790	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	23163	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	1369210	0	0
T8	1228	160	0	0
T9	2071	608	0	0
T10	628	0	0	0
T11	15667	0	0	0
T12	0	167	0	0
T21	29901	0	0	0
T22	489	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T56	507	0	0	0
T57	0	692	0	0
T74	0	53	0	0
T76	0	230	0	0
T83	0	378	0	0
T86	0	487006	0	0
T132	0	269	0	0
T133	0	138	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T6,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T6,T13
1	1	Covered	T5,T6,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T8,T9,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T8,T9,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T8,T9,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T12
1	0	Covered	T5,T6,T13
1	1	Covered	T8,T9,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T12
0	1	Covered	T74,T75,T86
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T12
0	1	Unreachable
1	0	Covered	T8,T9,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T9,T12
DetectSt	168	Covered	T8,T9,T12
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T8,T9,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T9,T12
DebounceSt->IdleSt	163	Covered	T71,T72,T74
DetectSt->IdleSt	186	Covered	T74,T75,T86
DetectSt->StableSt	191	Covered	T8,T9,T12
IdleSt->DebounceSt	148	Covered	T8,T9,T12
StableSt->IdleSt	206	Covered	T8,T9,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T9,T12
0	1	Covered	T8,T9,T12
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T12
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T9,T12
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T77,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T9,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T71,T72,T74
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T9,T12
DetectSt	-	-	-	-	1	-	-	Covered	T74,T75,T86
DetectSt	-	-	-	-	0	1	-	Covered	T8,T9,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T9,T12
StableSt	-	-	-	-	-	-	0	Covered	T8,T9,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9322746	200	0	0
CntIncr_A	9322746	131552	0	0
CntNoWrap_A	9322746	8666135	0	0
DetectStDropOut_A	9322746	22	0	0
DetectedOut_A	9322746	399441	0	0
DetectedPulseOut_A	9322746	50	0	0
DisabledIdleSt_A	9322746	6026194	0	0
DisabledNoDetection_A	9322746	6028645	0	0
EnterDebounceSt_A	9322746	130	0	0
EnterDetectSt_A	9322746	72	0	0
EnterStableSt_A	9322746	50	0	0
PulseIsPulse_A	9322746	50	0	0
StayInStableSt	9322746	399391	0	0
gen_high_level_sva.HighLevelEvent_A	9322746	8668790	0	0
gen_sticky_sva.StableStDropOut_A	9322746	1357581	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	200	0	0
T8	1228	2	0	0
T9	2071	6	0	0
T10	628	0	0	0
T11	15667	0	0	0
T12	0	6	0	0
T21	29901	0	0	0
T22	489	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T56	507	0	0	0
T57	0	6	0	0
T71	0	4	0	0
T72	0	7	0	0
T73	0	4	0	0
T74	0	5	0	0
T75	0	8	0	0
T76	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	131552	0	0
T8	1228	97	0	0
T9	2071	237	0	0
T10	628	0	0	0
T11	15667	0	0	0
T12	0	282	0	0
T21	29901	0	0	0
T22	489	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T56	507	0	0	0
T57	0	159	0	0
T71	0	352	0	0
T72	0	196	0	0
T73	0	72	0	0
T74	0	90	0	0
T75	0	285	0	0
T76	0	285	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8666135	0	0
T1	16004	15584	0	0
T2	8919	4895	0	0
T3	5221	4820	0	0
T4	31242	23133	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11521	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	14731	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	22	0	0
T74	999	2	0	0
T75	5654	3	0	0
T86	0	1	0	0
T126	738	0	0	0
T135	0	1	0	0
T136	0	2	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	5	0	0
T144	0	4	0	0
T145	0	2	0	0
T146	441	0	0	0
T147	4426	0	0	0
T148	405	0	0	0
T149	443	0	0	0
T150	37892	0	0	0
T151	506	0	0	0
T152	914	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	399441	0	0
T8	1228	168	0	0
T9	2071	1142	0	0
T10	628	0	0	0
T11	15667	0	0	0
T12	0	445	0	0
T21	29901	0	0	0
T22	489	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T56	507	0	0	0
T57	0	757	0	0
T73	0	118	0	0
T87	0	34045	0	0
T132	0	489	0	0
T134	0	315	0	0
T135	0	829	0	0
T136	0	69	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	50	0	0
T8	1228	1	0	0
T9	2071	3	0	0
T10	628	0	0	0
T11	15667	0	0	0
T12	0	3	0	0
T21	29901	0	0	0
T22	489	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T56	507	0	0	0
T57	0	3	0	0
T73	0	2	0	0
T87	0	1	0	0
T132	0	1	0	0
T134	0	3	0	0
T135	0	3	0	0
T136	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	6026194	0	0
T1	16004	15584	0	0
T2	8919	4895	0	0
T3	5221	4820	0	0
T4	31242	23133	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11521	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	14731	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	6028645	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	23163	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	130	0	0
T8	1228	1	0	0
T9	2071	3	0	0
T10	628	0	0	0
T11	15667	0	0	0
T12	0	3	0	0
T21	29901	0	0	0
T22	489	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T56	507	0	0	0
T57	0	3	0	0
T71	0	4	0	0
T72	0	7	0	0
T73	0	2	0	0
T74	0	3	0	0
T75	0	5	0	0
T76	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	72	0	0
T8	1228	1	0	0
T9	2071	3	0	0
T10	628	0	0	0
T11	15667	0	0	0
T12	0	3	0	0
T21	29901	0	0	0
T22	489	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T56	507	0	0	0
T57	0	3	0	0
T73	0	2	0	0
T74	0	2	0	0
T75	0	3	0	0
T86	0	1	0	0
T132	0	1	0	0
T134	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	50	0	0
T8	1228	1	0	0
T9	2071	3	0	0
T10	628	0	0	0
T11	15667	0	0	0
T12	0	3	0	0
T21	29901	0	0	0
T22	489	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T56	507	0	0	0
T57	0	3	0	0
T73	0	2	0	0
T87	0	1	0	0
T132	0	1	0	0
T134	0	3	0	0
T135	0	3	0	0
T136	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	50	0	0
T8	1228	1	0	0
T9	2071	3	0	0
T10	628	0	0	0
T11	15667	0	0	0
T12	0	3	0	0
T21	29901	0	0	0
T22	489	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T56	507	0	0	0
T57	0	3	0	0
T73	0	2	0	0
T87	0	1	0	0
T132	0	1	0	0
T134	0	3	0	0
T135	0	3	0	0
T136	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	399391	0	0
T8	1228	167	0	0
T9	2071	1139	0	0
T10	628	0	0	0
T11	15667	0	0	0
T12	0	442	0	0
T21	29901	0	0	0
T22	489	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T56	507	0	0	0
T57	0	754	0	0
T73	0	116	0	0
T87	0	34044	0	0
T132	0	488	0	0
T134	0	312	0	0
T135	0	826	0	0
T136	0	68	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8668790	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	23163	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	1357581	0	0
T8	1228	38	0	0
T9	2071	185	0	0
T10	628	0	0	0
T11	15667	0	0	0
T12	0	330	0	0
T21	29901	0	0	0
T22	489	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T56	507	0	0	0
T57	0	220	0	0
T73	0	231	0	0
T87	0	82	0	0
T132	0	103	0	0
T134	0	840	0	0
T135	0	532	0	0
T136	0	466	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T8,T9,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T8,T9,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T8,T9,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T12
1	0	Covered	T5,T1,T6
1	1	Covered	T8,T9,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T12,T57
0	1	Covered	T8,T12,T83
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T12,T57
0	1	Unreachable
1	0	Covered	T9,T12,T57

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T9,T12
DetectSt	168	Covered	T8,T9,T12
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T9,T12,T57

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T9,T12
DebounceSt->IdleSt	163	Covered	T8,T87,T136
DetectSt->IdleSt	186	Covered	T8,T12,T83
DetectSt->StableSt	191	Covered	T9,T12,T57
IdleSt->DebounceSt	148	Covered	T8,T9,T12
StableSt->IdleSt	206	Covered	T9,T12,T57

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T9,T12
0	1	Covered	T8,T9,T12
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T12
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T9,T12
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T77,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T9,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T87,T136
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T9,T12
DetectSt	-	-	-	-	1	-	-	Covered	T8,T12,T83
DetectSt	-	-	-	-	0	1	-	Covered	T9,T12,T57
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T12,T57
StableSt	-	-	-	-	-	-	0	Covered	T9,T12,T57
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9322746	195	0	0
CntIncr_A	9322746	258673	0	0
CntNoWrap_A	9322746	8666140	0	0
DetectStDropOut_A	9322746	19	0	0
DetectedOut_A	9322746	1044985	0	0
DetectedPulseOut_A	9322746	54	0	0
DisabledIdleSt_A	9322746	6026194	0	0
DisabledNoDetection_A	9322746	6028645	0	0
EnterDebounceSt_A	9322746	124	0	0
EnterDetectSt_A	9322746	73	0	0
EnterStableSt_A	9322746	54	0	0
PulseIsPulse_A	9322746	54	0	0
StayInStableSt	9322746	1044931	0	0
gen_high_event_sva.HighLevelEvent_A	9322746	8668790	0	0
gen_high_level_sva.HighLevelEvent_A	9322746	8668790	0	0
gen_sticky_sva.StableStDropOut_A	9322746	326434	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	195	0	0
T8	1228	3	0	0
T9	2071	6	0	0
T10	628	0	0	0
T11	15667	0	0	0
T12	0	10	0	0
T21	29901	0	0	0
T22	489	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T56	507	0	0	0
T57	0	6	0	0
T71	0	2	0	0
T72	0	4	0	0
T73	0	4	0	0
T74	0	2	0	0
T75	0	2	0	0
T76	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	258673	0	0
T8	1228	156	0	0
T9	2071	48	0	0
T10	628	0	0	0
T11	15667	0	0	0
T12	0	230	0	0
T21	29901	0	0	0
T22	489	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T56	507	0	0	0
T57	0	225	0	0
T71	0	49	0	0
T72	0	166	0	0
T73	0	40	0	0
T74	0	30	0	0
T75	0	34	0	0
T76	0	52	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8666140	0	0
T1	16004	15584	0	0
T2	8919	4895	0	0
T3	5221	4820	0	0
T4	31242	23133	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11521	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	14731	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	19	0	0
T8	1228	1	0	0
T9	2071	0	0	0
T10	628	0	0	0
T11	15667	0	0	0
T12	0	4	0	0
T21	29901	0	0	0
T22	489	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T56	507	0	0	0
T83	0	2	0	0
T136	0	3	0	0
T139	0	2	0	0
T153	0	3	0	0
T154	0	2	0	0
T155	0	1	0	0
T156	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	1044985	0	0
T9	2071	196	0	0
T10	628	0	0	0
T11	15667	0	0	0
T12	0	97	0	0
T21	29901	0	0	0
T22	489	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T56	507	0	0	0
T57	0	784	0	0
T67	502	0	0	0
T71	0	266	0	0
T72	0	943	0	0
T73	0	76	0	0
T74	0	76	0	0
T75	0	235	0	0
T76	0	235	0	0
T132	0	264	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	54	0	0
T9	2071	3	0	0
T10	628	0	0	0
T11	15667	0	0	0
T12	0	1	0	0
T21	29901	0	0	0
T22	489	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T56	507	0	0	0
T57	0	3	0	0
T67	502	0	0	0
T71	0	1	0	0
T72	0	2	0	0
T73	0	2	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T132	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	6026194	0	0
T1	16004	15584	0	0
T2	8919	4895	0	0
T3	5221	4820	0	0
T4	31242	23133	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11521	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	14731	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	6028645	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	23163	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	124	0	0
T8	1228	2	0	0
T9	2071	3	0	0
T10	628	0	0	0
T11	15667	0	0	0
T12	0	5	0	0
T21	29901	0	0	0
T22	489	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T56	507	0	0	0
T57	0	3	0	0
T71	0	1	0	0
T72	0	2	0	0
T73	0	2	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	73	0	0
T8	1228	1	0	0
T9	2071	3	0	0
T10	628	0	0	0
T11	15667	0	0	0
T12	0	5	0	0
T21	29901	0	0	0
T22	489	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T56	507	0	0	0
T57	0	3	0	0
T71	0	1	0	0
T72	0	2	0	0
T73	0	2	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	54	0	0
T9	2071	3	0	0
T10	628	0	0	0
T11	15667	0	0	0
T12	0	1	0	0
T21	29901	0	0	0
T22	489	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T56	507	0	0	0
T57	0	3	0	0
T67	502	0	0	0
T71	0	1	0	0
T72	0	2	0	0
T73	0	2	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T132	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	54	0	0
T9	2071	3	0	0
T10	628	0	0	0
T11	15667	0	0	0
T12	0	1	0	0
T21	29901	0	0	0
T22	489	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T56	507	0	0	0
T57	0	3	0	0
T67	502	0	0	0
T71	0	1	0	0
T72	0	2	0	0
T73	0	2	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T132	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	1044931	0	0
T9	2071	193	0	0
T10	628	0	0	0
T11	15667	0	0	0
T12	0	96	0	0
T21	29901	0	0	0
T22	489	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T56	507	0	0	0
T57	0	781	0	0
T67	502	0	0	0
T71	0	265	0	0
T72	0	941	0	0
T73	0	74	0	0
T74	0	75	0	0
T75	0	234	0	0
T76	0	234	0	0
T132	0	263	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8668790	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	23163	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8668790	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	23163	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	326434	0	0
T9	2071	1333	0	0
T10	628	0	0	0
T11	15667	0	0	0
T12	0	315	0	0
T21	29901	0	0	0
T22	489	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T56	507	0	0	0
T57	0	155	0	0
T67	502	0	0	0
T71	0	244	0	0
T72	0	408	0	0
T73	0	325	0	0
T74	0	459	0	0
T75	0	563	0	0
T76	0	198	0	0
T132	0	381	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T4,T35,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T4,T35,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T4,T35,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T10,T30
1	0	Covered	T5,T1,T6
1	1	Covered	T4,T35,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T35,T41
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T35,T41
0	1	Covered	T35,T157,T158
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T35,T41
1	-	Covered	T35,T157,T158

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T35,T41
DetectSt	168	Covered	T4,T35,T41
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T4,T35,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T35,T41
DebounceSt->IdleSt	163	Covered	T159,T77,T78
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T4,T35,T41
IdleSt->DebounceSt	148	Covered	T4,T35,T41
StableSt->IdleSt	206	Covered	T4,T35,T157

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T35,T41
0	1	Covered	T4,T35,T41
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T35,T41
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T35,T41
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T77,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T35,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T159
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T35,T41
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T4,T35,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T35,T157,T158
StableSt	-	-	-	-	-	-	0	Covered	T4,T35,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9322746	65	0	0
CntIncr_A	9322746	132795	0	0
CntNoWrap_A	9322746	8666270	0	0
DetectStDropOut_A	9322746	0	0	0
DetectedOut_A	9322746	53064	0	0
DetectedPulseOut_A	9322746	31	0	0
DisabledIdleSt_A	9322746	8152463	0	0
DisabledNoDetection_A	9322746	8154873	0	0
EnterDebounceSt_A	9322746	34	0	0
EnterDetectSt_A	9322746	31	0	0
EnterStableSt_A	9322746	31	0	0
PulseIsPulse_A	9322746	31	0	0
StayInStableSt	9322746	53012	0	0
gen_high_level_sva.HighLevelEvent_A	9322746	8668790	0	0
gen_not_sticky_sva.StableStDropOut_A	9322746	10	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	65	0	0
T4	31242	2	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T35	0	2	0	0
T41	0	2	0	0
T52	522	0	0	0
T152	0	2	0	0
T157	0	2	0	0
T158	0	4	0	0
T160	0	2	0	0
T161	0	2	0	0
T162	0	2	0	0
T163	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	132795	0	0
T4	31242	28	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T35	0	28	0	0
T41	0	83	0	0
T52	522	0	0	0
T152	0	99	0	0
T157	0	15	0	0
T158	0	96950	0	0
T160	0	60	0	0
T161	0	42	0	0
T162	0	90	0	0
T163	0	34077	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8666270	0	0
T1	16004	15584	0	0
T2	8919	4895	0	0
T3	5221	4820	0	0
T4	31242	23131	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11521	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	14731	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	53064	0	0
T4	31242	115	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T35	0	42	0	0
T41	0	209	0	0
T52	522	0	0	0
T152	0	270	0	0
T157	0	13	0	0
T158	0	79	0	0
T160	0	48	0	0
T161	0	41	0	0
T162	0	39	0	0
T163	0	50306	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	31	0	0
T4	31242	1	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T35	0	1	0	0
T41	0	1	0	0
T52	522	0	0	0
T152	0	1	0	0
T157	0	1	0	0
T158	0	2	0	0
T160	0	1	0	0
T161	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8152463	0	0
T1	16004	15584	0	0
T2	8919	4895	0	0
T3	5221	4820	0	0
T4	31242	22755	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11521	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	14731	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8154873	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	22784	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	34	0	0
T4	31242	1	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T35	0	1	0	0
T41	0	1	0	0
T52	522	0	0	0
T152	0	1	0	0
T157	0	1	0	0
T158	0	2	0	0
T160	0	1	0	0
T161	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	31	0	0
T4	31242	1	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T35	0	1	0	0
T41	0	1	0	0
T52	522	0	0	0
T152	0	1	0	0
T157	0	1	0	0
T158	0	2	0	0
T160	0	1	0	0
T161	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	31	0	0
T4	31242	1	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T35	0	1	0	0
T41	0	1	0	0
T52	522	0	0	0
T152	0	1	0	0
T157	0	1	0	0
T158	0	2	0	0
T160	0	1	0	0
T161	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	31	0	0
T4	31242	1	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T35	0	1	0	0
T41	0	1	0	0
T52	522	0	0	0
T152	0	1	0	0
T157	0	1	0	0
T158	0	2	0	0
T160	0	1	0	0
T161	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	53012	0	0
T4	31242	113	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T35	0	41	0	0
T41	0	207	0	0
T52	522	0	0	0
T152	0	268	0	0
T157	0	12	0	0
T158	0	76	0	0
T160	0	46	0	0
T161	0	39	0	0
T162	0	37	0	0
T163	0	50304	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8668790	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	23163	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	10	0	0
T35	724	1	0	0
T36	835	0	0	0
T69	16921	0	0	0
T106	0	1	0	0
T128	428	0	0	0
T129	964	0	0	0
T130	536	0	0	0
T131	402	0	0	0
T144	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T164	0	1	0	0
T165	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	503	0	0	0
T170	506	0	0	0
T171	494	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T4,T37,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T4,T37,T31

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T4,T37,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T37,T31
1	0	Covered	T5,T1,T6
1	1	Covered	T4,T37,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T37,T31
0	1	Covered	T161,T165,T168
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T37,T31
0	1	Covered	T4,T35,T152
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T37,T31
1	-	Covered	T4,T35,T152

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T37,T31
DetectSt	168	Covered	T4,T37,T31
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T4,T37,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T37,T31
DebounceSt->IdleSt	163	Covered	T77,T172,T173
DetectSt->IdleSt	186	Covered	T161,T165,T168
DetectSt->StableSt	191	Covered	T4,T37,T31
IdleSt->DebounceSt	148	Covered	T4,T37,T31
StableSt->IdleSt	206	Covered	T4,T35,T152

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T37,T31
0	1	Covered	T4,T37,T31
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T37,T31
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T37,T31
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T77,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T37,T31
DebounceSt	-	0	1	0	-	-	-	Covered	T172,T173
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T37,T31
DetectSt	-	-	-	-	1	-	-	Covered	T161,T165,T168
DetectSt	-	-	-	-	0	1	-	Covered	T4,T37,T31
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T35,T152
StableSt	-	-	-	-	-	-	0	Covered	T4,T37,T31
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9322746	96	0	0
CntIncr_A	9322746	46020	0	0
CntNoWrap_A	9322746	8666239	0	0
DetectStDropOut_A	9322746	4	0	0
DetectedOut_A	9322746	17141	0	0
DetectedPulseOut_A	9322746	42	0	0
DisabledIdleSt_A	9322746	8592776	0	0
DisabledNoDetection_A	9322746	8595189	0	0
EnterDebounceSt_A	9322746	50	0	0
EnterDetectSt_A	9322746	46	0	0
EnterStableSt_A	9322746	42	0	0
PulseIsPulse_A	9322746	42	0	0
StayInStableSt	9322746	17081	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9322746	2640	0	0
gen_low_level_sva.LowLevelEvent_A	9322746	8668790	0	0
gen_not_sticky_sva.StableStDropOut_A	9322746	24	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	96	0	0
T4	31242	4	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T31	0	2	0	0
T33	0	2	0	0
T35	0	4	0	0
T36	0	2	0	0
T37	0	2	0	0
T40	0	2	0	0
T52	522	0	0	0
T152	0	2	0	0
T160	0	2	0	0
T174	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	46020	0	0
T4	31242	58	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T31	0	100	0	0
T33	0	10	0	0
T35	0	56	0	0
T36	0	76	0	0
T37	0	30	0	0
T40	0	21	0	0
T52	522	0	0	0
T152	0	99	0	0
T160	0	60	0	0
T174	0	61	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8666239	0	0
T1	16004	15584	0	0
T2	8919	4895	0	0
T3	5221	4820	0	0
T4	31242	23129	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11521	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	14731	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	4	0	0
T99	6228	0	0	0
T161	536	1	0	0
T165	0	1	0	0
T168	0	1	0	0
T175	0	1	0	0
T176	2655	0	0	0
T177	29322	0	0	0
T178	8940	0	0	0
T179	17119	0	0	0
T180	522	0	0	0
T181	522	0	0	0
T182	503	0	0	0
T183	507	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	17141	0	0
T4	31242	275	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T31	0	169	0	0
T33	0	54	0	0
T35	0	173	0	0
T36	0	152	0	0
T37	0	42	0	0
T40	0	57	0	0
T52	522	0	0	0
T152	0	35	0	0
T160	0	43	0	0
T174	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	42	0	0
T4	31242	2	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T31	0	1	0	0
T33	0	1	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T52	522	0	0	0
T152	0	1	0	0
T160	0	1	0	0
T174	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8592776	0	0
T1	16004	15584	0	0
T2	8919	4895	0	0
T3	5221	4820	0	0
T4	31242	22542	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11521	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	14731	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8595189	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	22570	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	50	0	0
T4	31242	2	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T31	0	1	0	0
T33	0	1	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T52	522	0	0	0
T152	0	1	0	0
T160	0	1	0	0
T174	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	46	0	0
T4	31242	2	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T31	0	1	0	0
T33	0	1	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T52	522	0	0	0
T152	0	1	0	0
T160	0	1	0	0
T174	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	42	0	0
T4	31242	2	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T31	0	1	0	0
T33	0	1	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T52	522	0	0	0
T152	0	1	0	0
T160	0	1	0	0
T174	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	42	0	0
T4	31242	2	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T31	0	1	0	0
T33	0	1	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T52	522	0	0	0
T152	0	1	0	0
T160	0	1	0	0
T174	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	17081	0	0
T4	31242	273	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T31	0	167	0	0
T33	0	52	0	0
T35	0	170	0	0
T36	0	150	0	0
T37	0	40	0	0
T40	0	55	0	0
T52	522	0	0	0
T152	0	34	0	0
T160	0	42	0	0
T174	0	41	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	2640	0	0
T1	16004	0	0	0
T2	8919	15	0	0
T3	5221	0	0	0
T4	31242	45	0	0
T5	422	3	0	0
T6	502	5	0	0
T7	13942	5	0	0
T10	0	1	0	0
T13	443	5	0	0
T14	505	4	0	0
T15	15149	0	0	0
T16	0	1	0	0
T52	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8668790	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	23163	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	24	0	0
T4	31242	2	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T35	0	1	0	0
T52	522	0	0	0
T106	0	1	0	0
T152	0	1	0	0
T159	0	2	0	0
T160	0	1	0	0
T184	0	1	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	1	0	0