Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T29,T39,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T29,T39,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T29,T39,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T29,T33
1	0	Covered	T5,T1,T6
1	1	Covered	T29,T39,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T29,T39,T40
0	1	Covered	T85,T165
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T39,T40
0	1	Covered	T29,T184,T185
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T29,T39,T40
1	-	Covered	T29,T184,T185

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T29,T39,T40
DetectSt	168	Covered	T29,T39,T40
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T29,T39,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T29,T39,T40
DebounceSt->IdleSt	163	Covered	T77,T78
DetectSt->IdleSt	186	Covered	T85,T165
DetectSt->StableSt	191	Covered	T29,T39,T40
IdleSt->DebounceSt	148	Covered	T29,T39,T40
StableSt->IdleSt	206	Covered	T29,T40,T184

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T29,T39,T40
0	1	Covered	T29,T39,T40
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T29,T39,T40
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T29,T39,T40
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T77,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T29,T39,T40
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T29,T39,T40
DetectSt	-	-	-	-	1	-	-	Covered	T85,T165
DetectSt	-	-	-	-	0	1	-	Covered	T29,T39,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T29,T184,T185
StableSt	-	-	-	-	-	-	0	Covered	T29,T39,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9322746	66	0	0
CntIncr_A	9322746	132875	0	0
CntNoWrap_A	9322746	8666269	0	0
DetectStDropOut_A	9322746	2	0	0
DetectedOut_A	9322746	14459	0	0
DetectedPulseOut_A	9322746	30	0	0
DisabledIdleSt_A	9322746	8155991	0	0
DisabledNoDetection_A	9322746	8158401	0	0
EnterDebounceSt_A	9322746	34	0	0
EnterDetectSt_A	9322746	32	0	0
EnterStableSt_A	9322746	30	0	0
PulseIsPulse_A	9322746	30	0	0
StayInStableSt	9322746	14413	0	0
gen_high_level_sva.HighLevelEvent_A	9322746	8668790	0	0
gen_not_sticky_sva.StableStDropOut_A	9322746	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	66	0	0
T29	25501	4	0	0
T39	0	2	0	0
T40	0	2	0	0
T45	8351	0	0	0
T46	14939	0	0	0
T47	13072	0	0	0
T63	493	0	0	0
T64	494	0	0	0
T85	0	2	0	0
T158	0	4	0	0
T163	0	2	0	0
T184	0	2	0	0
T185	0	2	0	0
T188	0	2	0	0
T189	0	2	0	0
T190	502	0	0	0
T191	522	0	0	0
T192	523	0	0	0
T193	1396	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	132875	0	0
T29	25501	118	0	0
T39	0	53	0	0
T40	0	90	0	0
T45	8351	0	0	0
T46	14939	0	0	0
T47	13072	0	0	0
T63	493	0	0	0
T64	494	0	0	0
T85	0	95	0	0
T158	0	96950	0	0
T163	0	34077	0	0
T184	0	86	0	0
T185	0	64	0	0
T188	0	94	0	0
T189	0	47	0	0
T190	502	0	0	0
T191	522	0	0	0
T192	523	0	0	0
T193	1396	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8666269	0	0
T1	16004	15584	0	0
T2	8919	4895	0	0
T3	5221	4820	0	0
T4	31242	23133	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11521	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	14731	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	2	0	0
T85	11766	1	0	0
T165	0	1	0	0
T189	889	0	0	0
T194	18096	0	0	0
T195	449	0	0	0
T196	5068	0	0	0
T197	434	0	0	0
T198	12544	0	0	0
T199	21113	0	0	0
T200	525	0	0	0
T201	3055	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	14459	0	0
T29	25501	53	0	0
T39	0	94	0	0
T40	0	65	0	0
T45	8351	0	0	0
T46	14939	0	0	0
T47	13072	0	0	0
T63	493	0	0	0
T64	494	0	0	0
T158	0	12054	0	0
T163	0	40	0	0
T184	0	68	0	0
T185	0	327	0	0
T188	0	43	0	0
T189	0	44	0	0
T190	502	0	0	0
T191	522	0	0	0
T192	523	0	0	0
T193	1396	0	0	0
T202	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	30	0	0
T29	25501	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T45	8351	0	0	0
T46	14939	0	0	0
T47	13072	0	0	0
T63	493	0	0	0
T64	494	0	0	0
T158	0	2	0	0
T163	0	1	0	0
T184	0	1	0	0
T185	0	1	0	0
T188	0	1	0	0
T189	0	1	0	0
T190	502	0	0	0
T191	522	0	0	0
T192	523	0	0	0
T193	1396	0	0	0
T202	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8155991	0	0
T1	16004	15584	0	0
T2	8919	4895	0	0
T3	5221	4820	0	0
T4	31242	23133	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11307	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	14731	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8158401	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	23163	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11313	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	34	0	0
T29	25501	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T45	8351	0	0	0
T46	14939	0	0	0
T47	13072	0	0	0
T63	493	0	0	0
T64	494	0	0	0
T85	0	1	0	0
T158	0	2	0	0
T163	0	1	0	0
T184	0	1	0	0
T185	0	1	0	0
T188	0	1	0	0
T189	0	1	0	0
T190	502	0	0	0
T191	522	0	0	0
T192	523	0	0	0
T193	1396	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	32	0	0
T29	25501	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T45	8351	0	0	0
T46	14939	0	0	0
T47	13072	0	0	0
T63	493	0	0	0
T64	494	0	0	0
T85	0	1	0	0
T158	0	2	0	0
T163	0	1	0	0
T184	0	1	0	0
T185	0	1	0	0
T188	0	1	0	0
T189	0	1	0	0
T190	502	0	0	0
T191	522	0	0	0
T192	523	0	0	0
T193	1396	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	30	0	0
T29	25501	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T45	8351	0	0	0
T46	14939	0	0	0
T47	13072	0	0	0
T63	493	0	0	0
T64	494	0	0	0
T158	0	2	0	0
T163	0	1	0	0
T184	0	1	0	0
T185	0	1	0	0
T188	0	1	0	0
T189	0	1	0	0
T190	502	0	0	0
T191	522	0	0	0
T192	523	0	0	0
T193	1396	0	0	0
T202	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	30	0	0
T29	25501	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T45	8351	0	0	0
T46	14939	0	0	0
T47	13072	0	0	0
T63	493	0	0	0
T64	494	0	0	0
T158	0	2	0	0
T163	0	1	0	0
T184	0	1	0	0
T185	0	1	0	0
T188	0	1	0	0
T189	0	1	0	0
T190	502	0	0	0
T191	522	0	0	0
T192	523	0	0	0
T193	1396	0	0	0
T202	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	14413	0	0
T29	25501	50	0	0
T39	0	92	0	0
T40	0	63	0	0
T45	8351	0	0	0
T46	14939	0	0	0
T47	13072	0	0	0
T63	493	0	0	0
T64	494	0	0	0
T158	0	12052	0	0
T163	0	39	0	0
T184	0	67	0	0
T185	0	326	0	0
T188	0	42	0	0
T189	0	43	0	0
T190	502	0	0	0
T191	522	0	0	0
T192	523	0	0	0
T193	1396	0	0	0
T202	0	39	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8668790	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	23163	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	14	0	0
T29	25501	1	0	0
T45	8351	0	0	0
T46	14939	0	0	0
T47	13072	0	0	0
T63	493	0	0	0
T64	494	0	0	0
T144	0	1	0	0
T158	0	2	0	0
T163	0	1	0	0
T173	0	1	0	0
T184	0	1	0	0
T185	0	1	0	0
T188	0	1	0	0
T189	0	1	0	0
T190	502	0	0	0
T191	522	0	0	0
T192	523	0	0	0
T193	1396	0	0	0
T202	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T37,T34,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T37,T34,T31

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T37,T34,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T37,T34
1	0	Covered	T5,T1,T6
1	1	Covered	T37,T34,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T37,T34,T31
0	1	Covered	T79,T40,T80
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T37,T34,T31
0	1	Covered	T37,T34,T31
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T37,T34,T31
1	-	Covered	T37,T34,T31

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T37,T34,T31
DetectSt	168	Covered	T37,T34,T31
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T37,T34,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T37,T34,T31
DebounceSt->IdleSt	163	Covered	T85,T203,T77
DetectSt->IdleSt	186	Covered	T79,T40,T80
DetectSt->StableSt	191	Covered	T37,T34,T31
IdleSt->DebounceSt	148	Covered	T37,T34,T31
StableSt->IdleSt	206	Covered	T37,T34,T31

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T37,T34,T31
0	1	Covered	T37,T34,T31
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T37,T34,T31
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T37,T34,T31
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T77,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T37,T34,T31
DebounceSt	-	0	1	0	-	-	-	Covered	T203,T144
DebounceSt	-	0	0	-	-	-	-	Covered	T37,T34,T31
DetectSt	-	-	-	-	1	-	-	Covered	T79,T40,T80
DetectSt	-	-	-	-	0	1	-	Covered	T37,T34,T31
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T37,T34,T31
StableSt	-	-	-	-	-	-	0	Covered	T37,T34,T31
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9322746	126	0	0
CntIncr_A	9322746	115147	0	0
CntNoWrap_A	9322746	8666209	0	0
DetectStDropOut_A	9322746	7	0	0
DetectedOut_A	9322746	135283	0	0
DetectedPulseOut_A	9322746	54	0	0
DisabledIdleSt_A	9322746	8358512	0	0
DisabledNoDetection_A	9322746	8360916	0	0
EnterDebounceSt_A	9322746	66	0	0
EnterDetectSt_A	9322746	61	0	0
EnterStableSt_A	9322746	54	0	0
PulseIsPulse_A	9322746	54	0	0
StayInStableSt	9322746	135208	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9322746	3029	0	0
gen_low_level_sva.LowLevelEvent_A	9322746	8668790	0	0
gen_not_sticky_sva.StableStDropOut_A	9322746	33	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	126	0	0
T28	39034	0	0	0
T31	0	2	0	0
T32	0	4	0	0
T34	3913	4	0	0
T37	646	4	0	0
T40	0	4	0	0
T41	0	2	0	0
T44	666	0	0	0
T59	79590	0	0	0
T62	496	0	0	0
T79	0	2	0	0
T89	502	0	0	0
T90	526	0	0	0
T152	0	2	0	0
T160	0	4	0	0
T174	0	4	0	0
T204	426	0	0	0
T205	409	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	115147	0	0
T28	39034	0	0	0
T31	0	100	0	0
T32	0	88	0	0
T34	3913	48	0	0
T37	646	60	0	0
T40	0	42	0	0
T41	0	83	0	0
T44	666	0	0	0
T59	79590	0	0	0
T62	496	0	0	0
T79	0	83	0	0
T89	502	0	0	0
T90	526	0	0	0
T152	0	99	0	0
T160	0	120	0	0
T174	0	122	0	0
T204	426	0	0	0
T205	409	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8666209	0	0
T1	16004	15584	0	0
T2	8919	4895	0	0
T3	5221	4820	0	0
T4	31242	23133	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11521	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	14731	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	7	0	0
T40	0	1	0	0
T50	28469	0	0	0
T73	1097	0	0	0
T79	829	1	0	0
T80	0	1	0	0
T92	4916	0	0	0
T163	0	1	0	0
T168	0	1	0	0
T173	0	1	0	0
T202	0	1	0	0
T206	402	0	0	0
T207	1356	0	0	0
T208	27952	0	0	0
T209	403	0	0	0
T210	494	0	0	0
T211	622	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	135283	0	0
T28	39034	0	0	0
T31	0	144	0	0
T32	0	80	0	0
T34	3913	128	0	0
T37	646	105	0	0
T40	0	5	0	0
T41	0	456	0	0
T44	666	0	0	0
T59	79590	0	0	0
T62	496	0	0	0
T89	502	0	0	0
T90	526	0	0	0
T152	0	128	0	0
T160	0	57	0	0
T174	0	156	0	0
T204	426	0	0	0
T205	409	0	0	0
T212	0	344	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	54	0	0
T28	39034	0	0	0
T31	0	1	0	0
T32	0	2	0	0
T34	3913	2	0	0
T37	646	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T44	666	0	0	0
T59	79590	0	0	0
T62	496	0	0	0
T89	502	0	0	0
T90	526	0	0	0
T152	0	1	0	0
T160	0	2	0	0
T174	0	2	0	0
T204	426	0	0	0
T205	409	0	0	0
T212	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8358512	0	0
T1	16004	15584	0	0
T2	8919	4895	0	0
T3	5221	4820	0	0
T4	31242	23133	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11307	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	14731	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8360916	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	23163	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11313	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	66	0	0
T28	39034	0	0	0
T31	0	1	0	0
T32	0	2	0	0
T34	3913	2	0	0
T37	646	2	0	0
T40	0	2	0	0
T41	0	1	0	0
T44	666	0	0	0
T59	79590	0	0	0
T62	496	0	0	0
T79	0	1	0	0
T89	502	0	0	0
T90	526	0	0	0
T152	0	1	0	0
T160	0	2	0	0
T174	0	2	0	0
T204	426	0	0	0
T205	409	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	61	0	0
T28	39034	0	0	0
T31	0	1	0	0
T32	0	2	0	0
T34	3913	2	0	0
T37	646	2	0	0
T40	0	2	0	0
T41	0	1	0	0
T44	666	0	0	0
T59	79590	0	0	0
T62	496	0	0	0
T79	0	1	0	0
T89	502	0	0	0
T90	526	0	0	0
T152	0	1	0	0
T160	0	2	0	0
T174	0	2	0	0
T204	426	0	0	0
T205	409	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	54	0	0
T28	39034	0	0	0
T31	0	1	0	0
T32	0	2	0	0
T34	3913	2	0	0
T37	646	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T44	666	0	0	0
T59	79590	0	0	0
T62	496	0	0	0
T89	502	0	0	0
T90	526	0	0	0
T152	0	1	0	0
T160	0	2	0	0
T174	0	2	0	0
T204	426	0	0	0
T205	409	0	0	0
T212	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	54	0	0
T28	39034	0	0	0
T31	0	1	0	0
T32	0	2	0	0
T34	3913	2	0	0
T37	646	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T44	666	0	0	0
T59	79590	0	0	0
T62	496	0	0	0
T89	502	0	0	0
T90	526	0	0	0
T152	0	1	0	0
T160	0	2	0	0
T174	0	2	0	0
T204	426	0	0	0
T205	409	0	0	0
T212	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	135208	0	0
T28	39034	0	0	0
T31	0	143	0	0
T32	0	78	0	0
T34	3913	126	0	0
T37	646	102	0	0
T40	0	4	0	0
T41	0	454	0	0
T44	666	0	0	0
T59	79590	0	0	0
T62	496	0	0	0
T89	502	0	0	0
T90	526	0	0	0
T152	0	126	0	0
T160	0	54	0	0
T174	0	153	0	0
T204	426	0	0	0
T205	409	0	0	0
T212	0	343	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	3029	0	0
T1	16004	0	0	0
T2	8919	12	0	0
T3	5221	0	0	0
T4	31242	43	0	0
T5	422	3	0	0
T6	502	8	0	0
T7	13942	9	0	0
T10	0	1	0	0
T13	443	5	0	0
T14	505	5	0	0
T15	15149	0	0	0
T16	0	2	0	0
T52	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8668790	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	23163	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	33	0	0
T28	39034	0	0	0
T31	0	1	0	0
T32	0	2	0	0
T34	3913	2	0	0
T37	646	1	0	0
T40	0	1	0	0
T44	666	0	0	0
T59	79590	0	0	0
T62	496	0	0	0
T85	0	1	0	0
T89	502	0	0	0
T90	526	0	0	0
T160	0	1	0	0
T162	0	1	0	0
T174	0	1	0	0
T204	426	0	0	0
T205	409	0	0	0
T212	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T4,T37,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T4,T37,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T4,T37,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T37,T34
1	0	Covered	T5,T1,T6
1	1	Covered	T4,T37,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T37,T34
0	1	Covered	T144
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T37,T34
0	1	Covered	T4,T37,T34
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T37,T34
1	-	Covered	T4,T37,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T37,T34
DetectSt	168	Covered	T4,T37,T34
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T4,T37,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T37,T34
DebounceSt->IdleSt	163	Covered	T29,T152,T77
DetectSt->IdleSt	186	Covered	T144
DetectSt->StableSt	191	Covered	T4,T37,T34
IdleSt->DebounceSt	148	Covered	T4,T37,T34
StableSt->IdleSt	206	Covered	T4,T37,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T37,T34
0	1	Covered	T4,T37,T34
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T37,T34
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T37,T34
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T77,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T37,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T29,T152,T213
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T37,T34
DetectSt	-	-	-	-	1	-	-	Covered	T144
DetectSt	-	-	-	-	0	1	-	Covered	T4,T37,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T37,T34
StableSt	-	-	-	-	-	-	0	Covered	T4,T37,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9322746	146	0	0
CntIncr_A	9322746	144673	0	0
CntNoWrap_A	9322746	8666189	0	0
DetectStDropOut_A	9322746	2	0	0
DetectedOut_A	9322746	117877	0	0
DetectedPulseOut_A	9322746	67	0	0
DisabledIdleSt_A	9322746	8329175	0	0
DisabledNoDetection_A	9322746	8331577	0	0
EnterDebounceSt_A	9322746	78	0	0
EnterDetectSt_A	9322746	69	0	0
EnterStableSt_A	9322746	67	0	0
PulseIsPulse_A	9322746	67	0	0
StayInStableSt	9322746	117779	0	0
gen_high_level_sva.HighLevelEvent_A	9322746	8668790	0	0
gen_not_sticky_sva.StableStDropOut_A	9322746	36	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	146	0	0
T4	31242	2	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T29	0	1	0	0
T33	0	2	0	0
T34	0	2	0	0
T37	0	4	0	0
T39	0	4	0	0
T52	522	0	0	0
T79	0	2	0	0
T152	0	3	0	0
T160	0	2	0	0
T174	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	144673	0	0
T4	31242	28	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T29	0	59	0	0
T33	0	10	0	0
T34	0	24	0	0
T37	0	60	0	0
T39	0	106	0	0
T52	522	0	0	0
T79	0	83	0	0
T152	0	198	0	0
T160	0	60	0	0
T174	0	122	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8666189	0	0
T1	16004	15584	0	0
T2	8919	4895	0	0
T3	5221	4820	0	0
T4	31242	23131	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11521	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	14731	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	2	0	0
T108	6986	0	0	0
T140	31850	0	0	0
T144	23233	2	0	0
T166	6865	0	0	0
T173	39106	0	0	0
T214	14258	0	0	0
T215	538	0	0	0
T216	408	0	0	0
T217	23379	0	0	0
T218	6715	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	117877	0	0
T4	31242	14	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T33	0	1	0	0
T34	0	19	0	0
T37	0	123	0	0
T39	0	79	0	0
T40	0	155	0	0
T52	522	0	0	0
T79	0	208	0	0
T152	0	35	0	0
T160	0	108	0	0
T174	0	263	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	67	0	0
T4	31242	1	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T37	0	2	0	0
T39	0	2	0	0
T40	0	1	0	0
T52	522	0	0	0
T79	0	1	0	0
T152	0	1	0	0
T160	0	1	0	0
T174	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8329175	0	0
T1	16004	15584	0	0
T2	8919	4895	0	0
T3	5221	4820	0	0
T4	31242	22542	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11521	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	14731	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8331577	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	22570	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	78	0	0
T4	31242	1	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T29	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T37	0	2	0	0
T39	0	2	0	0
T52	522	0	0	0
T79	0	1	0	0
T152	0	2	0	0
T160	0	1	0	0
T174	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	69	0	0
T4	31242	1	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T37	0	2	0	0
T39	0	2	0	0
T40	0	1	0	0
T52	522	0	0	0
T79	0	1	0	0
T152	0	1	0	0
T160	0	1	0	0
T174	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	67	0	0
T4	31242	1	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T37	0	2	0	0
T39	0	2	0	0
T40	0	1	0	0
T52	522	0	0	0
T79	0	1	0	0
T152	0	1	0	0
T160	0	1	0	0
T174	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	67	0	0
T4	31242	1	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T37	0	2	0	0
T39	0	2	0	0
T40	0	1	0	0
T52	522	0	0	0
T79	0	1	0	0
T152	0	1	0	0
T160	0	1	0	0
T174	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	117779	0	0
T4	31242	13	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T34	0	18	0	0
T37	0	120	0	0
T39	0	76	0	0
T40	0	153	0	0
T52	522	0	0	0
T79	0	207	0	0
T152	0	34	0	0
T160	0	107	0	0
T174	0	260	0	0
T185	0	196	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8668790	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	23163	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	36	0	0
T4	31242	1	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0
T52	522	0	0	0
T79	0	1	0	0
T152	0	1	0	0
T160	0	1	0	0
T174	0	1	0	0
T185	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T30,T37,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T30,T37,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T30,T37,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T30,T37,T31
1	0	Covered	T5,T1,T6
1	1	Covered	T30,T37,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T30,T37,T35
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T30,T37,T35
0	1	Covered	T30,T37,T35
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T30,T37,T35
1	-	Covered	T30,T37,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T30,T37,T35
DetectSt	168	Covered	T30,T37,T35
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T30,T37,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T30,T37,T35
DebounceSt->IdleSt	163	Covered	T85,T77,T165
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T30,T37,T35
IdleSt->DebounceSt	148	Covered	T30,T37,T35
StableSt->IdleSt	206	Covered	T30,T37,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T30,T37,T35
0	1	Covered	T30,T37,T35
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T30,T37,T35
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T30,T37,T35
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T77,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T30,T37,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T165
DebounceSt	-	0	0	-	-	-	-	Covered	T30,T37,T35
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T30,T37,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T30,T37,T35
StableSt	-	-	-	-	-	-	0	Covered	T30,T37,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9322746	73	0	0
CntIncr_A	9322746	84537	0	0
CntNoWrap_A	9322746	8666262	0	0
DetectStDropOut_A	9322746	0	0	0
DetectedOut_A	9322746	7871	0	0
DetectedPulseOut_A	9322746	35	0	0
DisabledIdleSt_A	9322746	8098144	0	0
DisabledNoDetection_A	9322746	8100555	0	0
EnterDebounceSt_A	9322746	39	0	0
EnterDetectSt_A	9322746	35	0	0
EnterStableSt_A	9322746	35	0	0
PulseIsPulse_A	9322746	35	0	0
StayInStableSt	9322746	7821	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9322746	6601	0	0
gen_low_level_sva.LowLevelEvent_A	9322746	8668790	0	0
gen_not_sticky_sva.StableStDropOut_A	9322746	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	73	0	0
T28	39034	0	0	0
T30	832	4	0	0
T33	0	2	0	0
T34	3913	0	0	0
T35	0	2	0	0
T36	0	2	0	0
T37	646	2	0	0
T39	0	2	0	0
T59	79590	0	0	0
T62	496	0	0	0
T79	0	2	0	0
T89	502	0	0	0
T90	526	0	0	0
T157	0	4	0	0
T174	0	2	0	0
T185	0	2	0	0
T204	426	0	0	0
T205	409	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	84537	0	0
T28	39034	0	0	0
T30	832	126	0	0
T33	0	10	0	0
T34	3913	0	0	0
T35	0	28	0	0
T36	0	76	0	0
T37	646	30	0	0
T39	0	53	0	0
T59	79590	0	0	0
T62	496	0	0	0
T79	0	83	0	0
T89	502	0	0	0
T90	526	0	0	0
T157	0	30	0	0
T174	0	61	0	0
T185	0	64	0	0
T204	426	0	0	0
T205	409	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8666262	0	0
T1	16004	15584	0	0
T2	8919	4895	0	0
T3	5221	4820	0	0
T4	31242	23133	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11521	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	14731	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	7871	0	0
T28	39034	0	0	0
T30	832	84	0	0
T33	0	54	0	0
T34	3913	0	0	0
T35	0	73	0	0
T36	0	272	0	0
T37	646	21	0	0
T39	0	163	0	0
T59	79590	0	0	0
T62	496	0	0	0
T79	0	44	0	0
T89	502	0	0	0
T90	526	0	0	0
T157	0	77	0	0
T174	0	37	0	0
T185	0	107	0	0
T204	426	0	0	0
T205	409	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	35	0	0
T28	39034	0	0	0
T30	832	2	0	0
T33	0	1	0	0
T34	3913	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	646	1	0	0
T39	0	1	0	0
T59	79590	0	0	0
T62	496	0	0	0
T79	0	1	0	0
T89	502	0	0	0
T90	526	0	0	0
T157	0	2	0	0
T174	0	1	0	0
T185	0	1	0	0
T204	426	0	0	0
T205	409	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8098144	0	0
T1	16004	15584	0	0
T2	8919	4895	0	0
T3	5221	4820	0	0
T4	31242	23133	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11521	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	14731	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8100555	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	23163	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	39	0	0
T28	39034	0	0	0
T30	832	2	0	0
T33	0	1	0	0
T34	3913	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	646	1	0	0
T39	0	1	0	0
T59	79590	0	0	0
T62	496	0	0	0
T79	0	1	0	0
T89	502	0	0	0
T90	526	0	0	0
T157	0	2	0	0
T174	0	1	0	0
T185	0	1	0	0
T204	426	0	0	0
T205	409	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	35	0	0
T28	39034	0	0	0
T30	832	2	0	0
T33	0	1	0	0
T34	3913	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	646	1	0	0
T39	0	1	0	0
T59	79590	0	0	0
T62	496	0	0	0
T79	0	1	0	0
T89	502	0	0	0
T90	526	0	0	0
T157	0	2	0	0
T174	0	1	0	0
T185	0	1	0	0
T204	426	0	0	0
T205	409	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	35	0	0
T28	39034	0	0	0
T30	832	2	0	0
T33	0	1	0	0
T34	3913	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	646	1	0	0
T39	0	1	0	0
T59	79590	0	0	0
T62	496	0	0	0
T79	0	1	0	0
T89	502	0	0	0
T90	526	0	0	0
T157	0	2	0	0
T174	0	1	0	0
T185	0	1	0	0
T204	426	0	0	0
T205	409	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	35	0	0
T28	39034	0	0	0
T30	832	2	0	0
T33	0	1	0	0
T34	3913	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	646	1	0	0
T39	0	1	0	0
T59	79590	0	0	0
T62	496	0	0	0
T79	0	1	0	0
T89	502	0	0	0
T90	526	0	0	0
T157	0	2	0	0
T174	0	1	0	0
T185	0	1	0	0
T204	426	0	0	0
T205	409	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	7821	0	0
T28	39034	0	0	0
T30	832	81	0	0
T33	0	52	0	0
T34	3913	0	0	0
T35	0	72	0	0
T36	0	270	0	0
T37	646	20	0	0
T39	0	162	0	0
T59	79590	0	0	0
T62	496	0	0	0
T79	0	42	0	0
T89	502	0	0	0
T90	526	0	0	0
T157	0	74	0	0
T174	0	36	0	0
T185	0	106	0	0
T204	426	0	0	0
T205	409	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	6601	0	0
T1	16004	26	0	0
T2	8919	21	0	0
T3	5221	12	0	0
T4	31242	57	0	0
T5	422	2	0	0
T6	502	7	0	0
T7	13942	16	0	0
T13	443	7	0	0
T14	505	3	0	0
T15	15149	22	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8668790	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	23163	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	20	0	0
T28	39034	0	0	0
T30	832	1	0	0
T34	3913	0	0	0
T35	0	1	0	0
T37	646	1	0	0
T39	0	1	0	0
T59	79590	0	0	0
T62	496	0	0	0
T89	502	0	0	0
T90	526	0	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0
T174	0	1	0	0
T185	0	1	0	0
T187	0	1	0	0
T204	426	0	0	0
T205	409	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T38,T31,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T38,T31,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T38,T31,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T38,T31
1	0	Covered	T5,T1,T6
1	1	Covered	T38,T31,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T38,T31,T35
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T38,T31,T35
0	1	Covered	T38,T31,T35
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T38,T31,T35
1	-	Covered	T38,T31,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T38,T31,T35
DetectSt	168	Covered	T38,T31,T35
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T38,T31,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T38,T31,T35
DebounceSt->IdleSt	163	Covered	T174,T219,T85
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T38,T31,T35
IdleSt->DebounceSt	148	Covered	T38,T31,T35
StableSt->IdleSt	206	Covered	T38,T31,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T38,T31,T35
0	1	Covered	T38,T31,T35
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T38,T31,T35
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T38,T31,T35
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T77,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T38,T31,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T174,T219
DebounceSt	-	0	0	-	-	-	-	Covered	T38,T31,T35
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T38,T31,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T38,T31,T35
StableSt	-	-	-	-	-	-	0	Covered	T38,T31,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9322746	114	0	0
CntIncr_A	9322746	102543	0	0
CntNoWrap_A	9322746	8666221	0	0
DetectStDropOut_A	9322746	0	0	0
DetectedOut_A	9322746	66325	0	0
DetectedPulseOut_A	9322746	55	0	0
DisabledIdleSt_A	9322746	8384773	0	0
DisabledNoDetection_A	9322746	8387182	0	0
EnterDebounceSt_A	9322746	61	0	0
EnterDetectSt_A	9322746	55	0	0
EnterStableSt_A	9322746	55	0	0
PulseIsPulse_A	9322746	55	0	0
StayInStableSt	9322746	66245	0	0
gen_high_level_sva.HighLevelEvent_A	9322746	8668790	0	0
gen_not_sticky_sva.StableStDropOut_A	9322746	30	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	114	0	0
T29	25501	0	0	0
T31	0	4	0	0
T32	0	2	0	0
T33	0	2	0	0
T35	0	2	0	0
T38	899	2	0	0
T40	0	4	0	0
T41	0	2	0	0
T45	8351	0	0	0
T46	14939	0	0	0
T47	13072	0	0	0
T63	493	0	0	0
T79	0	2	0	0
T127	6945	0	0	0
T152	0	2	0	0
T174	0	5	0	0
T190	502	0	0	0
T191	522	0	0	0
T220	427	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	102543	0	0
T29	25501	0	0	0
T31	0	200	0	0
T32	0	44	0	0
T33	0	10	0	0
T35	0	28	0	0
T38	899	97	0	0
T40	0	42	0	0
T41	0	83	0	0
T45	8351	0	0	0
T46	14939	0	0	0
T47	13072	0	0	0
T63	493	0	0	0
T79	0	83	0	0
T127	6945	0	0	0
T152	0	99	0	0
T174	0	183	0	0
T190	502	0	0	0
T191	522	0	0	0
T220	427	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8666221	0	0
T1	16004	15584	0	0
T2	8919	4895	0	0
T3	5221	4820	0	0
T4	31242	23133	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11521	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	14731	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	66325	0	0
T29	25501	0	0	0
T31	0	185	0	0
T32	0	348	0	0
T33	0	66	0	0
T35	0	209	0	0
T38	899	42	0	0
T40	0	122	0	0
T41	0	324	0	0
T45	8351	0	0	0
T46	14939	0	0	0
T47	13072	0	0	0
T63	493	0	0	0
T79	0	40	0	0
T127	6945	0	0	0
T152	0	271	0	0
T174	0	48	0	0
T190	502	0	0	0
T191	522	0	0	0
T220	427	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	55	0	0
T29	25501	0	0	0
T31	0	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T35	0	1	0	0
T38	899	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T45	8351	0	0	0
T46	14939	0	0	0
T47	13072	0	0	0
T63	493	0	0	0
T79	0	1	0	0
T127	6945	0	0	0
T152	0	1	0	0
T174	0	2	0	0
T190	502	0	0	0
T191	522	0	0	0
T220	427	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8384773	0	0
T1	16004	15584	0	0
T2	8919	4895	0	0
T3	5221	4820	0	0
T4	31242	23133	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11521	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	14731	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8387182	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	23163	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	61	0	0
T29	25501	0	0	0
T31	0	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T35	0	1	0	0
T38	899	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T45	8351	0	0	0
T46	14939	0	0	0
T47	13072	0	0	0
T63	493	0	0	0
T79	0	1	0	0
T127	6945	0	0	0
T152	0	1	0	0
T174	0	3	0	0
T190	502	0	0	0
T191	522	0	0	0
T220	427	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	55	0	0
T29	25501	0	0	0
T31	0	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T35	0	1	0	0
T38	899	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T45	8351	0	0	0
T46	14939	0	0	0
T47	13072	0	0	0
T63	493	0	0	0
T79	0	1	0	0
T127	6945	0	0	0
T152	0	1	0	0
T174	0	2	0	0
T190	502	0	0	0
T191	522	0	0	0
T220	427	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	55	0	0
T29	25501	0	0	0
T31	0	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T35	0	1	0	0
T38	899	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T45	8351	0	0	0
T46	14939	0	0	0
T47	13072	0	0	0
T63	493	0	0	0
T79	0	1	0	0
T127	6945	0	0	0
T152	0	1	0	0
T174	0	2	0	0
T190	502	0	0	0
T191	522	0	0	0
T220	427	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	55	0	0
T29	25501	0	0	0
T31	0	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T35	0	1	0	0
T38	899	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T45	8351	0	0	0
T46	14939	0	0	0
T47	13072	0	0	0
T63	493	0	0	0
T79	0	1	0	0
T127	6945	0	0	0
T152	0	1	0	0
T174	0	2	0	0
T190	502	0	0	0
T191	522	0	0	0
T220	427	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	66245	0	0
T29	25501	0	0	0
T31	0	182	0	0
T32	0	347	0	0
T33	0	64	0	0
T35	0	208	0	0
T38	899	41	0	0
T40	0	120	0	0
T41	0	323	0	0
T45	8351	0	0	0
T46	14939	0	0	0
T47	13072	0	0	0
T63	493	0	0	0
T79	0	39	0	0
T127	6945	0	0	0
T152	0	269	0	0
T174	0	46	0	0
T190	502	0	0	0
T191	522	0	0	0
T220	427	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8668790	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	23163	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	30	0	0
T29	25501	0	0	0
T31	0	1	0	0
T32	0	1	0	0
T35	0	1	0	0
T38	899	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T45	8351	0	0	0
T46	14939	0	0	0
T47	13072	0	0	0
T63	493	0	0	0
T79	0	1	0	0
T127	6945	0	0	0
T174	0	2	0	0
T184	0	1	0	0
T185	0	2	0	0
T190	502	0	0	0
T191	522	0	0	0
T220	427	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T34,T35,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T34,T35,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T34,T35,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T30
1	0	Covered	T5,T1,T6
1	1	Covered	T34,T35,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T34,T35,T36
0	1	Covered	T85
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T34,T35,T36
0	1	Covered	T34,T185,T164
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T34,T35,T36
1	-	Covered	T34,T185,T164

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T34,T35,T36
DetectSt	168	Covered	T34,T35,T36
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T34,T35,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T34,T35,T36
DebounceSt->IdleSt	163	Covered	T159,T77,T78
DetectSt->IdleSt	186	Covered	T85
DetectSt->StableSt	191	Covered	T34,T35,T36
IdleSt->DebounceSt	148	Covered	T34,T35,T36
StableSt->IdleSt	206	Covered	T34,T185,T164

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T34,T35,T36
0	1	Covered	T34,T35,T36
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T34,T35,T36
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T77,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T34,T35,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T159
DebounceSt	-	0	0	-	-	-	-	Covered	T34,T35,T36
DetectSt	-	-	-	-	1	-	-	Covered	T85
DetectSt	-	-	-	-	0	1	-	Covered	T34,T35,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T34,T185,T164
StableSt	-	-	-	-	-	-	0	Covered	T34,T35,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9322746	49	0	0
CntIncr_A	9322746	1423	0	0
CntNoWrap_A	9322746	8666286	0	0
DetectStDropOut_A	9322746	1	0	0
DetectedOut_A	9322746	2222	0	0
DetectedPulseOut_A	9322746	22	0	0
DisabledIdleSt_A	9322746	8651864	0	0
DisabledNoDetection_A	9322746	8654281	0	0
EnterDebounceSt_A	9322746	26	0	0
EnterDetectSt_A	9322746	23	0	0
EnterStableSt_A	9322746	22	0	0
PulseIsPulse_A	9322746	22	0	0
StayInStableSt	9322746	2187	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9322746	6218	0	0
gen_low_level_sva.LowLevelEvent_A	9322746	8668790	0	0
gen_not_sticky_sva.StableStDropOut_A	9322746	9	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	49	0	0
T28	39034	0	0	0
T32	0	2	0	0
T34	3913	4	0	0
T35	0	2	0	0
T36	0	2	0	0
T44	666	0	0	0
T59	79590	0	0	0
T79	0	2	0	0
T85	0	2	0	0
T89	502	0	0	0
T90	526	0	0	0
T159	0	1	0	0
T184	0	2	0	0
T185	0	4	0	0
T204	426	0	0	0
T205	409	0	0	0
T219	0	2	0	0
T221	441	0	0	0
T222	441	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	1423	0	0
T28	39034	0	0	0
T32	0	44	0	0
T34	3913	48	0	0
T35	0	28	0	0
T36	0	76	0	0
T44	666	0	0	0
T59	79590	0	0	0
T79	0	83	0	0
T85	0	95	0	0
T89	502	0	0	0
T90	526	0	0	0
T159	0	68	0	0
T184	0	86	0	0
T185	0	128	0	0
T204	426	0	0	0
T205	409	0	0	0
T219	0	58	0	0
T221	441	0	0	0
T222	441	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8666286	0	0
T1	16004	15584	0	0
T2	8919	4895	0	0
T3	5221	4820	0	0
T4	31242	23133	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11521	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	14731	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	1	0	0
T85	11766	1	0	0
T189	889	0	0	0
T194	18096	0	0	0
T195	449	0	0	0
T196	5068	0	0	0
T197	434	0	0	0
T198	12544	0	0	0
T199	21113	0	0	0
T200	525	0	0	0
T201	3055	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	2222	0	0
T28	39034	0	0	0
T32	0	39	0	0
T34	3913	83	0	0
T35	0	49	0	0
T36	0	272	0	0
T44	666	0	0	0
T59	79590	0	0	0
T79	0	128	0	0
T89	502	0	0	0
T90	526	0	0	0
T164	0	306	0	0
T184	0	412	0	0
T185	0	155	0	0
T204	426	0	0	0
T205	409	0	0	0
T213	0	19	0	0
T219	0	45	0	0
T221	441	0	0	0
T222	441	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	22	0	0
T28	39034	0	0	0
T32	0	1	0	0
T34	3913	2	0	0
T35	0	1	0	0
T36	0	1	0	0
T44	666	0	0	0
T59	79590	0	0	0
T79	0	1	0	0
T89	502	0	0	0
T90	526	0	0	0
T164	0	2	0	0
T184	0	1	0	0
T185	0	2	0	0
T204	426	0	0	0
T205	409	0	0	0
T213	0	1	0	0
T219	0	1	0	0
T221	441	0	0	0
T222	441	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8651864	0	0
T1	16004	15584	0	0
T2	8919	4895	0	0
T3	5221	4820	0	0
T4	31242	22920	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11307	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	14731	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8654281	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	22949	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11313	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	26	0	0
T28	39034	0	0	0
T32	0	1	0	0
T34	3913	2	0	0
T35	0	1	0	0
T36	0	1	0	0
T44	666	0	0	0
T59	79590	0	0	0
T79	0	1	0	0
T85	0	1	0	0
T89	502	0	0	0
T90	526	0	0	0
T159	0	1	0	0
T184	0	1	0	0
T185	0	2	0	0
T204	426	0	0	0
T205	409	0	0	0
T219	0	1	0	0
T221	441	0	0	0
T222	441	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	23	0	0
T28	39034	0	0	0
T32	0	1	0	0
T34	3913	2	0	0
T35	0	1	0	0
T36	0	1	0	0
T44	666	0	0	0
T59	79590	0	0	0
T79	0	1	0	0
T85	0	1	0	0
T89	502	0	0	0
T90	526	0	0	0
T164	0	2	0	0
T184	0	1	0	0
T185	0	2	0	0
T204	426	0	0	0
T205	409	0	0	0
T219	0	1	0	0
T221	441	0	0	0
T222	441	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	22	0	0
T28	39034	0	0	0
T32	0	1	0	0
T34	3913	2	0	0
T35	0	1	0	0
T36	0	1	0	0
T44	666	0	0	0
T59	79590	0	0	0
T79	0	1	0	0
T89	502	0	0	0
T90	526	0	0	0
T164	0	2	0	0
T184	0	1	0	0
T185	0	2	0	0
T204	426	0	0	0
T205	409	0	0	0
T213	0	1	0	0
T219	0	1	0	0
T221	441	0	0	0
T222	441	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	22	0	0
T28	39034	0	0	0
T32	0	1	0	0
T34	3913	2	0	0
T35	0	1	0	0
T36	0	1	0	0
T44	666	0	0	0
T59	79590	0	0	0
T79	0	1	0	0
T89	502	0	0	0
T90	526	0	0	0
T164	0	2	0	0
T184	0	1	0	0
T185	0	2	0	0
T204	426	0	0	0
T205	409	0	0	0
T213	0	1	0	0
T219	0	1	0	0
T221	441	0	0	0
T222	441	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	2187	0	0
T28	39034	0	0	0
T32	0	37	0	0
T34	3913	81	0	0
T35	0	47	0	0
T36	0	270	0	0
T44	666	0	0	0
T59	79590	0	0	0
T79	0	126	0	0
T89	502	0	0	0
T90	526	0	0	0
T164	0	303	0	0
T184	0	410	0	0
T185	0	152	0	0
T204	426	0	0	0
T205	409	0	0	0
T213	0	18	0	0
T219	0	43	0	0
T221	441	0	0	0
T222	441	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	6218	0	0
T1	16004	28	0	0
T2	8919	12	0	0
T3	5221	13	0	0
T4	31242	57	0	0
T5	422	3	0	0
T6	502	6	0	0
T7	13942	20	0	0
T13	443	5	0	0
T14	505	2	0	0
T15	15149	35	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8668790	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	23163	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	9	0	0
T28	39034	0	0	0
T34	3913	2	0	0
T44	666	0	0	0
T59	79590	0	0	0
T89	502	0	0	0
T90	526	0	0	0
T106	0	1	0	0
T164	0	1	0	0
T172	0	1	0	0
T185	0	1	0	0
T204	426	0	0	0
T205	409	0	0	0
T213	0	1	0	0
T221	441	0	0	0
T222	441	0	0	0
T223	0	1	0	0
T224	0	1	0	0