Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.26	93.48	85.71		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.26	93.48	85.71		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T4,T7,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T4,T7,T30

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T4,T7,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T10
1	0	Covered	T5,T1,T6
1	1	Covered	T4,T7,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T30
0	1	Covered	T84
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T30
0	1	Covered	T4,T7,T37
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T7,T30
1	-	Covered	T4,T7,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T7,T30
DetectSt	168	Covered	T4,T7,T30
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T4,T7,T30

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T7,T30
DebounceSt->IdleSt	163	Covered	T4,T29,T225
DetectSt->IdleSt	186	Covered	T84
DetectSt->StableSt	191	Covered	T4,T7,T30
IdleSt->DebounceSt	148	Covered	T4,T7,T30
StableSt->IdleSt	206	Covered	T4,T7,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T7,T30
0	1	Covered	T4,T7,T30
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T30
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T7,T30
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T77,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T7,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T29,T225
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T7,T30
DetectSt	-	-	-	-	1	-	-	Covered	T84
DetectSt	-	-	-	-	0	1	-	Covered	T4,T7,T30
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T7,T37
StableSt	-	-	-	-	-	-	0	Covered	T4,T7,T30
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9322746	113	0	0
CntIncr_A	9322746	102509	0	0
CntNoWrap_A	9322746	8666222	0	0
DetectStDropOut_A	9322746	1	0	0
DetectedOut_A	9322746	61953	0	0
DetectedPulseOut_A	9322746	52	0	0
DisabledIdleSt_A	9322746	8385512	0	0
DisabledNoDetection_A	9322746	8387918	0	0
EnterDebounceSt_A	9322746	61	0	0
EnterDetectSt_A	9322746	53	0	0
EnterStableSt_A	9322746	52	0	0
PulseIsPulse_A	9322746	52	0	0
StayInStableSt	9322746	61875	0	0
gen_high_level_sva.HighLevelEvent_A	9322746	8668790	0	0
gen_not_sticky_sva.StableStDropOut_A	9322746	26	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	113	0	0
T4	31242	7	0	0
T7	13942	4	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T29	0	1	0	0
T30	0	2	0	0
T31	0	2	0	0
T33	0	2	0	0
T34	0	4	0	0
T37	0	2	0	0
T38	0	2	0	0
T52	522	0	0	0
T174	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	102509	0	0
T4	31242	116	0	0
T7	13942	56	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T29	0	59	0	0
T30	0	63	0	0
T31	0	100	0	0
T33	0	10	0	0
T34	0	48	0	0
T37	0	30	0	0
T38	0	97	0	0
T52	522	0	0	0
T174	0	122	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8666222	0	0
T1	16004	15584	0	0
T2	8919	4895	0	0
T3	5221	4820	0	0
T4	31242	23126	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11517	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	14731	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	1	0	0
T84	564	1	0	0
T85	11766	0	0	0
T194	18096	0	0	0
T195	449	0	0	0
T196	5068	0	0	0
T197	434	0	0	0
T198	12544	0	0	0
T226	421	0	0	0
T227	495	0	0	0
T228	11806	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	61953	0	0
T4	31242	145	0	0
T7	13942	52	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T30	0	259	0	0
T31	0	168	0	0
T33	0	66	0	0
T34	0	117	0	0
T37	0	11	0	0
T38	0	60	0	0
T52	522	0	0	0
T152	0	405	0	0
T174	0	308	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	52	0	0
T4	31242	3	0	0
T7	13942	2	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T30	0	1	0	0
T31	0	1	0	0
T33	0	1	0	0
T34	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T52	522	0	0	0
T152	0	1	0	0
T174	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8385512	0	0
T1	16004	15584	0	0
T2	8919	4895	0	0
T3	5221	4820	0	0
T4	31242	22542	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11307	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	14731	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8387918	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	22570	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11313	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	61	0	0
T4	31242	4	0	0
T7	13942	2	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T29	0	1	0	0
T30	0	1	0	0
T31	0	1	0	0
T33	0	1	0	0
T34	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T52	522	0	0	0
T174	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	53	0	0
T4	31242	3	0	0
T7	13942	2	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T30	0	1	0	0
T31	0	1	0	0
T33	0	1	0	0
T34	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T52	522	0	0	0
T152	0	1	0	0
T174	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	52	0	0
T4	31242	3	0	0
T7	13942	2	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T30	0	1	0	0
T31	0	1	0	0
T33	0	1	0	0
T34	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T52	522	0	0	0
T152	0	1	0	0
T174	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	52	0	0
T4	31242	3	0	0
T7	13942	2	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T30	0	1	0	0
T31	0	1	0	0
T33	0	1	0	0
T34	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T52	522	0	0	0
T152	0	1	0	0
T174	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	61875	0	0
T4	31242	141	0	0
T7	13942	49	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T30	0	257	0	0
T31	0	167	0	0
T33	0	64	0	0
T34	0	114	0	0
T37	0	10	0	0
T38	0	58	0	0
T52	522	0	0	0
T152	0	403	0	0
T174	0	305	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8668790	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	23163	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	26	0	0
T4	31242	2	0	0
T7	13942	1	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T31	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T52	522	0	0	0
T158	0	2	0	0
T160	0	1	0	0
T162	0	1	0	0
T174	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T4,T7,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T4,T7,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T4,T7,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T30
1	0	Covered	T5,T1,T6
1	1	Covered	T4,T7,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T34
0	1	Covered	T173
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T34
0	1	Covered	T4,T7,T34
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T7,T34
1	-	Covered	T4,T7,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T7,T34
DetectSt	168	Covered	T4,T7,T34
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T4,T7,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T7,T34
DebounceSt->IdleSt	163	Covered	T158,T77,T144
DetectSt->IdleSt	186	Covered	T173
DetectSt->StableSt	191	Covered	T4,T7,T34
IdleSt->DebounceSt	148	Covered	T4,T7,T34
StableSt->IdleSt	206	Covered	T4,T7,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T7,T34
0	1	Covered	T4,T7,T34
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T34
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T7,T34
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T77,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T7,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T158,T144
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T7,T34
DetectSt	-	-	-	-	1	-	-	Covered	T173
DetectSt	-	-	-	-	0	1	-	Covered	T4,T7,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T7,T34
StableSt	-	-	-	-	-	-	0	Covered	T4,T7,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9322746	74	0	0
CntIncr_A	9322746	132922	0	0
CntNoWrap_A	9322746	8666261	0	0
DetectStDropOut_A	9322746	1	0	0
DetectedOut_A	9322746	103670	0	0
DetectedPulseOut_A	9322746	34	0	0
DisabledIdleSt_A	9322746	8151623	0	0
DisabledNoDetection_A	9322746	8154027	0	0
EnterDebounceSt_A	9322746	39	0	0
EnterDetectSt_A	9322746	35	0	0
EnterStableSt_A	9322746	34	0	0
PulseIsPulse_A	9322746	34	0	0
StayInStableSt	9322746	103623	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9322746	6172	0	0
gen_low_level_sva.LowLevelEvent_A	9322746	8668790	0	0
gen_not_sticky_sva.StableStDropOut_A	9322746	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	74	0	0
T4	31242	4	0	0
T7	13942	2	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T34	0	2	0	0
T40	0	2	0	0
T41	0	2	0	0
T52	522	0	0	0
T158	0	3	0	0
T160	0	2	0	0
T162	0	2	0	0
T174	0	2	0	0
T184	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	132922	0	0
T4	31242	56	0	0
T7	13942	28	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T34	0	24	0	0
T40	0	21	0	0
T41	0	83	0	0
T52	522	0	0	0
T158	0	96950	0	0
T160	0	60	0	0
T162	0	90	0	0
T174	0	61	0	0
T184	0	86	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8666261	0	0
T1	16004	15584	0	0
T2	8919	4895	0	0
T3	5221	4820	0	0
T4	31242	23129	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11519	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	14731	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	1	0	0
T140	31850	0	0	0
T166	6865	0	0	0
T173	39106	1	0	0
T216	408	0	0	0
T217	23379	0	0	0
T218	6715	0	0	0
T229	522	0	0	0
T230	402	0	0	0
T231	8690	0	0	0
T232	16444	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	103670	0	0
T4	31242	197	0	0
T7	13942	71	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T34	0	42	0	0
T40	0	92	0	0
T41	0	77	0	0
T52	522	0	0	0
T158	0	55569	0	0
T160	0	40	0	0
T162	0	38	0	0
T174	0	43	0	0
T184	0	68	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	34	0	0
T4	31242	2	0	0
T7	13942	1	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T34	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T52	522	0	0	0
T158	0	1	0	0
T160	0	1	0	0
T162	0	1	0	0
T174	0	1	0	0
T184	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8151623	0	0
T1	16004	15584	0	0
T2	8919	4895	0	0
T3	5221	4820	0	0
T4	31242	22755	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11307	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	14731	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8154027	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	22784	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11313	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	39	0	0
T4	31242	2	0	0
T7	13942	1	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T34	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T52	522	0	0	0
T158	0	2	0	0
T160	0	1	0	0
T162	0	1	0	0
T174	0	1	0	0
T184	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	35	0	0
T4	31242	2	0	0
T7	13942	1	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T34	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T52	522	0	0	0
T158	0	1	0	0
T160	0	1	0	0
T162	0	1	0	0
T174	0	1	0	0
T184	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	34	0	0
T4	31242	2	0	0
T7	13942	1	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T34	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T52	522	0	0	0
T158	0	1	0	0
T160	0	1	0	0
T162	0	1	0	0
T174	0	1	0	0
T184	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	34	0	0
T4	31242	2	0	0
T7	13942	1	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T34	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T52	522	0	0	0
T158	0	1	0	0
T160	0	1	0	0
T162	0	1	0	0
T174	0	1	0	0
T184	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	103623	0	0
T4	31242	194	0	0
T7	13942	70	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T34	0	41	0	0
T40	0	91	0	0
T41	0	76	0	0
T52	522	0	0	0
T158	0	55567	0	0
T160	0	39	0	0
T162	0	36	0	0
T174	0	42	0	0
T184	0	67	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	6172	0	0
T1	16004	23	0	0
T2	8919	12	0	0
T3	5221	8	0	0
T4	31242	58	0	0
T5	422	3	0	0
T6	502	3	0	0
T7	13942	20	0	0
T13	443	4	0	0
T14	505	5	0	0
T15	15149	29	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8668790	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	23163	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	21	0	0
T4	31242	1	0	0
T7	13942	1	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T34	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T52	522	0	0	0
T160	0	1	0	0
T163	0	1	0	0
T174	0	1	0	0
T184	0	1	0	0
T225	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T10,T30,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T10,T30,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T10,T30,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T30,T37
1	0	Covered	T5,T1,T6
1	1	Covered	T10,T30,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T30,T37
0	1	Covered	T40,T202,T233
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T30,T37
0	1	Covered	T30,T174,T33
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T30,T37
1	-	Covered	T30,T174,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T30,T37
DetectSt	168	Covered	T10,T30,T37
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T10,T30,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T30,T37
DebounceSt->IdleSt	163	Covered	T174,T163,T77
DetectSt->IdleSt	186	Covered	T40,T202,T233
DetectSt->StableSt	191	Covered	T10,T30,T37
IdleSt->DebounceSt	148	Covered	T10,T30,T37
StableSt->IdleSt	206	Covered	T30,T34,T174

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T30,T37
0	1	Covered	T10,T30,T37
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T30,T37
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T30,T37
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T77,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T30,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T174,T163,T234
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T30,T37
DetectSt	-	-	-	-	1	-	-	Covered	T40,T202,T233
DetectSt	-	-	-	-	0	1	-	Covered	T10,T30,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T30,T174,T33
StableSt	-	-	-	-	-	-	0	Covered	T10,T30,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9322746	127	0	0
CntIncr_A	9322746	156808	0	0
CntNoWrap_A	9322746	8666208	0	0
DetectStDropOut_A	9322746	5	0	0
DetectedOut_A	9322746	4406	0	0
DetectedPulseOut_A	9322746	55	0	0
DisabledIdleSt_A	9322746	8313326	0	0
DisabledNoDetection_A	9322746	8315725	0	0
EnterDebounceSt_A	9322746	68	0	0
EnterDetectSt_A	9322746	60	0	0
EnterStableSt_A	9322746	55	0	0
PulseIsPulse_A	9322746	55	0	0
StayInStableSt	9322746	4323	0	0
gen_high_level_sva.HighLevelEvent_A	9322746	8668790	0	0
gen_not_sticky_sva.StableStDropOut_A	9322746	27	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	127	0	0
T10	628	2	0	0
T11	15667	0	0	0
T21	29901	0	0	0
T22	489	0	0	0
T30	0	2	0	0
T32	0	4	0	0
T33	0	2	0	0
T34	0	2	0	0
T37	0	2	0	0
T39	0	4	0	0
T40	0	4	0	0
T42	1605	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T56	507	0	0	0
T67	502	0	0	0
T160	0	2	0	0
T174	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	156808	0	0
T10	628	73	0	0
T11	15667	0	0	0
T21	29901	0	0	0
T22	489	0	0	0
T30	0	63	0	0
T32	0	88	0	0
T33	0	10	0	0
T34	0	24	0	0
T37	0	30	0	0
T39	0	106	0	0
T40	0	111	0	0
T42	1605	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T56	507	0	0	0
T67	502	0	0	0
T160	0	60	0	0
T174	0	122	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8666208	0	0
T1	16004	15584	0	0
T2	8919	4895	0	0
T3	5221	4820	0	0
T4	31242	23133	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11521	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	14731	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	5	0	0
T40	25465	1	0	0
T88	13171	0	0	0
T132	2068	0	0	0
T166	0	1	0	0
T202	0	1	0	0
T233	0	1	0	0
T235	0	1	0	0
T236	413	0	0	0
T237	880	0	0	0
T238	405	0	0	0
T239	37073	0	0	0
T240	496	0	0	0
T241	494	0	0	0
T242	27873	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	4406	0	0
T10	628	146	0	0
T11	15667	0	0	0
T21	29901	0	0	0
T22	489	0	0	0
T30	0	46	0	0
T32	0	238	0	0
T33	0	2	0	0
T34	0	53	0	0
T37	0	95	0	0
T39	0	228	0	0
T40	0	273	0	0
T42	1605	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T56	507	0	0	0
T67	502	0	0	0
T160	0	6	0	0
T174	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	55	0	0
T10	628	1	0	0
T11	15667	0	0	0
T21	29901	0	0	0
T22	489	0	0	0
T30	0	1	0	0
T32	0	2	0	0
T33	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T42	1605	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T56	507	0	0	0
T67	502	0	0	0
T160	0	1	0	0
T174	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8313326	0	0
T1	16004	15584	0	0
T2	8919	4895	0	0
T3	5221	4820	0	0
T4	31242	23133	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11521	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	14731	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8315725	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	23163	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	68	0	0
T10	628	1	0	0
T11	15667	0	0	0
T21	29901	0	0	0
T22	489	0	0	0
T30	0	1	0	0
T32	0	2	0	0
T33	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0
T42	1605	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T56	507	0	0	0
T67	502	0	0	0
T160	0	1	0	0
T174	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	60	0	0
T10	628	1	0	0
T11	15667	0	0	0
T21	29901	0	0	0
T22	489	0	0	0
T30	0	1	0	0
T32	0	2	0	0
T33	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0
T42	1605	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T56	507	0	0	0
T67	502	0	0	0
T160	0	1	0	0
T174	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	55	0	0
T10	628	1	0	0
T11	15667	0	0	0
T21	29901	0	0	0
T22	489	0	0	0
T30	0	1	0	0
T32	0	2	0	0
T33	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T42	1605	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T56	507	0	0	0
T67	502	0	0	0
T160	0	1	0	0
T174	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	55	0	0
T10	628	1	0	0
T11	15667	0	0	0
T21	29901	0	0	0
T22	489	0	0	0
T30	0	1	0	0
T32	0	2	0	0
T33	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T42	1605	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T56	507	0	0	0
T67	502	0	0	0
T160	0	1	0	0
T174	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	4323	0	0
T10	628	144	0	0
T11	15667	0	0	0
T21	29901	0	0	0
T22	489	0	0	0
T30	0	45	0	0
T32	0	235	0	0
T33	0	1	0	0
T34	0	51	0	0
T37	0	93	0	0
T39	0	225	0	0
T40	0	271	0	0
T42	1605	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T56	507	0	0	0
T67	502	0	0	0
T160	0	5	0	0
T174	0	42	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8668790	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	23163	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	27	0	0
T28	39034	0	0	0
T30	832	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	3913	0	0	0
T37	646	0	0	0
T39	0	1	0	0
T59	79590	0	0	0
T62	496	0	0	0
T84	0	1	0	0
T89	502	0	0	0
T90	526	0	0	0
T160	0	1	0	0
T163	0	1	0	0
T174	0	1	0	0
T185	0	1	0	0
T204	426	0	0	0
T205	409	0	0	0
T225	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T7,T30,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T7,T30,T33

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T7,T30,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T30,T34
1	0	Covered	T5,T1,T6
1	1	Covered	T7,T30,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T30,T33
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T30,T33
0	1	Covered	T32,T212,T162
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T30,T33
1	-	Covered	T32,T212,T162

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T30,T33
DetectSt	168	Covered	T7,T30,T33
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T7,T30,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T30,T33
DebounceSt->IdleSt	163	Covered	T77,T78
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T7,T30,T33
IdleSt->DebounceSt	148	Covered	T7,T30,T33
StableSt->IdleSt	206	Covered	T7,T32,T212

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T30,T33
0	1	Covered	T7,T30,T33
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T30,T33
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T30,T33
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T77,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T30,T33
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T30,T33
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T7,T30,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T32,T212,T162
StableSt	-	-	-	-	-	-	0	Covered	T7,T30,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9322746	54	0	0
CntIncr_A	9322746	52282	0	0
CntNoWrap_A	9322746	8666281	0	0
DetectStDropOut_A	9322746	0	0	0
DetectedOut_A	9322746	1775	0	0
DetectedPulseOut_A	9322746	26	0	0
DisabledIdleSt_A	9322746	8491468	0	0
DisabledNoDetection_A	9322746	8493882	0	0
EnterDebounceSt_A	9322746	28	0	0
EnterDetectSt_A	9322746	26	0	0
EnterStableSt_A	9322746	26	0	0
PulseIsPulse_A	9322746	26	0	0
StayInStableSt	9322746	1733	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9322746	6244	0	0
gen_low_level_sva.LowLevelEvent_A	9322746	8668790	0	0
gen_not_sticky_sva.StableStDropOut_A	9322746	10	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	54	0	0
T7	13942	2	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T30	0	2	0	0
T32	0	2	0	0
T33	0	2	0	0
T52	522	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T159	0	2	0	0
T162	0	2	0	0
T164	0	2	0	0
T189	0	2	0	0
T212	0	4	0	0
T219	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	52282	0	0
T7	13942	28	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T30	0	63	0	0
T32	0	44	0	0
T33	0	10	0	0
T52	522	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T159	0	68	0	0
T162	0	90	0	0
T164	0	77	0	0
T189	0	47	0	0
T212	0	114	0	0
T219	0	58	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8666281	0	0
T1	16004	15584	0	0
T2	8919	4895	0	0
T3	5221	4820	0	0
T4	31242	23133	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11519	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	14731	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	1775	0	0
T7	13942	41	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T30	0	42	0	0
T32	0	15	0	0
T33	0	54	0	0
T52	522	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T159	0	112	0	0
T162	0	77	0	0
T164	0	40	0	0
T189	0	255	0	0
T212	0	85	0	0
T219	0	45	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	26	0	0
T7	13942	1	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T30	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T52	522	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T159	0	1	0	0
T162	0	1	0	0
T164	0	1	0	0
T189	0	1	0	0
T212	0	2	0	0
T219	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8491468	0	0
T1	16004	15584	0	0
T2	8919	4895	0	0
T3	5221	4820	0	0
T4	31242	23133	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11307	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	14731	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8493882	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	23163	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11313	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	28	0	0
T7	13942	1	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T30	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T52	522	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T159	0	1	0	0
T162	0	1	0	0
T164	0	1	0	0
T189	0	1	0	0
T212	0	2	0	0
T219	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	26	0	0
T7	13942	1	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T30	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T52	522	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T159	0	1	0	0
T162	0	1	0	0
T164	0	1	0	0
T189	0	1	0	0
T212	0	2	0	0
T219	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	26	0	0
T7	13942	1	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T30	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T52	522	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T159	0	1	0	0
T162	0	1	0	0
T164	0	1	0	0
T189	0	1	0	0
T212	0	2	0	0
T219	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	26	0	0
T7	13942	1	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T30	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T52	522	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T159	0	1	0	0
T162	0	1	0	0
T164	0	1	0	0
T189	0	1	0	0
T212	0	2	0	0
T219	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	1733	0	0
T7	13942	39	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T30	0	40	0	0
T32	0	14	0	0
T33	0	52	0	0
T52	522	0	0	0
T53	616	0	0	0
T54	504	0	0	0
T55	582	0	0	0
T159	0	110	0	0
T162	0	76	0	0
T164	0	39	0	0
T189	0	253	0	0
T212	0	83	0	0
T219	0	43	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	6244	0	0
T1	16004	30	0	0
T2	8919	15	0	0
T3	5221	13	0	0
T4	31242	58	0	0
T5	422	1	0	0
T6	502	6	0	0
T7	13942	17	0	0
T13	443	6	0	0
T14	505	4	0	0
T15	15149	30	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8668790	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	23163	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	10	0	0
T32	885	1	0	0
T40	25465	0	0	0
T88	13171	0	0	0
T132	2068	0	0	0
T162	0	1	0	0
T164	0	1	0	0
T167	0	1	0	0
T212	0	2	0	0
T236	413	0	0	0
T237	880	0	0	0
T238	405	0	0	0
T239	37073	0	0	0
T240	496	0	0	0
T241	494	0	0	0
T243	0	1	0	0
T244	0	2	0	0
T245	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T4,T37,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T4,T37,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T4,T37,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T37,T35
1	0	Covered	T5,T1,T6
1	1	Covered	T4,T37,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T37,T35
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T37,T35
0	1	Covered	T4,T37,T35
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T37,T35
1	-	Covered	T4,T37,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T37,T35
DetectSt	168	Covered	T4,T37,T35
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T4,T37,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T37,T35
DebounceSt->IdleSt	163	Covered	T4,T160,T85
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T4,T37,T35
IdleSt->DebounceSt	148	Covered	T4,T37,T35
StableSt->IdleSt	206	Covered	T4,T37,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T37,T35
0	1	Covered	T4,T37,T35
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T37,T35
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T37,T35
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T77,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T37,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T160,T203
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T37,T35
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T4,T37,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T37,T35
StableSt	-	-	-	-	-	-	0	Covered	T4,T37,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9322746	134	0	0
CntIncr_A	9322746	98213	0	0
CntNoWrap_A	9322746	8666201	0	0
DetectStDropOut_A	9322746	0	0	0
DetectedOut_A	9322746	5131	0	0
DetectedPulseOut_A	9322746	63	0	0
DisabledIdleSt_A	9322746	8491081	0	0
DisabledNoDetection_A	9322746	8493484	0	0
EnterDebounceSt_A	9322746	72	0	0
EnterDetectSt_A	9322746	63	0	0
EnterStableSt_A	9322746	63	0	0
PulseIsPulse_A	9322746	63	0	0
StayInStableSt	9322746	5037	0	0
gen_high_level_sva.HighLevelEvent_A	9322746	8668790	0	0
gen_not_sticky_sva.StableStDropOut_A	9322746	32	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	134	0	0
T4	31242	3	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T35	0	4	0	0
T37	0	4	0	0
T39	0	2	0	0
T41	0	2	0	0
T52	522	0	0	0
T79	0	4	0	0
T80	0	2	0	0
T152	0	4	0	0
T160	0	3	0	0
T161	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	98213	0	0
T4	31242	60	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T35	0	56	0	0
T37	0	60	0	0
T39	0	53	0	0
T41	0	83	0	0
T52	522	0	0	0
T79	0	166	0	0
T80	0	60	0	0
T152	0	198	0	0
T160	0	120	0	0
T161	0	42	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8666201	0	0
T1	16004	15584	0	0
T2	8919	4895	0	0
T3	5221	4820	0	0
T4	31242	23130	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11521	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	14731	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	5131	0	0
T4	31242	5	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T35	0	128	0	0
T37	0	52	0	0
T39	0	302	0	0
T41	0	40	0	0
T52	522	0	0	0
T79	0	168	0	0
T80	0	110	0	0
T152	0	83	0	0
T160	0	6	0	0
T161	0	85	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	63	0	0
T4	31242	1	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T35	0	2	0	0
T37	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T52	522	0	0	0
T79	0	2	0	0
T80	0	1	0	0
T152	0	2	0	0
T160	0	1	0	0
T161	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8491081	0	0
T1	16004	15584	0	0
T2	8919	4895	0	0
T3	5221	4820	0	0
T4	31242	22920	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11521	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	14731	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8493484	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	22949	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	72	0	0
T4	31242	2	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T35	0	2	0	0
T37	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T52	522	0	0	0
T79	0	2	0	0
T80	0	1	0	0
T152	0	2	0	0
T160	0	2	0	0
T161	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	63	0	0
T4	31242	1	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T35	0	2	0	0
T37	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T52	522	0	0	0
T79	0	2	0	0
T80	0	1	0	0
T152	0	2	0	0
T160	0	1	0	0
T161	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	63	0	0
T4	31242	1	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T35	0	2	0	0
T37	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T52	522	0	0	0
T79	0	2	0	0
T80	0	1	0	0
T152	0	2	0	0
T160	0	1	0	0
T161	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	63	0	0
T4	31242	1	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T35	0	2	0	0
T37	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T52	522	0	0	0
T79	0	2	0	0
T80	0	1	0	0
T152	0	2	0	0
T160	0	1	0	0
T161	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	5037	0	0
T4	31242	4	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T35	0	126	0	0
T37	0	49	0	0
T39	0	301	0	0
T41	0	39	0	0
T52	522	0	0	0
T79	0	165	0	0
T80	0	108	0	0
T152	0	80	0	0
T160	0	5	0	0
T161	0	83	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8668790	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	23163	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	32	0	0
T4	31242	1	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	29901	0	0	0
T35	0	2	0	0
T37	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T52	522	0	0	0
T79	0	1	0	0
T85	0	1	0	0
T152	0	1	0	0
T160	0	1	0	0
T188	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T30,T31,T152

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T30,T31,T152

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T30,T31,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T30,T38
1	0	Covered	T5,T1,T6
1	1	Covered	T30,T31,T152

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T30,T31,T32
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T30,T31,T32
0	1	Covered	T30,T32,T184
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T30,T31,T32
1	-	Covered	T30,T32,T184

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T30,T31,T152
DetectSt	168	Covered	T30,T31,T32
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T30,T31,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T30,T31,T32
DebounceSt->IdleSt	163	Covered	T152,T77,T104
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T30,T31,T32
IdleSt->DebounceSt	148	Covered	T30,T31,T152
StableSt->IdleSt	206	Covered	T30,T32,T184

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T30,T31,T152
0	1	Covered	T30,T31,T152
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T30,T31,T32
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T30,T31,T152
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T77,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T30,T31,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T152
DebounceSt	-	0	0	-	-	-	-	Covered	T30,T31,T152
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T30,T31,T32
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T30,T32,T184
StableSt	-	-	-	-	-	-	0	Covered	T30,T31,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9322746	63	0	0
CntIncr_A	9322746	45269	0	0
CntNoWrap_A	9322746	8666272	0	0
DetectStDropOut_A	9322746	0	0	0
DetectedOut_A	9322746	2352	0	0
DetectedPulseOut_A	9322746	30	0	0
DisabledIdleSt_A	9322746	8592933	0	0
DisabledNoDetection_A	9322746	8595350	0	0
EnterDebounceSt_A	9322746	34	0	0
EnterDetectSt_A	9322746	30	0	0
EnterStableSt_A	9322746	30	0	0
PulseIsPulse_A	9322746	30	0	0
StayInStableSt	9322746	2309	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9322746	6918	0	0
gen_low_level_sva.LowLevelEvent_A	9322746	8668790	0	0
gen_not_sticky_sva.StableStDropOut_A	9322746	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	63	0	0
T28	39034	0	0	0
T30	832	2	0	0
T31	0	2	0	0
T32	0	4	0	0
T34	3913	0	0	0
T37	646	0	0	0
T59	79590	0	0	0
T62	496	0	0	0
T89	502	0	0	0
T90	526	0	0	0
T152	0	1	0	0
T184	0	2	0	0
T185	0	2	0	0
T188	0	2	0	0
T189	0	4	0	0
T201	0	2	0	0
T203	0	2	0	0
T204	426	0	0	0
T205	409	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	45269	0	0
T28	39034	0	0	0
T30	832	63	0	0
T31	0	100	0	0
T32	0	88	0	0
T34	3913	0	0	0
T37	646	0	0	0
T59	79590	0	0	0
T62	496	0	0	0
T89	502	0	0	0
T90	526	0	0	0
T152	0	99	0	0
T184	0	86	0	0
T185	0	64	0	0
T188	0	94	0	0
T189	0	94	0	0
T201	0	80	0	0
T203	0	43527	0	0
T204	426	0	0	0
T205	409	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8666272	0	0
T1	16004	15584	0	0
T2	8919	4895	0	0
T3	5221	4820	0	0
T4	31242	23133	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11521	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	14731	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	2352	0	0
T28	39034	0	0	0
T30	832	48	0	0
T31	0	168	0	0
T32	0	128	0	0
T34	3913	0	0	0
T37	646	0	0	0
T59	79590	0	0	0
T62	496	0	0	0
T89	502	0	0	0
T90	526	0	0	0
T164	0	223	0	0
T184	0	66	0	0
T185	0	108	0	0
T188	0	293	0	0
T189	0	83	0	0
T201	0	43	0	0
T203	0	40	0	0
T204	426	0	0	0
T205	409	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	30	0	0
T28	39034	0	0	0
T30	832	1	0	0
T31	0	1	0	0
T32	0	2	0	0
T34	3913	0	0	0
T37	646	0	0	0
T59	79590	0	0	0
T62	496	0	0	0
T89	502	0	0	0
T90	526	0	0	0
T164	0	2	0	0
T184	0	1	0	0
T185	0	1	0	0
T188	0	1	0	0
T189	0	2	0	0
T201	0	1	0	0
T203	0	1	0	0
T204	426	0	0	0
T205	409	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8592933	0	0
T1	16004	15584	0	0
T2	8919	4895	0	0
T3	5221	4820	0	0
T4	31242	23133	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11521	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	14731	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8595350	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	23163	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	34	0	0
T28	39034	0	0	0
T30	832	1	0	0
T31	0	1	0	0
T32	0	2	0	0
T34	3913	0	0	0
T37	646	0	0	0
T59	79590	0	0	0
T62	496	0	0	0
T89	502	0	0	0
T90	526	0	0	0
T152	0	1	0	0
T184	0	1	0	0
T185	0	1	0	0
T188	0	1	0	0
T189	0	2	0	0
T201	0	1	0	0
T203	0	1	0	0
T204	426	0	0	0
T205	409	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	30	0	0
T28	39034	0	0	0
T30	832	1	0	0
T31	0	1	0	0
T32	0	2	0	0
T34	3913	0	0	0
T37	646	0	0	0
T59	79590	0	0	0
T62	496	0	0	0
T89	502	0	0	0
T90	526	0	0	0
T164	0	2	0	0
T184	0	1	0	0
T185	0	1	0	0
T188	0	1	0	0
T189	0	2	0	0
T201	0	1	0	0
T203	0	1	0	0
T204	426	0	0	0
T205	409	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	30	0	0
T28	39034	0	0	0
T30	832	1	0	0
T31	0	1	0	0
T32	0	2	0	0
T34	3913	0	0	0
T37	646	0	0	0
T59	79590	0	0	0
T62	496	0	0	0
T89	502	0	0	0
T90	526	0	0	0
T164	0	2	0	0
T184	0	1	0	0
T185	0	1	0	0
T188	0	1	0	0
T189	0	2	0	0
T201	0	1	0	0
T203	0	1	0	0
T204	426	0	0	0
T205	409	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	30	0	0
T28	39034	0	0	0
T30	832	1	0	0
T31	0	1	0	0
T32	0	2	0	0
T34	3913	0	0	0
T37	646	0	0	0
T59	79590	0	0	0
T62	496	0	0	0
T89	502	0	0	0
T90	526	0	0	0
T164	0	2	0	0
T184	0	1	0	0
T185	0	1	0	0
T188	0	1	0	0
T189	0	2	0	0
T201	0	1	0	0
T203	0	1	0	0
T204	426	0	0	0
T205	409	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	2309	0	0
T28	39034	0	0	0
T30	832	47	0	0
T31	0	166	0	0
T32	0	125	0	0
T34	3913	0	0	0
T37	646	0	0	0
T59	79590	0	0	0
T62	496	0	0	0
T89	502	0	0	0
T90	526	0	0	0
T164	0	221	0	0
T184	0	65	0	0
T185	0	107	0	0
T188	0	291	0	0
T189	0	80	0	0
T201	0	41	0	0
T203	0	38	0	0
T204	426	0	0	0
T205	409	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	6918	0	0
T1	16004	30	0	0
T2	8919	19	0	0
T3	5221	8	0	0
T4	31242	70	0	0
T5	422	2	0	0
T6	502	2	0	0
T7	13942	15	0	0
T13	443	7	0	0
T14	505	5	0	0
T15	15149	29	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8668790	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	23163	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	17	0	0
T28	39034	0	0	0
T30	832	1	0	0
T32	0	1	0	0
T34	3913	0	0	0
T37	646	0	0	0
T59	79590	0	0	0
T62	496	0	0	0
T89	502	0	0	0
T90	526	0	0	0
T108	0	1	0	0
T164	0	2	0	0
T165	0	1	0	0
T173	0	2	0	0
T184	0	1	0	0
T185	0	1	0	0
T187	0	1	0	0
T189	0	1	0	0
T204	426	0	0	0
T205	409	0	0	0