Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T15,T23
1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T15,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T15,T23

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T15,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T23
1	0	Covered	T1,T15,T23
1	1	Covered	T1,T15,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T15,T23
0	1	Covered	T48,T70,T92
1	0	Covered	T46,T117,T96

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T15,T23
0	1	Covered	T1,T15,T23
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T15,T23
1	-	Covered	T1,T15,T23

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T15,T23
DetectSt	168	Covered	T1,T15,T23
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T1,T15,T23

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T15,T23
DebounceSt->IdleSt	163	Covered	T88,T246,T247
DetectSt->IdleSt	186	Covered	T46,T48,T70
DetectSt->StableSt	191	Covered	T1,T15,T23
IdleSt->DebounceSt	148	Covered	T1,T15,T23
StableSt->IdleSt	206	Covered	T1,T15,T23

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T15,T23
0	1	Covered	T1,T15,T23
0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T15,T23
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T15,T23
IdleSt	0	-	-	-	-	-	-	Covered	T1,T15,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T77,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T15,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T88,T246,T247
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T15,T23
DetectSt	-	-	-	-	1	-	-	Covered	T46,T48,T70
DetectSt	-	-	-	-	0	1	-	Covered	T1,T15,T23
DetectSt	-	-	-	-	0	0	-	Covered	T1,T15,T23
StableSt	-	-	-	-	-	-	1	Covered	T1,T15,T23
StableSt	-	-	-	-	-	-	0	Covered	T1,T15,T23
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9322746	2980	0	0
CntIncr_A	9322746	111572	0	0
CntNoWrap_A	9322746	8663355	0	0
DetectStDropOut_A	9322746	319	0	0
DetectedOut_A	9322746	88000	0	0
DetectedPulseOut_A	9322746	979	0	0
DisabledIdleSt_A	9322746	8190715	0	0
DisabledNoDetection_A	9322746	8192957	0	0
EnterDebounceSt_A	9322746	1521	0	0
EnterDetectSt_A	9322746	1460	0	0
EnterStableSt_A	9322746	979	0	0
PulseIsPulse_A	9322746	979	0	0
StayInStableSt	9322746	86898	0	0
gen_high_event_sva.HighLevelEvent_A	9322746	8668790	0	0
gen_high_level_sva.HighLevelEvent_A	9322746	8668790	0	0
gen_not_sticky_sva.StableStDropOut_A	9322746	856	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	2980	0	0
T1	16004	26	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	0	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	60	0	0
T16	417	0	0	0
T23	0	54	0	0
T45	0	46	0	0
T46	0	48	0	0
T47	0	12	0	0
T48	0	22	0	0
T68	0	22	0	0
T69	0	30	0	0
T70	0	58	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	111572	0	0
T1	16004	949	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	0	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	2490	0	0
T16	417	0	0	0
T23	0	1782	0	0
T45	0	1771	0	0
T46	0	1152	0	0
T47	0	288	0	0
T48	0	478	0	0
T68	0	451	0	0
T69	0	990	0	0
T70	0	1509	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8663355	0	0
T1	16004	15558	0	0
T2	8919	4895	0	0
T3	5221	4820	0	0
T4	31242	23133	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11521	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	14671	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	319	0	0
T31	923	0	0	0
T48	4816	11	0	0
T65	491	0	0	0
T66	491	0	0	0
T68	8642	0	0	0
T70	0	29	0	0
T72	1987	0	0	0
T92	0	17	0	0
T93	0	18	0	0
T94	0	11	0	0
T96	0	4	0	0
T98	0	9	0	0
T99	0	11	0	0
T100	0	27	0	0
T101	0	11	0	0
T248	424	0	0	0
T249	423	0	0	0
T250	31679	0	0	0
T251	489	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	88000	0	0
T1	16004	1043	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	0	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	3233	0	0
T16	417	0	0	0
T23	0	2037	0	0
T45	0	1414	0	0
T47	0	1540	0	0
T68	0	496	0	0
T69	0	1264	0	0
T252	0	7425	0	0
T253	0	2988	0	0
T254	0	1308	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	979	0	0
T1	16004	13	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	0	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	30	0	0
T16	417	0	0	0
T23	0	27	0	0
T45	0	23	0	0
T47	0	6	0	0
T68	0	11	0	0
T69	0	15	0	0
T252	0	26	0	0
T253	0	24	0	0
T254	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8190715	0	0
T1	16004	9403	0	0
T2	8919	4895	0	0
T3	5221	4820	0	0
T4	31242	23133	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11521	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	6103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8192957	0	0
T1	16004	9405	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	23163	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	6103	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	1521	0	0
T1	16004	13	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	0	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	30	0	0
T16	417	0	0	0
T23	0	27	0	0
T45	0	23	0	0
T46	0	24	0	0
T47	0	6	0	0
T48	0	11	0	0
T68	0	11	0	0
T69	0	15	0	0
T70	0	29	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	1460	0	0
T1	16004	13	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	0	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	30	0	0
T16	417	0	0	0
T23	0	27	0	0
T45	0	23	0	0
T46	0	24	0	0
T47	0	6	0	0
T48	0	11	0	0
T68	0	11	0	0
T69	0	15	0	0
T70	0	29	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	979	0	0
T1	16004	13	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	0	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	30	0	0
T16	417	0	0	0
T23	0	27	0	0
T45	0	23	0	0
T47	0	6	0	0
T68	0	11	0	0
T69	0	15	0	0
T252	0	26	0	0
T253	0	24	0	0
T254	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	979	0	0
T1	16004	13	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	0	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	30	0	0
T16	417	0	0	0
T23	0	27	0	0
T45	0	23	0	0
T47	0	6	0	0
T68	0	11	0	0
T69	0	15	0	0
T252	0	26	0	0
T253	0	24	0	0
T254	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	86898	0	0
T1	16004	1029	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	0	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	3201	0	0
T16	417	0	0	0
T23	0	2010	0	0
T45	0	1391	0	0
T47	0	1531	0	0
T68	0	484	0	0
T69	0	1248	0	0
T252	0	7393	0	0
T253	0	2959	0	0
T254	0	1305	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8668790	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	23163	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8668790	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	23163	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	856	0	0
T1	16004	12	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	0	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	28	0	0
T16	417	0	0	0
T23	0	27	0	0
T45	0	23	0	0
T47	0	3	0	0
T68	0	10	0	0
T69	0	14	0	0
T252	0	20	0	0
T253	0	19	0	0
T254	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T2,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T1,T2,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T2,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T91,T95,T97
1	0	Covered	T77,T78

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T77,T78

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T2,T3,T4

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T3
DetectSt	168	Covered	T1,T2,T3
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T3
DebounceSt->IdleSt	163	Covered	T4,T11,T34
DetectSt->IdleSt	186	Covered	T91,T95,T97
DetectSt->StableSt	191	Covered	T1,T2,T3
IdleSt->DebounceSt	148	Covered	T1,T2,T3
StableSt->IdleSt	206	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T77,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T11,T34
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	1	-	-	Covered	T91,T95,T97
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	1	Covered	T2,T3,T4
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9322746	1029	0	0
CntIncr_A	9322746	52924	0	0
CntNoWrap_A	9322746	8665306	0	0
DetectStDropOut_A	9322746	36	0	0
DetectedOut_A	9322746	19577	0	0
DetectedPulseOut_A	9322746	438	0	0
DisabledIdleSt_A	9322746	8256146	0	0
DisabledNoDetection_A	9322746	8257772	0	0
EnterDebounceSt_A	9322746	552	0	0
EnterDetectSt_A	9322746	479	0	0
EnterStableSt_A	9322746	438	0	0
PulseIsPulse_A	9322746	438	0	0
StayInStableSt	9322746	19122	0	0
gen_high_level_sva.HighLevelEvent_A	9322746	8668790	0	0
gen_not_sticky_sva.StableStDropOut_A	9322746	418	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	1029	0	0
T1	16004	2	0	0
T2	8919	2	0	0
T3	5221	4	0	0
T4	31242	9	0	0
T6	502	0	0	0
T7	13942	4	0	0
T11	0	3	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	0	12	0	0
T23	0	4	0	0
T27	0	14	0	0
T43	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	52924	0	0
T1	16004	62	0	0
T2	8919	144	0	0
T3	5221	84	0	0
T4	31242	324	0	0
T6	502	0	0	0
T7	13942	182	0	0
T11	0	178	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	0	1032	0	0
T23	0	164	0	0
T27	0	903	0	0
T43	0	25	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8665306	0	0
T1	16004	15582	0	0
T2	8919	4893	0	0
T3	5221	4816	0	0
T4	31242	23124	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11517	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	14731	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	36	0	0
T70	5219	0	0	0
T91	20347	7	0	0
T95	0	3	0	0
T97	0	3	0	0
T102	0	1	0	0
T103	0	4	0	0
T104	0	1	0	0
T106	0	2	0	0
T107	0	4	0	0
T108	0	1	0	0
T109	0	4	0	0
T110	723	0	0	0
T111	436	0	0	0
T112	502	0	0	0
T113	428	0	0	0
T114	1431	0	0	0
T115	506	0	0	0
T116	508	0	0	0
T117	7202	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	19577	0	0
T1	16004	72	0	0
T2	8919	17	0	0
T3	5221	79	0	0
T4	31242	86	0	0
T6	502	0	0	0
T7	13942	156	0	0
T11	0	6	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	0	164	0	0
T23	0	98	0	0
T27	0	129	0	0
T43	0	4	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	438	0	0
T1	16004	1	0	0
T2	8919	1	0	0
T3	5221	2	0	0
T4	31242	4	0	0
T6	502	0	0	0
T7	13942	2	0	0
T11	0	1	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	0	6	0	0
T23	0	2	0	0
T27	0	7	0	0
T43	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8256146	0	0
T1	16004	14542	0	0
T2	8919	4443	0	0
T3	5221	2015	0	0
T4	31242	17903	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	6961	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	11500	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8257772	0	0
T1	16004	14545	0	0
T2	8919	4453	0	0
T3	5221	2015	0	0
T4	31242	17925	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	6965	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	11501	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	552	0	0
T1	16004	1	0	0
T2	8919	1	0	0
T3	5221	2	0	0
T4	31242	5	0	0
T6	502	0	0	0
T7	13942	2	0	0
T11	0	2	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	0	6	0	0
T23	0	2	0	0
T27	0	7	0	0
T43	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	479	0	0
T1	16004	1	0	0
T2	8919	1	0	0
T3	5221	2	0	0
T4	31242	4	0	0
T6	502	0	0	0
T7	13942	2	0	0
T11	0	1	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	0	6	0	0
T23	0	2	0	0
T27	0	7	0	0
T43	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	438	0	0
T1	16004	1	0	0
T2	8919	1	0	0
T3	5221	2	0	0
T4	31242	4	0	0
T6	502	0	0	0
T7	13942	2	0	0
T11	0	1	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	0	6	0	0
T23	0	2	0	0
T27	0	7	0	0
T43	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	438	0	0
T1	16004	1	0	0
T2	8919	1	0	0
T3	5221	2	0	0
T4	31242	4	0	0
T6	502	0	0	0
T7	13942	2	0	0
T11	0	1	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	0	6	0	0
T23	0	2	0	0
T27	0	7	0	0
T43	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	19122	0	0
T1	16004	70	0	0
T2	8919	16	0	0
T3	5221	77	0	0
T4	31242	82	0	0
T6	502	0	0	0
T7	13942	154	0	0
T11	0	5	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	0	158	0	0
T23	0	96	0	0
T27	0	122	0	0
T43	0	3	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8668790	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	23163	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	418	0	0
T2	8919	1	0	0
T3	5221	2	0	0
T4	31242	4	0	0
T7	13942	2	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T11	0	1	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	0	6	0	0
T23	0	2	0	0
T27	0	7	0	0
T43	0	1	0	0
T52	522	0	0	0
T127	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T15,T23
1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T15,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T15,T23

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T15,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T23
1	0	Covered	T1,T15,T23
1	1	Covered	T1,T15,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T15,T23
0	1	Covered	T47,T48,T70
1	0	Covered	T45,T47,T96

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T15,T23
0	1	Covered	T1,T15,T23
1	0	Covered	T45,T81,T255

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T15,T23
1	-	Covered	T1,T15,T23

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T15,T23
DetectSt	168	Covered	T1,T15,T23
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T1,T15,T23

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T15,T23
DebounceSt->IdleSt	163	Covered	T88,T246,T247
DetectSt->IdleSt	186	Covered	T45,T47,T48
DetectSt->StableSt	191	Covered	T1,T15,T23
IdleSt->DebounceSt	148	Covered	T1,T15,T23
StableSt->IdleSt	206	Covered	T1,T15,T23

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T15,T23
0	1	Covered	T1,T15,T23
0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T15,T23
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T15,T23
IdleSt	0	-	-	-	-	-	-	Covered	T1,T15,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T77,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T15,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T88,T246,T247
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T15,T23
DetectSt	-	-	-	-	1	-	-	Covered	T45,T47,T48
DetectSt	-	-	-	-	0	1	-	Covered	T1,T15,T23
DetectSt	-	-	-	-	0	0	-	Covered	T1,T15,T23
StableSt	-	-	-	-	-	-	1	Covered	T1,T15,T23
StableSt	-	-	-	-	-	-	0	Covered	T1,T15,T23
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9322746	2932	0	0
CntIncr_A	9322746	107402	0	0
CntNoWrap_A	9322746	8663403	0	0
DetectStDropOut_A	9322746	296	0	0
DetectedOut_A	9322746	89188	0	0
DetectedPulseOut_A	9322746	1016	0	0
DisabledIdleSt_A	9322746	8192977	0	0
DisabledNoDetection_A	9322746	8195236	0	0
EnterDebounceSt_A	9322746	1499	0	0
EnterDetectSt_A	9322746	1434	0	0
EnterStableSt_A	9322746	1016	0	0
PulseIsPulse_A	9322746	1016	0	0
StayInStableSt	9322746	88066	0	0
gen_high_event_sva.HighLevelEvent_A	9322746	8668790	0	0
gen_high_level_sva.HighLevelEvent_A	9322746	8668790	0	0
gen_not_sticky_sva.StableStDropOut_A	9322746	884	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	2932	0	0
T1	16004	54	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	0	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	28	0	0
T16	417	0	0	0
T23	0	44	0	0
T45	0	24	0	0
T46	0	12	0	0
T47	0	20	0	0
T48	0	30	0	0
T68	0	64	0	0
T69	0	12	0	0
T70	0	50	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	107402	0	0
T1	16004	2376	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	0	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	952	0	0
T16	417	0	0	0
T23	0	1584	0	0
T45	0	1064	0	0
T46	0	240	0	0
T47	0	579	0	0
T48	0	654	0	0
T68	0	1472	0	0
T69	0	318	0	0
T70	0	1301	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8663403	0	0
T1	16004	15530	0	0
T2	8919	4895	0	0
T3	5221	4820	0	0
T4	31242	23133	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11521	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	14703	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	296	0	0
T47	13072	4	0	0
T48	4816	15	0	0
T64	494	0	0	0
T70	0	25	0	0
T71	999	0	0	0
T92	0	28	0	0
T93	0	14	0	0
T94	0	11	0	0
T96	0	19	0	0
T99	0	5	0	0
T100	0	7	0	0
T192	523	0	0	0
T193	1396	0	0	0
T256	0	2	0	0
T257	522	0	0	0
T258	442	0	0	0
T259	522	0	0	0
T260	440	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	89188	0	0
T1	16004	1720	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	0	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	1093	0	0
T16	417	0	0	0
T23	0	440	0	0
T45	0	1	0	0
T46	0	683	0	0
T68	0	1221	0	0
T69	0	492	0	0
T88	0	731	0	0
T117	0	1695	0	0
T252	0	1988	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	1016	0	0
T1	16004	27	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	0	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	14	0	0
T16	417	0	0	0
T23	0	22	0	0
T45	0	1	0	0
T46	0	6	0	0
T68	0	32	0	0
T69	0	6	0	0
T88	0	4	0	0
T117	0	23	0	0
T252	0	10	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8192977	0	0
T1	16004	8796	0	0
T2	8919	4895	0	0
T3	5221	4820	0	0
T4	31242	23133	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11521	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	7629	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8195236	0	0
T1	16004	8797	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	23163	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	7630	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	1499	0	0
T1	16004	27	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	0	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	14	0	0
T16	417	0	0	0
T23	0	22	0	0
T45	0	12	0	0
T46	0	6	0	0
T47	0	10	0	0
T48	0	15	0	0
T68	0	32	0	0
T69	0	6	0	0
T70	0	25	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	1434	0	0
T1	16004	27	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	0	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	14	0	0
T16	417	0	0	0
T23	0	22	0	0
T45	0	12	0	0
T46	0	6	0	0
T47	0	10	0	0
T48	0	15	0	0
T68	0	32	0	0
T69	0	6	0	0
T70	0	25	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	1016	0	0
T1	16004	27	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	0	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	14	0	0
T16	417	0	0	0
T23	0	22	0	0
T45	0	1	0	0
T46	0	6	0	0
T68	0	32	0	0
T69	0	6	0	0
T88	0	4	0	0
T117	0	23	0	0
T252	0	10	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	1016	0	0
T1	16004	27	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	0	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	14	0	0
T16	417	0	0	0
T23	0	22	0	0
T45	0	1	0	0
T46	0	6	0	0
T68	0	32	0	0
T69	0	6	0	0
T88	0	4	0	0
T117	0	23	0	0
T252	0	10	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	88066	0	0
T1	16004	1691	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	0	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	1078	0	0
T16	417	0	0	0
T23	0	418	0	0
T46	0	674	0	0
T68	0	1189	0	0
T69	0	485	0	0
T88	0	727	0	0
T117	0	1672	0	0
T252	0	1976	0	0
T253	0	1626	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8668790	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	23163	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8668790	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	23163	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	884	0	0
T1	16004	25	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	0	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	13	0	0
T16	417	0	0	0
T23	0	22	0	0
T46	0	3	0	0
T68	0	32	0	0
T69	0	5	0	0
T88	0	4	0	0
T117	0	23	0	0
T252	0	8	0	0
T253	0	11	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T2,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T1,T2,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T2,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T29,T250
1	0	Covered	T77,T78

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T77

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T3
DetectSt	168	Covered	T1,T2,T3
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T3
DebounceSt->IdleSt	163	Covered	T1,T7,T29
DetectSt->IdleSt	186	Covered	T11,T29,T250
DetectSt->StableSt	191	Covered	T1,T2,T3
IdleSt->DebounceSt	148	Covered	T1,T2,T3
StableSt->IdleSt	206	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T77,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T7,T29
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	1	-	-	Covered	T11,T29,T250
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9322746	855	0	0
CntIncr_A	9322746	46777	0	0
CntNoWrap_A	9322746	8665480	0	0
DetectStDropOut_A	9322746	94	0	0
DetectedOut_A	9322746	15534	0	0
DetectedPulseOut_A	9322746	311	0	0
DisabledIdleSt_A	9322746	8247828	0	0
DisabledNoDetection_A	9322746	8249499	0	0
EnterDebounceSt_A	9322746	447	0	0
EnterDetectSt_A	9322746	408	0	0
EnterStableSt_A	9322746	311	0	0
PulseIsPulse_A	9322746	311	0	0
StayInStableSt	9322746	15201	0	0
gen_high_level_sva.HighLevelEvent_A	9322746	8668790	0	0
gen_not_sticky_sva.StableStDropOut_A	9322746	287	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	855	0	0
T1	16004	7	0	0
T2	8919	2	0	0
T3	5221	4	0	0
T4	31242	12	0	0
T6	502	0	0	0
T7	13942	5	0	0
T11	0	2	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	2	0	0
T16	417	0	0	0
T27	0	14	0	0
T28	0	10	0	0
T127	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	46777	0	0
T1	16004	252	0	0
T2	8919	124	0	0
T3	5221	130	0	0
T4	31242	628	0	0
T6	502	0	0	0
T7	13942	397	0	0
T11	0	164	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	77	0	0
T16	417	0	0	0
T27	0	665	0	0
T28	0	715	0	0
T127	0	175	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8665480	0	0
T1	16004	15577	0	0
T2	8919	4893	0	0
T3	5221	4816	0	0
T4	31242	23121	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11516	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	14729	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	94	0	0
T11	15667	1	0	0
T12	1587	0	0	0
T22	489	0	0	0
T23	8521	0	0	0
T27	40810	0	0	0
T29	0	2	0	0
T40	0	1	0	0
T42	1605	0	0	0
T56	507	0	0	0
T57	1668	0	0	0
T67	502	0	0	0
T179	0	7	0	0
T242	0	2	0	0
T250	0	6	0	0
T261	0	8	0	0
T262	0	6	0	0
T263	0	9	0	0
T264	0	5	0	0
T265	417	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	15534	0	0
T1	16004	197	0	0
T2	8919	38	0	0
T3	5221	32	0	0
T4	31242	366	0	0
T6	502	0	0	0
T7	13942	22	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	53	0	0
T16	417	0	0	0
T27	0	368	0	0
T28	0	135	0	0
T29	0	64	0	0
T127	0	6	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	311	0	0
T1	16004	3	0	0
T2	8919	1	0	0
T3	5221	2	0	0
T4	31242	6	0	0
T6	502	0	0	0
T7	13942	2	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	1	0	0
T16	417	0	0	0
T27	0	7	0	0
T28	0	5	0	0
T29	0	2	0	0
T127	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8247828	0	0
T1	16004	13866	0	0
T2	8919	4443	0	0
T3	5221	2015	0	0
T4	31242	17943	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	6961	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	13639	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8249499	0	0
T1	16004	13868	0	0
T2	8919	4453	0	0
T3	5221	2015	0	0
T4	31242	17966	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	6965	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	13641	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	447	0	0
T1	16004	4	0	0
T2	8919	1	0	0
T3	5221	2	0	0
T4	31242	6	0	0
T6	502	0	0	0
T7	13942	3	0	0
T11	0	1	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	1	0	0
T16	417	0	0	0
T27	0	7	0	0
T28	0	5	0	0
T127	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	408	0	0
T1	16004	3	0	0
T2	8919	1	0	0
T3	5221	2	0	0
T4	31242	6	0	0
T6	502	0	0	0
T7	13942	2	0	0
T11	0	1	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	1	0	0
T16	417	0	0	0
T27	0	7	0	0
T28	0	5	0	0
T127	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	311	0	0
T1	16004	3	0	0
T2	8919	1	0	0
T3	5221	2	0	0
T4	31242	6	0	0
T6	502	0	0	0
T7	13942	2	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	1	0	0
T16	417	0	0	0
T27	0	7	0	0
T28	0	5	0	0
T29	0	2	0	0
T127	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	311	0	0
T1	16004	3	0	0
T2	8919	1	0	0
T3	5221	2	0	0
T4	31242	6	0	0
T6	502	0	0	0
T7	13942	2	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	1	0	0
T16	417	0	0	0
T27	0	7	0	0
T28	0	5	0	0
T29	0	2	0	0
T127	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	15201	0	0
T1	16004	194	0	0
T2	8919	37	0	0
T3	5221	30	0	0
T4	31242	360	0	0
T6	502	0	0	0
T7	13942	20	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	51	0	0
T16	417	0	0	0
T27	0	361	0	0
T28	0	130	0	0
T29	0	62	0	0
T127	0	5	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8668790	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	23163	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	287	0	0
T1	16004	3	0	0
T2	8919	1	0	0
T3	5221	2	0	0
T4	31242	6	0	0
T6	502	0	0	0
T7	13942	2	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T27	0	7	0	0
T28	0	5	0	0
T29	0	2	0	0
T46	0	3	0	0
T127	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T15,T23
1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T15,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T15,T23

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T15,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T23
1	0	Covered	T1,T15,T23
1	1	Covered	T1,T15,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T15,T23
0	1	Covered	T47,T48,T70
1	0	Covered	T45,T47,T68

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T15,T23
0	1	Covered	T1,T15,T23
1	0	Covered	T82,T266,T78

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T15,T23
1	-	Covered	T1,T15,T23

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T15,T23
DetectSt	168	Covered	T1,T15,T23
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T1,T15,T23

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T15,T23
DebounceSt->IdleSt	163	Covered	T88,T246,T247
DetectSt->IdleSt	186	Covered	T45,T47,T48
DetectSt->StableSt	191	Covered	T1,T15,T23
IdleSt->DebounceSt	148	Covered	T1,T15,T23
StableSt->IdleSt	206	Covered	T1,T15,T23

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T15,T23
0	1	Covered	T1,T15,T23
0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T15,T23
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T15,T23
IdleSt	0	-	-	-	-	-	-	Covered	T1,T15,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T77,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T15,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T88,T246,T247
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T15,T23
DetectSt	-	-	-	-	1	-	-	Covered	T45,T47,T48
DetectSt	-	-	-	-	0	1	-	Covered	T1,T15,T23
DetectSt	-	-	-	-	0	0	-	Covered	T1,T15,T23
StableSt	-	-	-	-	-	-	1	Covered	T1,T15,T23
StableSt	-	-	-	-	-	-	0	Covered	T1,T15,T23
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9322746	2649	0	0
CntIncr_A	9322746	96209	0	0
CntNoWrap_A	9322746	8663686	0	0
DetectStDropOut_A	9322746	276	0	0
DetectedOut_A	9322746	63596	0	0
DetectedPulseOut_A	9322746	831	0	0
DisabledIdleSt_A	9322746	8209641	0	0
DisabledNoDetection_A	9322746	8211920	0	0
EnterDebounceSt_A	9322746	1353	0	0
EnterDetectSt_A	9322746	1297	0	0
EnterStableSt_A	9322746	831	0	0
PulseIsPulse_A	9322746	831	0	0
StayInStableSt	9322746	62679	0	0
gen_high_event_sva.HighLevelEvent_A	9322746	8668790	0	0
gen_high_level_sva.HighLevelEvent_A	9322746	8668790	0	0
gen_not_sticky_sva.StableStDropOut_A	9322746	713	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	2649	0	0
T1	16004	12	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	0	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	52	0	0
T16	417	0	0	0
T23	0	44	0	0
T45	0	18	0	0
T46	0	26	0	0
T47	0	24	0	0
T48	0	28	0	0
T68	0	12	0	0
T69	0	28	0	0
T70	0	50	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	96209	0	0
T1	16004	330	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	0	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	2002	0	0
T16	417	0	0	0
T23	0	1518	0	0
T45	0	799	0	0
T46	0	533	0	0
T47	0	695	0	0
T48	0	608	0	0
T68	0	303	0	0
T69	0	630	0	0
T70	0	1301	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8663686	0	0
T1	16004	15572	0	0
T2	8919	4895	0	0
T3	5221	4820	0	0
T4	31242	23133	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11521	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	14679	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	276	0	0
T47	13072	7	0	0
T48	4816	14	0	0
T64	494	0	0	0
T70	0	25	0	0
T71	999	0	0	0
T92	0	13	0	0
T93	0	12	0	0
T94	0	23	0	0
T96	0	6	0	0
T100	0	25	0	0
T192	523	0	0	0
T193	1396	0	0	0
T228	0	3	0	0
T247	0	1	0	0
T257	522	0	0	0
T258	442	0	0	0
T259	522	0	0	0
T260	440	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	63596	0	0
T1	16004	473	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	0	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	1965	0	0
T16	417	0	0	0
T23	0	506	0	0
T46	0	867	0	0
T69	0	1814	0	0
T81	0	111	0	0
T88	0	1475	0	0
T117	0	16	0	0
T253	0	568	0	0
T254	0	1869	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	831	0	0
T1	16004	6	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	0	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	26	0	0
T16	417	0	0	0
T23	0	22	0	0
T46	0	13	0	0
T69	0	14	0	0
T81	0	3	0	0
T88	0	9	0	0
T117	0	5	0	0
T253	0	6	0	0
T254	0	10	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8209641	0	0
T1	16004	9857	0	0
T2	8919	4895	0	0
T3	5221	4820	0	0
T4	31242	23133	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11521	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	7331	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8211920	0	0
T1	16004	9859	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	23163	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	7331	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	1353	0	0
T1	16004	6	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	0	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	26	0	0
T16	417	0	0	0
T23	0	22	0	0
T45	0	9	0	0
T46	0	13	0	0
T47	0	12	0	0
T48	0	14	0	0
T68	0	6	0	0
T69	0	14	0	0
T70	0	25	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	1297	0	0
T1	16004	6	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	0	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	26	0	0
T16	417	0	0	0
T23	0	22	0	0
T45	0	9	0	0
T46	0	13	0	0
T47	0	12	0	0
T48	0	14	0	0
T68	0	6	0	0
T69	0	14	0	0
T70	0	25	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	831	0	0
T1	16004	6	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	0	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	26	0	0
T16	417	0	0	0
T23	0	22	0	0
T46	0	13	0	0
T69	0	14	0	0
T81	0	3	0	0
T88	0	9	0	0
T117	0	5	0	0
T253	0	6	0	0
T254	0	10	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	831	0	0
T1	16004	6	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	0	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	26	0	0
T16	417	0	0	0
T23	0	22	0	0
T46	0	13	0	0
T69	0	14	0	0
T81	0	3	0	0
T88	0	9	0	0
T117	0	5	0	0
T253	0	6	0	0
T254	0	10	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	62679	0	0
T1	16004	466	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	0	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	1937	0	0
T16	417	0	0	0
T23	0	484	0	0
T46	0	850	0	0
T69	0	1796	0	0
T81	0	108	0	0
T88	0	1466	0	0
T117	0	11	0	0
T253	0	561	0	0
T254	0	1858	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8668790	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	23163	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8668790	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	23163	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	713	0	0
T1	16004	5	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	0	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	24	0	0
T16	417	0	0	0
T23	0	22	0	0
T46	0	9	0	0
T69	0	10	0	0
T81	0	3	0	0
T88	0	9	0	0
T117	0	5	0	0
T253	0	5	0	0
T254	0	9	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T3,T4

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T1,T3,T4

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T3,T4

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T3,T4

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T3,T4,T127
1	0	Covered	T77,T78

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T15
0	1	Covered	T1,T4,T7
1	0	Covered	T77,T78

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T4,T15
1	-	Covered	T1,T4,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T4
DetectSt	168	Covered	T1,T3,T4
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T1,T4,T15

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T4
DebounceSt->IdleSt	163	Covered	T29,T250,T49
DetectSt->IdleSt	186	Covered	T3,T4,T127
DetectSt->StableSt	191	Covered	T1,T4,T15
IdleSt->DebounceSt	148	Covered	T1,T3,T4
StableSt->IdleSt	206	Covered	T1,T4,T15

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T77,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T4
DebounceSt	-	0	1	0	-	-	-	Covered	T29,T250,T49
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T4
DetectSt	-	-	-	-	1	-	-	Covered	T3,T4,T127
DetectSt	-	-	-	-	0	1	-	Covered	T1,T4,T15
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T4
StableSt	-	-	-	-	-	-	1	Covered	T1,T4,T7
StableSt	-	-	-	-	-	-	0	Covered	T1,T4,T15
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9322746	873	0	0
CntIncr_A	9322746	50921	0	0
CntNoWrap_A	9322746	8665462	0	0
DetectStDropOut_A	9322746	56	0	0
DetectedOut_A	9322746	15270	0	0
DetectedPulseOut_A	9322746	352	0	0
DisabledIdleSt_A	9322746	8285857	0	0
DisabledNoDetection_A	9322746	8287586	0	0
EnterDebounceSt_A	9322746	462	0	0
EnterDetectSt_A	9322746	411	0	0
EnterStableSt_A	9322746	352	0	0
PulseIsPulse_A	9322746	352	0	0
StayInStableSt	9322746	14885	0	0
gen_high_level_sva.HighLevelEvent_A	9322746	8668790	0	0
gen_not_sticky_sva.StableStDropOut_A	9322746	315	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	873	0	0
T1	16004	2	0	0
T2	8919	0	0	0
T3	5221	4	0	0
T4	31242	10	0	0
T6	502	0	0	0
T7	13942	6	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	4	0	0
T16	417	0	0	0
T27	0	16	0	0
T28	0	6	0	0
T29	0	12	0	0
T46	0	2	0	0
T127	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	50921	0	0
T1	16004	89	0	0
T2	8919	0	0	0
T3	5221	162	0	0
T4	31242	585	0	0
T6	502	0	0	0
T7	13942	438	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	110	0	0
T16	417	0	0	0
T27	0	976	0	0
T28	0	387	0	0
T29	0	684	0	0
T46	0	55	0	0
T127	0	542	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8665462	0	0
T1	16004	15582	0	0
T2	8919	4895	0	0
T3	5221	4816	0	0
T4	31242	23123	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11515	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	14727	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	56	0	0
T3	5221	2	0	0
T4	31242	4	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T52	522	0	0	0
T127	0	3	0	0
T198	0	3	0	0
T208	0	1	0	0
T242	0	7	0	0
T264	0	1	0	0
T267	0	2	0	0
T268	0	1	0	0
T269	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	15270	0	0
T1	16004	47	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	4	0	0
T6	502	0	0	0
T7	13942	69	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	151	0	0
T16	417	0	0	0
T27	0	203	0	0
T28	0	122	0	0
T29	0	156	0	0
T46	0	62	0	0
T49	0	1017	0	0
T250	0	174	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	352	0	0
T1	16004	1	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	1	0	0
T6	502	0	0	0
T7	13942	3	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	2	0	0
T16	417	0	0	0
T27	0	8	0	0
T28	0	3	0	0
T29	0	5	0	0
T46	0	1	0	0
T49	0	11	0	0
T250	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8285857	0	0
T1	16004	15112	0	0
T2	8919	4443	0	0
T3	5221	2015	0	0
T4	31242	17943	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	6961	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	12768	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8287586	0	0
T1	16004	15115	0	0
T2	8919	4453	0	0
T3	5221	2015	0	0
T4	31242	17966	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	6965	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	12769	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	462	0	0
T1	16004	1	0	0
T2	8919	0	0	0
T3	5221	2	0	0
T4	31242	5	0	0
T6	502	0	0	0
T7	13942	3	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	2	0	0
T16	417	0	0	0
T27	0	8	0	0
T28	0	3	0	0
T29	0	7	0	0
T46	0	1	0	0
T127	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	411	0	0
T1	16004	1	0	0
T2	8919	0	0	0
T3	5221	2	0	0
T4	31242	5	0	0
T6	502	0	0	0
T7	13942	3	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	2	0	0
T16	417	0	0	0
T27	0	8	0	0
T28	0	3	0	0
T29	0	5	0	0
T46	0	1	0	0
T127	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	352	0	0
T1	16004	1	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	1	0	0
T6	502	0	0	0
T7	13942	3	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	2	0	0
T16	417	0	0	0
T27	0	8	0	0
T28	0	3	0	0
T29	0	5	0	0
T46	0	1	0	0
T49	0	11	0	0
T250	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	352	0	0
T1	16004	1	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	1	0	0
T6	502	0	0	0
T7	13942	3	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	2	0	0
T16	417	0	0	0
T27	0	8	0	0
T28	0	3	0	0
T29	0	5	0	0
T46	0	1	0	0
T49	0	11	0	0
T250	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	14885	0	0
T1	16004	46	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	3	0	0
T6	502	0	0	0
T7	13942	66	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	147	0	0
T16	417	0	0	0
T27	0	195	0	0
T28	0	119	0	0
T29	0	151	0	0
T46	0	61	0	0
T49	0	1006	0	0
T250	0	171	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8668790	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	23163	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	315	0	0
T1	16004	1	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	1	0	0
T6	502	0	0	0
T7	13942	3	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T27	0	8	0	0
T28	0	3	0	0
T29	0	5	0	0
T46	0	1	0	0
T49	0	11	0	0
T69	0	1	0	0
T250	0	3	0	0