Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T15,T23
1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T15,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T15,T23

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T15,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T23
1	0	Covered	T1,T15,T23
1	1	Covered	T1,T15,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T15,T23
0	1	Covered	T47,T48,T70
1	0	Covered	T47,T117,T270

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T15,T23
0	1	Covered	T1,T15,T23
1	0	Covered	T271,T272

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T15,T23
1	-	Covered	T1,T15,T23

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T15,T23
DetectSt	168	Covered	T1,T15,T23
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T1,T15,T23

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T15,T23
DebounceSt->IdleSt	163	Covered	T88,T246,T247
DetectSt->IdleSt	186	Covered	T47,T48,T70
DetectSt->StableSt	191	Covered	T1,T15,T23
IdleSt->DebounceSt	148	Covered	T1,T15,T23
StableSt->IdleSt	206	Covered	T1,T15,T23

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T15,T23
0	1	Covered	T1,T15,T23
0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T15,T23
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T15,T23
IdleSt	0	-	-	-	-	-	-	Covered	T1,T15,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T77,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T15,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T88,T246,T247
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T15,T23
DetectSt	-	-	-	-	1	-	-	Covered	T47,T48,T70
DetectSt	-	-	-	-	0	1	-	Covered	T1,T15,T23
DetectSt	-	-	-	-	0	0	-	Covered	T1,T15,T23
StableSt	-	-	-	-	-	-	1	Covered	T1,T15,T23
StableSt	-	-	-	-	-	-	0	Covered	T1,T15,T23
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9322746	2821	0	0
CntIncr_A	9322746	102141	0	0
CntNoWrap_A	9322746	8663514	0	0
DetectStDropOut_A	9322746	320	0	0
DetectedOut_A	9322746	75009	0	0
DetectedPulseOut_A	9322746	922	0	0
DisabledIdleSt_A	9322746	8199704	0	0
DisabledNoDetection_A	9322746	8201955	0	0
EnterDebounceSt_A	9322746	1452	0	0
EnterDetectSt_A	9322746	1372	0	0
EnterStableSt_A	9322746	922	0	0
PulseIsPulse_A	9322746	922	0	0
StayInStableSt	9322746	73972	0	0
gen_high_event_sva.HighLevelEvent_A	9322746	8668790	0	0
gen_high_level_sva.HighLevelEvent_A	9322746	8668790	0	0
gen_not_sticky_sva.StableStDropOut_A	9322746	801	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	2821	0	0
T1	16004	42	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	0	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	56	0	0
T16	417	0	0	0
T23	0	28	0	0
T45	0	30	0	0
T46	0	48	0	0
T47	0	62	0	0
T48	0	62	0	0
T68	0	26	0	0
T69	0	6	0	0
T70	0	22	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	102141	0	0
T1	16004	1155	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	0	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	2520	0	0
T16	417	0	0	0
T23	0	714	0	0
T45	0	915	0	0
T46	0	864	0	0
T47	0	1795	0	0
T48	0	1363	0	0
T68	0	598	0	0
T69	0	228	0	0
T70	0	565	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8663514	0	0
T1	16004	15542	0	0
T2	8919	4895	0	0
T3	5221	4820	0	0
T4	31242	23133	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11521	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	14675	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	320	0	0
T47	13072	26	0	0
T48	4816	31	0	0
T64	494	0	0	0
T70	0	11	0	0
T71	999	0	0	0
T92	0	14	0	0
T93	0	33	0	0
T94	0	13	0	0
T99	0	7	0	0
T100	0	20	0	0
T117	0	8	0	0
T192	523	0	0	0
T193	1396	0	0	0
T257	522	0	0	0
T258	442	0	0	0
T259	522	0	0	0
T260	440	0	0	0
T273	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	75009	0	0
T1	16004	2416	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	0	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	1320	0	0
T16	417	0	0	0
T23	0	568	0	0
T45	0	700	0	0
T46	0	1970	0	0
T68	0	84	0	0
T69	0	32	0	0
T88	0	693	0	0
T252	0	2037	0	0
T253	0	2203	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	922	0	0
T1	16004	21	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	0	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	28	0	0
T16	417	0	0	0
T23	0	14	0	0
T45	0	15	0	0
T46	0	24	0	0
T68	0	13	0	0
T69	0	3	0	0
T88	0	4	0	0
T252	0	10	0	0
T253	0	30	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8199704	0	0
T1	16004	8692	0	0
T2	8919	4895	0	0
T3	5221	4820	0	0
T4	31242	23133	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11521	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	7719	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8201955	0	0
T1	16004	8693	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	23163	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	7721	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	1452	0	0
T1	16004	21	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	0	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	28	0	0
T16	417	0	0	0
T23	0	14	0	0
T45	0	15	0	0
T46	0	24	0	0
T47	0	31	0	0
T48	0	31	0	0
T68	0	13	0	0
T69	0	3	0	0
T70	0	11	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	1372	0	0
T1	16004	21	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	0	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	28	0	0
T16	417	0	0	0
T23	0	14	0	0
T45	0	15	0	0
T46	0	24	0	0
T47	0	31	0	0
T48	0	31	0	0
T68	0	13	0	0
T69	0	3	0	0
T70	0	11	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	922	0	0
T1	16004	21	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	0	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	28	0	0
T16	417	0	0	0
T23	0	14	0	0
T45	0	15	0	0
T46	0	24	0	0
T68	0	13	0	0
T69	0	3	0	0
T88	0	4	0	0
T252	0	10	0	0
T253	0	30	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	922	0	0
T1	16004	21	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	0	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	28	0	0
T16	417	0	0	0
T23	0	14	0	0
T45	0	15	0	0
T46	0	24	0	0
T68	0	13	0	0
T69	0	3	0	0
T88	0	4	0	0
T252	0	10	0	0
T253	0	30	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	73972	0	0
T1	16004	2393	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	0	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	1292	0	0
T16	417	0	0	0
T23	0	554	0	0
T45	0	685	0	0
T46	0	1943	0	0
T68	0	71	0	0
T69	0	29	0	0
T88	0	689	0	0
T252	0	2026	0	0
T253	0	2165	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8668790	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	23163	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8668790	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	23163	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	801	0	0
T1	16004	19	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	0	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	28	0	0
T16	417	0	0	0
T23	0	14	0	0
T45	0	15	0	0
T46	0	21	0	0
T68	0	13	0	0
T69	0	3	0	0
T88	0	4	0	0
T252	0	9	0	0
T253	0	22	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T3,T4

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T1,T3,T4

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T3,T4

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T3,T4

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T3,T127,T91
1	0	Covered	T77,T78

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T21
0	1	Covered	T1,T4,T21
1	0	Covered	T77

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T4,T21
1	-	Covered	T1,T4,T21

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T4
DetectSt	168	Covered	T1,T3,T4
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T1,T4,T21

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T4
DebounceSt->IdleSt	163	Covered	T3,T28,T29
DetectSt->IdleSt	186	Covered	T3,T127,T91
DetectSt->StableSt	191	Covered	T1,T4,T21
IdleSt->DebounceSt	148	Covered	T1,T3,T4
StableSt->IdleSt	206	Covered	T1,T4,T21

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T77,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T4
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T28,T29
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T4
DetectSt	-	-	-	-	1	-	-	Covered	T3,T127,T91
DetectSt	-	-	-	-	0	1	-	Covered	T1,T4,T21
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T4
StableSt	-	-	-	-	-	-	1	Covered	T1,T4,T21
StableSt	-	-	-	-	-	-	0	Covered	T1,T4,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9322746	992	0	0
CntIncr_A	9322746	50720	0	0
CntNoWrap_A	9322746	8665343	0	0
DetectStDropOut_A	9322746	74	0	0
DetectedOut_A	9322746	18073	0	0
DetectedPulseOut_A	9322746	391	0	0
DisabledIdleSt_A	9322746	8272035	0	0
DisabledNoDetection_A	9322746	8273708	0	0
EnterDebounceSt_A	9322746	523	0	0
EnterDetectSt_A	9322746	469	0	0
EnterStableSt_A	9322746	391	0	0
PulseIsPulse_A	9322746	391	0	0
StayInStableSt	9322746	17647	0	0
gen_high_level_sva.HighLevelEvent_A	9322746	8668790	0	0
gen_not_sticky_sva.StableStDropOut_A	9322746	353	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	992	0	0
T1	16004	2	0	0
T2	8919	0	0	0
T3	5221	9	0	0
T4	31242	6	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	0	12	0	0
T27	0	26	0	0
T28	0	31	0	0
T29	0	10	0	0
T45	0	4	0	0
T46	0	8	0	0
T127	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	50720	0	0
T1	16004	62	0	0
T2	8919	0	0	0
T3	5221	350	0	0
T4	31242	314	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	0	804	0	0
T27	0	1768	0	0
T28	0	2353	0	0
T29	0	652	0	0
T45	0	126	0	0
T46	0	212	0	0
T127	0	361	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8665343	0	0
T1	16004	15582	0	0
T2	8919	4895	0	0
T3	5221	4811	0	0
T4	31242	23127	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	11521	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	14731	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	74	0	0
T3	5221	4	0	0
T4	31242	0	0	0
T7	13942	0	0	0
T8	1228	0	0	0
T9	2071	0	0	0
T10	628	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T40	0	5	0	0
T52	522	0	0	0
T91	0	4	0	0
T106	0	3	0	0
T127	0	2	0	0
T140	0	1	0	0
T202	0	1	0	0
T274	0	3	0	0
T275	0	10	0	0
T276	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	18073	0	0
T1	16004	74	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	79	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	0	394	0	0
T27	0	152	0	0
T28	0	274	0	0
T29	0	70	0	0
T45	0	107	0	0
T46	0	259	0	0
T49	0	11	0	0
T250	0	602	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	391	0	0
T1	16004	1	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	3	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	0	6	0	0
T27	0	13	0	0
T28	0	15	0	0
T29	0	4	0	0
T45	0	2	0	0
T46	0	4	0	0
T49	0	2	0	0
T250	0	9	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8272035	0	0
T1	16004	13170	0	0
T2	8919	4443	0	0
T3	5221	2015	0	0
T4	31242	17943	0	0
T5	422	21	0	0
T6	502	101	0	0
T7	13942	6961	0	0
T13	443	42	0	0
T14	505	104	0	0
T15	15149	13411	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8273708	0	0
T1	16004	13172	0	0
T2	8919	4453	0	0
T3	5221	2015	0	0
T4	31242	17966	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	6965	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	13414	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	523	0	0
T1	16004	1	0	0
T2	8919	0	0	0
T3	5221	5	0	0
T4	31242	3	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	0	6	0	0
T27	0	13	0	0
T28	0	16	0	0
T29	0	6	0	0
T45	0	2	0	0
T46	0	4	0	0
T127	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	469	0	0
T1	16004	1	0	0
T2	8919	0	0	0
T3	5221	4	0	0
T4	31242	3	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	0	6	0	0
T27	0	13	0	0
T28	0	15	0	0
T29	0	4	0	0
T45	0	2	0	0
T46	0	4	0	0
T127	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	391	0	0
T1	16004	1	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	3	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	0	6	0	0
T27	0	13	0	0
T28	0	15	0	0
T29	0	4	0	0
T45	0	2	0	0
T46	0	4	0	0
T49	0	2	0	0
T250	0	9	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	391	0	0
T1	16004	1	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	3	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	0	6	0	0
T27	0	13	0	0
T28	0	15	0	0
T29	0	4	0	0
T45	0	2	0	0
T46	0	4	0	0
T49	0	2	0	0
T250	0	9	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	17647	0	0
T1	16004	73	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	76	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	0	388	0	0
T27	0	139	0	0
T28	0	259	0	0
T29	0	66	0	0
T45	0	105	0	0
T46	0	255	0	0
T49	0	9	0	0
T250	0	593	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	8668790	0	0
T1	16004	15588	0	0
T2	8919	4906	0	0
T3	5221	4821	0	0
T4	31242	23163	0	0
T5	422	22	0	0
T6	502	102	0	0
T7	13942	11528	0	0
T13	443	43	0	0
T14	505	105	0	0
T15	15149	14734	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9322746	353	0	0
T1	16004	1	0	0
T2	8919	0	0	0
T3	5221	0	0	0
T4	31242	3	0	0
T6	502	0	0	0
T7	13942	0	0	0
T13	443	0	0	0
T14	505	0	0	0
T15	15149	0	0	0
T16	417	0	0	0
T21	0	6	0	0
T27	0	13	0	0
T28	0	15	0	0
T29	0	4	0	0
T45	0	2	0	0
T46	0	4	0	0
T49	0	2	0	0
T250	0	9	0	0