Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1288615529	10158	0	0
auto_block_debounce_ctl_rd_A	1288615529	2585	0	0
auto_block_out_ctl_rd_A	1288615529	3450	0	0
com_det_ctl_0_rd_A	1288615529	3813	0	0
com_det_ctl_1_rd_A	1288615529	3917	0	0
com_det_ctl_2_rd_A	1288615529	3919	0	0
com_det_ctl_3_rd_A	1288615529	3793	0	0
com_out_ctl_0_rd_A	1288615529	4920	0	0
com_out_ctl_1_rd_A	1288615529	4995	0	0
com_out_ctl_2_rd_A	1288615529	4862	0	0
com_out_ctl_3_rd_A	1288615529	5093	0	0
com_pre_det_ctl_0_rd_A	1288615529	1929	0	0
com_pre_det_ctl_1_rd_A	1288615529	1955	0	0
com_pre_det_ctl_2_rd_A	1288615529	2028	0	0
com_pre_det_ctl_3_rd_A	1288615529	1987	0	0
com_pre_sel_ctl_0_rd_A	1288615529	5187	0	0
com_pre_sel_ctl_1_rd_A	1288615529	5258	0	0
com_pre_sel_ctl_2_rd_A	1288615529	4871	0	0
com_pre_sel_ctl_3_rd_A	1288615529	5341	0	0
com_sel_ctl_0_rd_A	1288615529	5320	0	0
com_sel_ctl_1_rd_A	1288615529	5028	0	0
com_sel_ctl_2_rd_A	1288615529	5328	0	0
com_sel_ctl_3_rd_A	1288615529	5085	0	0
ec_rst_ctl_rd_A	1288615529	2837	0	0
intr_enable_rd_A	1288615529	2792	0	0
key_intr_ctl_rd_A	1288615529	6272	0	0
key_intr_debounce_ctl_rd_A	1288615529	1937	0	0
key_invert_ctl_rd_A	1288615529	6599	0	0
pin_allowed_ctl_rd_A	1288615529	9148	0	0
pin_out_ctl_rd_A	1288615529	6470	0	0
pin_out_value_rd_A	1288615529	6659	0	0
regwen_rd_A	1288615529	2147	0	0
ulp_ac_debounce_ctl_rd_A	1288615529	2018	0	0
ulp_ctl_rd_A	1288615529	2066	0	0
ulp_lid_debounce_ctl_rd_A	1288615529	2029	0	0
ulp_pwrb_debounce_ctl_rd_A	1288615529	2080	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1288615529	10158	0	0
T2	104629	11	0	0
T3	125298	0	0	0
T4	155810	6	0	0
T7	125480	0	0	0
T8	30496	0	0	0
T9	68979	0	0	0
T11	0	21	0	0
T14	55649	0	0	0
T15	181792	0	0	0
T16	208773	0	0	0
T29	0	11	0	0
T33	0	9	0	0
T34	0	9	0	0
T40	0	12	0	0
T43	0	5	0	0
T52	258623	0	0	0
T75	0	9	0	0
T150	0	9	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1288615529	2585	0	0
T4	155810	41	0	0
T7	125480	0	0	0
T8	30496	0	0	0
T9	68979	0	0	0
T10	314529	0	0	0
T14	55649	0	0	0
T15	181792	0	0	0
T16	208773	0	0	0
T21	732570	0	0	0
T29	0	32	0	0
T34	0	21	0	0
T42	0	16	0	0
T52	258623	0	0	0
T75	0	7	0	0
T150	0	15	0	0
T301	0	9	0	0
T302	0	12	0	0
T303	0	50	0	0
T304	0	11	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1288615529	3450	0	0
T4	155810	34	0	0
T7	125480	0	0	0
T8	30496	0	0	0
T9	68979	0	0	0
T10	314529	0	0	0
T14	55649	0	0	0
T15	181792	0	0	0
T16	208773	0	0	0
T21	732570	0	0	0
T29	0	44	0	0
T34	0	23	0	0
T42	0	15	0	0
T52	258623	0	0	0
T75	0	14	0	0
T150	0	35	0	0
T301	0	1	0	0
T302	0	13	0	0
T303	0	36	0	0
T304	0	15	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1288615529	3813	0	0
T3	125298	57	0	0
T4	155810	108	0	0
T7	125480	0	0	0
T8	30496	0	0	0
T9	68979	0	0	0
T10	314529	0	0	0
T14	55649	0	0	0
T15	181792	0	0	0
T16	208773	0	0	0
T28	0	75	0	0
T29	0	84	0	0
T34	0	28	0	0
T46	0	26	0	0
T52	258623	0	0	0
T75	0	9	0	0
T91	0	73	0	0
T150	0	77	0	0
T252	0	67	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1288615529	3917	0	0
T3	125298	56	0	0
T4	155810	152	0	0
T7	125480	0	0	0
T8	30496	0	0	0
T9	68979	0	0	0
T10	314529	0	0	0
T14	55649	0	0	0
T15	181792	0	0	0
T16	208773	0	0	0
T28	0	57	0	0
T29	0	100	0	0
T34	0	12	0	0
T46	0	28	0	0
T52	258623	0	0	0
T75	0	6	0	0
T91	0	70	0	0
T150	0	85	0	0
T252	0	48	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1288615529	3919	0	0
T3	125298	73	0	0
T4	155810	124	0	0
T7	125480	0	0	0
T8	30496	0	0	0
T9	68979	0	0	0
T10	314529	0	0	0
T14	55649	0	0	0
T15	181792	0	0	0
T16	208773	0	0	0
T28	0	73	0	0
T29	0	113	0	0
T34	0	20	0	0
T46	0	24	0	0
T52	258623	0	0	0
T75	0	1	0	0
T91	0	55	0	0
T150	0	110	0	0
T252	0	63	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1288615529	3793	0	0
T3	125298	43	0	0
T4	155810	127	0	0
T7	125480	0	0	0
T8	30496	0	0	0
T9	68979	0	0	0
T10	314529	0	0	0
T14	55649	0	0	0
T15	181792	0	0	0
T16	208773	0	0	0
T28	0	69	0	0
T29	0	104	0	0
T34	0	21	0	0
T46	0	15	0	0
T52	258623	0	0	0
T75	0	10	0	0
T91	0	71	0	0
T150	0	86	0	0
T252	0	51	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1288615529	4920	0	0
T3	125298	99	0	0
T4	155810	112	0	0
T7	125480	0	0	0
T8	30496	0	0	0
T9	68979	0	0	0
T10	314529	0	0	0
T14	55649	0	0	0
T15	181792	0	0	0
T16	208773	0	0	0
T28	0	79	0	0
T29	0	101	0	0
T34	0	14	0	0
T46	0	14	0	0
T52	258623	0	0	0
T91	0	56	0	0
T150	0	103	0	0
T252	0	84	0	0
T305	0	75	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1288615529	4995	0	0
T3	125298	59	0	0
T4	155810	124	0	0
T7	125480	0	0	0
T8	30496	0	0	0
T9	68979	0	0	0
T10	314529	0	0	0
T14	55649	0	0	0
T15	181792	0	0	0
T16	208773	0	0	0
T28	0	66	0	0
T29	0	90	0	0
T34	0	15	0	0
T46	0	27	0	0
T52	258623	0	0	0
T91	0	79	0	0
T150	0	73	0	0
T252	0	64	0	0
T305	0	80	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1288615529	4862	0	0
T3	125298	81	0	0
T4	155810	129	0	0
T7	125480	0	0	0
T8	30496	0	0	0
T9	68979	0	0	0
T10	314529	0	0	0
T14	55649	0	0	0
T15	181792	0	0	0
T16	208773	0	0	0
T28	0	82	0	0
T29	0	80	0	0
T34	0	23	0	0
T46	0	34	0	0
T52	258623	0	0	0
T75	0	8	0	0
T91	0	72	0	0
T150	0	110	0	0
T252	0	81	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1288615529	5093	0	0
T3	125298	65	0	0
T4	155810	104	0	0
T7	125480	0	0	0
T8	30496	0	0	0
T9	68979	0	0	0
T10	314529	0	0	0
T14	55649	0	0	0
T15	181792	0	0	0
T16	208773	0	0	0
T28	0	91	0	0
T29	0	106	0	0
T34	0	9	0	0
T46	0	34	0	0
T52	258623	0	0	0
T75	0	5	0	0
T91	0	75	0	0
T150	0	77	0	0
T252	0	50	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1288615529	1929	0	0
T4	155810	11	0	0
T7	125480	0	0	0
T8	30496	0	0	0
T9	68979	0	0	0
T10	314529	0	0	0
T14	55649	0	0	0
T15	181792	0	0	0
T16	208773	0	0	0
T21	732570	0	0	0
T29	0	41	0	0
T34	0	11	0	0
T52	258623	0	0	0
T75	0	6	0	0
T104	0	33	0	0
T136	0	9	0	0
T150	0	9	0	0
T303	0	12	0	0
T306	0	20	0	0
T307	0	30	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1288615529	1955	0	0
T4	155810	24	0	0
T7	125480	0	0	0
T8	30496	0	0	0
T9	68979	0	0	0
T10	314529	0	0	0
T14	55649	0	0	0
T15	181792	0	0	0
T16	208773	0	0	0
T21	732570	0	0	0
T29	0	27	0	0
T34	0	12	0	0
T52	258623	0	0	0
T75	0	4	0	0
T104	0	36	0	0
T136	0	10	0	0
T150	0	24	0	0
T303	0	35	0	0
T306	0	16	0	0
T307	0	16	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1288615529	2028	0	0
T4	155810	25	0	0
T7	125480	0	0	0
T8	30496	0	0	0
T9	68979	0	0	0
T10	314529	0	0	0
T14	55649	0	0	0
T15	181792	0	0	0
T16	208773	0	0	0
T21	732570	0	0	0
T29	0	28	0	0
T34	0	35	0	0
T52	258623	0	0	0
T75	0	10	0	0
T104	0	20	0	0
T136	0	18	0	0
T150	0	13	0	0
T303	0	35	0	0
T306	0	23	0	0
T307	0	29	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1288615529	1987	0	0
T4	155810	30	0	0
T7	125480	0	0	0
T8	30496	0	0	0
T9	68979	0	0	0
T10	314529	0	0	0
T14	55649	0	0	0
T15	181792	0	0	0
T16	208773	0	0	0
T21	732570	0	0	0
T29	0	34	0	0
T34	0	13	0	0
T52	258623	0	0	0
T75	0	15	0	0
T104	0	32	0	0
T136	0	8	0	0
T150	0	13	0	0
T303	0	39	0	0
T306	0	21	0	0
T307	0	21	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1288615529	5187	0	0
T3	125298	73	0	0
T4	155810	111	0	0
T7	125480	0	0	0
T8	30496	0	0	0
T9	68979	0	0	0
T10	314529	0	0	0
T14	55649	0	0	0
T15	181792	0	0	0
T16	208773	0	0	0
T28	0	77	0	0
T29	0	89	0	0
T34	0	18	0	0
T46	0	25	0	0
T52	258623	0	0	0
T75	0	8	0	0
T91	0	82	0	0
T150	0	89	0	0
T252	0	59	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1288615529	5258	0	0
T3	125298	72	0	0
T4	155810	114	0	0
T7	125480	0	0	0
T8	30496	0	0	0
T9	68979	0	0	0
T10	314529	0	0	0
T14	55649	0	0	0
T15	181792	0	0	0
T16	208773	0	0	0
T28	0	85	0	0
T29	0	101	0	0
T34	0	29	0	0
T46	0	46	0	0
T52	258623	0	0	0
T75	0	3	0	0
T91	0	68	0	0
T150	0	66	0	0
T252	0	86	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1288615529	4871	0	0
T3	125298	60	0	0
T4	155810	105	0	0
T7	125480	0	0	0
T8	30496	0	0	0
T9	68979	0	0	0
T10	314529	0	0	0
T14	55649	0	0	0
T15	181792	0	0	0
T16	208773	0	0	0
T28	0	55	0	0
T29	0	122	0	0
T34	0	17	0	0
T46	0	23	0	0
T52	258623	0	0	0
T75	0	17	0	0
T91	0	53	0	0
T150	0	93	0	0
T252	0	49	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1288615529	5341	0	0
T3	125298	46	0	0
T4	155810	99	0	0
T7	125480	0	0	0
T8	30496	0	0	0
T9	68979	0	0	0
T10	314529	0	0	0
T14	55649	0	0	0
T15	181792	0	0	0
T16	208773	0	0	0
T28	0	72	0	0
T29	0	83	0	0
T34	0	22	0	0
T46	0	16	0	0
T52	258623	0	0	0
T75	0	7	0	0
T91	0	66	0	0
T150	0	76	0	0
T252	0	76	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1288615529	5320	0	0
T3	125298	90	0	0
T4	155810	126	0	0
T7	125480	0	0	0
T8	30496	0	0	0
T9	68979	0	0	0
T10	314529	0	0	0
T14	55649	0	0	0
T15	181792	0	0	0
T16	208773	0	0	0
T28	0	66	0	0
T29	0	86	0	0
T34	0	17	0	0
T46	0	32	0	0
T52	258623	0	0	0
T75	0	13	0	0
T91	0	53	0	0
T150	0	66	0	0
T252	0	86	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1288615529	5028	0	0
T3	125298	86	0	0
T4	155810	117	0	0
T7	125480	0	0	0
T8	30496	0	0	0
T9	68979	0	0	0
T10	314529	0	0	0
T14	55649	0	0	0
T15	181792	0	0	0
T16	208773	0	0	0
T28	0	58	0	0
T29	0	78	0	0
T34	0	20	0	0
T46	0	38	0	0
T52	258623	0	0	0
T91	0	82	0	0
T150	0	97	0	0
T252	0	73	0	0
T305	0	70	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1288615529	5328	0	0
T3	125298	79	0	0
T4	155810	116	0	0
T7	125480	0	0	0
T8	30496	0	0	0
T9	68979	0	0	0
T10	314529	0	0	0
T14	55649	0	0	0
T15	181792	0	0	0
T16	208773	0	0	0
T28	0	85	0	0
T29	0	106	0	0
T34	0	26	0	0
T46	0	60	0	0
T52	258623	0	0	0
T75	0	11	0	0
T91	0	58	0	0
T150	0	109	0	0
T252	0	91	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1288615529	5085	0	0
T3	125298	77	0	0
T4	155810	120	0	0
T7	125480	0	0	0
T8	30496	0	0	0
T9	68979	0	0	0
T10	314529	0	0	0
T14	55649	0	0	0
T15	181792	0	0	0
T16	208773	0	0	0
T28	0	81	0	0
T29	0	103	0	0
T34	0	4	0	0
T46	0	36	0	0
T52	258623	0	0	0
T75	0	5	0	0
T91	0	86	0	0
T150	0	90	0	0
T252	0	80	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1288615529	2837	0	0
T4	155810	55	0	0
T7	125480	0	0	0
T8	30496	0	0	0
T9	68979	0	0	0
T10	314529	0	0	0
T14	55649	0	0	0
T15	181792	0	0	0
T16	208773	0	0	0
T21	732570	0	0	0
T28	0	44	0	0
T29	0	40	0	0
T34	0	13	0	0
T46	0	13	0	0
T52	258623	0	0	0
T91	0	28	0	0
T93	0	2	0	0
T94	0	3	0	0
T150	0	46	0	0
T252	0	26	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1288615529	2792	0	0
T4	155810	27	0	0
T7	125480	0	0	0
T8	30496	0	0	0
T9	68979	0	0	0
T10	314529	0	0	0
T14	55649	0	0	0
T15	181792	0	0	0
T16	208773	0	0	0
T21	732570	0	0	0
T29	0	14	0	0
T34	0	10	0	0
T52	258623	0	0	0
T75	0	13	0	0
T136	0	75	0	0
T150	0	22	0	0
T297	0	13	0	0
T303	0	53	0	0
T306	0	41	0	0
T308	0	8	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1288615529	6272	0	0
T4	155810	22	0	0
T7	125480	0	0	0
T8	30496	0	0	0
T9	68979	0	0	0
T10	314529	6	0	0
T14	55649	0	0	0
T15	181792	0	0	0
T16	208773	0	0	0
T21	732570	0	0	0
T29	0	32	0	0
T34	0	17	0	0
T35	0	7	0	0
T36	0	3	0	0
T38	0	1	0	0
T52	258623	0	0	0
T75	0	1	0	0
T79	0	6	0	0
T150	0	11	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1288615529	1937	0	0
T4	155810	22	0	0
T7	125480	0	0	0
T8	30496	0	0	0
T9	68979	0	0	0
T10	314529	0	0	0
T14	55649	0	0	0
T15	181792	0	0	0
T16	208773	0	0	0
T21	732570	0	0	0
T29	0	25	0	0
T34	0	32	0	0
T52	258623	0	0	0
T75	0	6	0	0
T104	0	54	0	0
T136	0	9	0	0
T150	0	18	0	0
T303	0	20	0	0
T306	0	21	0	0
T307	0	17	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1288615529	6599	0	0
T4	155810	23	0	0
T7	125480	0	0	0
T8	30496	0	0	0
T9	68979	0	0	0
T10	314529	0	0	0
T14	55649	0	0	0
T15	181792	0	0	0
T16	208773	0	0	0
T21	732570	0	0	0
T29	0	22	0	0
T34	0	12	0	0
T41	0	24	0	0
T52	258623	0	0	0
T150	0	13	0	0
T297	0	52	0	0
T309	0	61	0	0
T310	0	75	0	0
T311	0	64	0	0
T312	0	62	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1288615529	9148	0	0
T2	104629	0	0	0
T3	125298	0	0	0
T4	155810	90	0	0
T6	248342	56	0	0
T7	125480	0	0	0
T13	221989	0	0	0
T14	55649	69	0	0
T15	181792	0	0	0
T16	208773	0	0	0
T29	0	80	0	0
T34	0	175	0	0
T52	258623	0	0	0
T54	0	77	0	0
T169	0	59	0	0
T170	0	29	0	0
T190	0	31	0	0
T300	0	68	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1288615529	6470	0	0
T2	104629	0	0	0
T3	125298	0	0	0
T4	155810	90	0	0
T6	248342	103	0	0
T7	125480	0	0	0
T13	221989	0	0	0
T14	55649	73	0	0
T15	181792	0	0	0
T16	208773	0	0	0
T29	0	74	0	0
T34	0	187	0	0
T52	258623	0	0	0
T54	0	73	0	0
T169	0	86	0	0
T170	0	20	0	0
T190	0	37	0	0
T300	0	57	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1288615529	6659	0	0
T2	104629	0	0	0
T3	125298	0	0	0
T4	155810	92	0	0
T6	248342	59	0	0
T7	125480	0	0	0
T13	221989	0	0	0
T14	55649	63	0	0
T15	181792	0	0	0
T16	208773	0	0	0
T29	0	83	0	0
T34	0	160	0	0
T52	258623	0	0	0
T54	0	71	0	0
T169	0	61	0	0
T170	0	38	0	0
T190	0	29	0	0
T300	0	63	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1288615529	2147	0	0
T4	155810	19	0	0
T7	125480	0	0	0
T8	30496	0	0	0
T9	68979	0	0	0
T10	314529	0	0	0
T14	55649	0	0	0
T15	181792	0	0	0
T16	208773	0	0	0
T21	732570	0	0	0
T29	0	26	0	0
T34	0	18	0	0
T52	258623	0	0	0
T75	0	1	0	0
T104	0	15	0	0
T136	0	2	0	0
T150	0	21	0	0
T303	0	20	0	0
T306	0	16	0	0
T307	0	14	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1288615529	2018	0	0
T4	155810	18	0	0
T7	125480	0	0	0
T8	30496	0	0	0
T9	68979	9	0	0
T10	314529	0	0	0
T12	0	9	0	0
T14	55649	0	0	0
T15	181792	0	0	0
T16	208773	0	0	0
T21	732570	0	0	0
T29	0	18	0	0
T34	0	35	0	0
T52	258623	0	0	0
T73	0	14	0	0
T74	0	1	0	0
T75	0	16	0	0
T150	0	20	0	0
T313	0	3	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1288615529	2066	0	0
T4	155810	17	0	0
T7	125480	0	0	0
T8	30496	0	0	0
T9	68979	5	0	0
T10	314529	0	0	0
T12	0	10	0	0
T14	55649	0	0	0
T15	181792	0	0	0
T16	208773	0	0	0
T21	732570	0	0	0
T29	0	28	0	0
T34	0	30	0	0
T52	258623	0	0	0
T73	0	13	0	0
T74	0	2	0	0
T75	0	16	0	0
T150	0	14	0	0
T297	0	4	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1288615529	2029	0	0
T4	155810	17	0	0
T7	125480	0	0	0
T8	30496	0	0	0
T9	68979	10	0	0
T10	314529	0	0	0
T12	0	4	0	0
T14	55649	0	0	0
T15	181792	0	0	0
T16	208773	0	0	0
T21	732570	0	0	0
T29	0	32	0	0
T34	0	22	0	0
T52	258623	0	0	0
T71	0	1	0	0
T73	0	11	0	0
T74	0	1	0	0
T150	0	20	0	0
T297	0	1	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1288615529	2080	0	0
T4	155810	29	0	0
T7	125480	0	0	0
T8	30496	0	0	0
T9	68979	6	0	0
T10	314529	0	0	0
T12	0	10	0	0
T14	55649	0	0	0
T15	181792	0	0	0
T16	208773	0	0	0
T21	732570	0	0	0
T29	0	26	0	0
T34	0	24	0	0
T52	258623	0	0	0
T73	0	11	0	0
T74	0	4	0	0
T75	0	10	0	0
T150	0	11	0	0
T313	0	5	0	0