Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
92.68	92.68	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	92.68	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.68	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	6	56	90.32

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	6	25	80.65	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1958

1

T8

10

T9

3

T27

12

auto[1]

667

1

T8

14

T9

5

T41

2

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2030

1

T8

24

T41

2

T27

9

auto[1]

595

1

T9

8

T27

3

T34

11

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1983

1

T8

13

T9

8

T27

7

auto[1]

642

1

T8

11

T41

2

T27

5

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1933

1

T8

13

T27

12

T34

34

auto[1]

692

1

T8

11

T9

8

T41

2

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2397

1

T8

24

T9

8

T41

2

auto[1]

228

1

T34

21

T36

6

T70

4

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2353

1

T8

16

T9

8

T41

2

auto[1]

272

1

T8

8

T27

2

T70

4

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2430

1

T8

21

T9

8

T41

2

auto[1]

195

1

T8

3

T34

15

T46

1

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2421

1

T8

21

T9

8

T41

2

auto[1]

204

1

T8

3

T27

2

T34

1

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2383

1

T8

10

T9

8

T41

2

auto[1]

242

1

T8

14

T27

5

T34

5

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1993

1

T8

24

T9

5

T27

12

auto[1]

632

1

T9

3

T41

2

T34

12

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	6	25	80.65	6
Automatically Generated Cross Bins	31	6	25	80.65	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	908	1			T9	8		T41	2		T35	8
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	59	1			T34	11		T272	2		T98	1
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	41	1			T8	4		T27	3		T69	8
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	19	1			T96	2		T366	4		T367	1
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	44	1			T98	1		T368	2		T369	7
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	19	1			T366	5		T361	3		T359	6
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	40	1			T69	5		T369	7		T282	1
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	10	1			T274	2		T370	2		T371	4
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	83	1			T36	6		T70	51		T83	1
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	26	1			T34	9		T36	6		T72	1
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	15	1			T34	5		T94	4		T282	1
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	2	1			T372	1		T373	1		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	1	1			T374	1		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	1	1			T34	1		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	3	1			T46	1		T359	2		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	79	1			T72	5		T375	3		T369	2
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	50	1			T70	4		T361	3		T371	6
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	36	1			T8	3		T72	5		T83	1
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	1	1			T277	1		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	18	1			T376	3		T377	2		T378	6
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	18	1			T27	2		T328	2		T379	3
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	20	1			T366	1		T368	1		T283	2
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	15	1			T328	3		T380	2		T365	9
auto[1]	auto[1]	auto[1]	auto[0]	auto[1]	2	1			T263	2		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[1]	auto[0]	3	1			T8	2		T381	1		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

155

1

T8

2

T196

11

T201

6

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

97

1

T34

1

T366

1

T98

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

54

1

T285

7

T328

3

T278

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

88

1

T34

9

T94

4

T232

8

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

80

1

T34

5

T92

3

T69

8

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

73

1

T37

1

T72

1

T206

7

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

45

1

T35

3

T37

1

T93

6

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

111

1

T27

2

T122

18

T69

5

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

45

1

T232

8

T87

2

T382

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

74

1

T196

3

T201

2

T95

7

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

22

1

T35

2

T196

2

T284

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

48

1

T44

6

T196

2

T286

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

45

1

T8

7

T37

1

T72

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

25

1

T70

4

T196

2

T153

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

16

1

T41

2

T196

1

T201

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

75

1

T46

1

T90

10

T39

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

44

1

T158

1

T355

5

T361

8

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

42

1

T44

3

T196

7

T353

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

21

1

T122

1

T97

1

T382

5

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

89

1

T35

3

T36

6

T284

10

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

50

1

T9

5

T70

17

T279

5

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

28

1

T9

3

T36

6

T201

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

2

1

T201

1

T83

1

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

52

1

T27

3

T366

4

T368

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

18

1

T158

1

T354

5

T363

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

44

1

T34

11

T284

1

T102

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

16

1

T196

3

T279

6

T355

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

22

1

T272

2

T84

2

T383

6

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

5

1

T96

2

T356

2

T384

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

23

1

T284

4

T385

8

T362

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T356

4

-

-

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded