Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.44	99.42	96.76	100.00	98.08	98.89	99.71	89.25

Total tests in report: 913

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
45.72	45.72	62.47	62.47	46.49	46.49	84.82	84.82	5.13	5.13	65.95	65.95	52.02	52.02	3.17	3.17	/workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.2332546892
67.68	21.96	81.62	19.15	73.00	26.52	90.30	5.48	41.03	35.90	84.07	18.11	74.76	22.74	28.97	25.80	/workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.2891216403
76.04	8.36	91.16	9.54	85.19	12.18	93.95	3.65	51.28	10.26	91.57	7.50	84.97	10.21	34.16	5.19	/workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.2334976358
81.60	5.56	92.41	1.25	86.75	1.57	94.18	0.23	58.97	7.69	92.57	1.00	90.94	5.97	55.40	21.24	/workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.3048780134
85.37	3.76	94.12	1.72	88.75	2.00	94.18	0.00	78.85	19.87	94.27	1.70	91.91	0.96	55.50	0.10	/workspace/coverage/default/0.sysrst_ctrl_feature_disable.3081600762
87.62	2.25	94.87	0.75	89.51	0.76	94.18	0.00	83.33	4.49	94.82	0.55	93.55	1.64	63.08	7.58	/workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.1657317775
89.40	1.78	97.57	2.71	92.39	2.88	96.35	2.17	83.33	0.00	96.93	2.11	94.61	1.06	64.64	1.56	/workspace/coverage/default/36.sysrst_ctrl_pin_override_test.3081756993
90.76	1.36	98.08	0.50	92.77	0.38	96.35	0.00	87.82	4.49	97.41	0.48	96.05	1.45	66.87	2.23	/workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.3326688281
91.96	1.20	98.15	0.07	93.91	1.14	97.03	0.68	87.82	0.00	97.52	0.11	96.05	0.00	73.26	6.39	/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.1823263111
92.95	0.98	98.21	0.06	93.98	0.08	98.17	1.14	87.82	0.00	97.52	0.00	96.05	0.00	78.87	5.61	/workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.3556096723
93.72	0.77	98.54	0.34	94.29	0.30	98.17	0.00	91.03	3.21	97.78	0.26	96.92	0.87	79.28	0.42	/workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.2906507157
94.05	0.33	98.64	0.09	94.36	0.08	98.17	0.00	92.31	1.28	97.89	0.11	97.21	0.29	79.75	0.47	/workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.2644086439
94.33	0.28	98.64	0.00	94.39	0.03	99.77	1.60	92.31	0.00	97.89	0.00	97.30	0.10	80.01	0.26	/workspace/coverage/default/1.sysrst_ctrl_sec_cm.1005529147
94.61	0.28	98.69	0.06	94.44	0.05	99.77	0.00	92.95	0.64	97.97	0.07	97.50	0.19	80.94	0.93	/workspace/coverage/default/34.sysrst_ctrl_stress_all.1556500944
94.88	0.27	98.79	0.09	94.54	0.10	99.77	0.00	94.23	1.28	98.08	0.11	97.78	0.29	80.94	0.00	/workspace/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.2749264846
95.12	0.24	98.86	0.07	94.59	0.05	99.77	0.00	95.51	1.28	98.15	0.07	97.98	0.19	80.94	0.00	/workspace/coverage/default/41.sysrst_ctrl_edge_detect.109019556
95.34	0.23	98.86	0.00	94.62	0.03	99.77	0.00	95.51	0.00	98.15	0.00	98.07	0.10	82.40	1.45	/workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.219843965
95.52	0.18	98.88	0.02	94.62	0.00	99.77	0.00	95.51	0.00	98.15	0.00	98.07	0.00	83.64	1.25	/workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.4202784124
95.68	0.16	98.92	0.04	94.64	0.03	99.77	0.00	96.15	0.64	98.19	0.04	98.17	0.10	83.90	0.26	/workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.2427635639
95.81	0.13	98.92	0.00	95.42	0.78	99.77	0.00	96.15	0.00	98.19	0.00	98.17	0.00	84.06	0.16	/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.1741710929
95.94	0.13	98.92	0.00	95.53	0.10	99.77	0.00	96.15	0.00	98.19	0.00	98.75	0.58	84.27	0.21	/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.90349995
96.06	0.12	98.94	0.02	95.53	0.00	99.77	0.00	96.15	0.00	98.19	0.00	98.75	0.00	85.10	0.83	/workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.1155392056
96.18	0.12	98.97	0.04	95.55	0.03	99.77	0.00	96.79	0.64	98.23	0.04	98.84	0.10	85.10	0.00	/workspace/coverage/default/23.sysrst_ctrl_edge_detect.2375090871
96.30	0.12	99.01	0.04	95.58	0.03	99.77	0.00	97.44	0.64	98.26	0.04	98.94	0.10	85.10	0.00	/workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.4242773754
96.42	0.12	99.05	0.04	95.60	0.03	99.77	0.00	98.08	0.64	98.30	0.04	99.04	0.10	85.10	0.00	/workspace/coverage/default/42.sysrst_ctrl_edge_detect.204402111
96.51	0.09	99.09	0.04	95.65	0.05	99.77	0.00	98.08	0.00	98.37	0.07	99.13	0.10	85.46	0.36	/workspace/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.753274138
96.58	0.08	99.09	0.00	95.68	0.03	99.77	0.00	98.08	0.00	98.37	0.00	99.23	0.10	85.88	0.42	/workspace/coverage/default/8.sysrst_ctrl_combo_detect.1912195752
96.65	0.07	99.12	0.04	95.83	0.15	99.77	0.00	98.08	0.00	98.45	0.07	99.42	0.19	85.88	0.00	/workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.485697908
96.71	0.06	99.12	0.00	95.85	0.03	99.77	0.00	98.08	0.00	98.45	0.00	99.42	0.00	86.29	0.42	/workspace/coverage/default/17.sysrst_ctrl_combo_detect.4094781091
96.77	0.06	99.14	0.02	96.23	0.38	99.77	0.00	98.08	0.00	98.48	0.04	99.42	0.00	86.29	0.00	/workspace/coverage/default/1.sysrst_ctrl_feature_disable.1801009082
96.83	0.05	99.14	0.00	96.28	0.05	99.77	0.00	98.08	0.00	98.48	0.00	99.42	0.00	86.60	0.31	/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.1993407473
96.88	0.05	99.20	0.06	96.36	0.08	100.00	0.23	98.08	0.00	98.48	0.00	99.42	0.00	86.60	0.00	/workspace/coverage/default/15.sysrst_ctrl_alert_test.2926127819
96.93	0.05	99.22	0.02	96.36	0.00	100.00	0.00	98.08	0.00	98.52	0.04	99.52	0.10	86.81	0.21	/workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.3348047910
96.97	0.04	99.22	0.00	96.36	0.00	100.00	0.00	98.08	0.00	98.52	0.00	99.52	0.00	87.12	0.31	/workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.2346722902
97.02	0.04	99.23	0.02	96.44	0.08	100.00	0.00	98.08	0.00	98.52	0.00	99.61	0.10	87.23	0.10	/workspace/coverage/default/36.sysrst_ctrl_stress_all.2666163739
97.05	0.04	99.23	0.00	96.44	0.00	100.00	0.00	98.08	0.00	98.52	0.00	99.61	0.00	87.49	0.26	/workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.1429842360
97.08	0.03	99.23	0.00	96.44	0.00	100.00	0.00	98.08	0.00	98.52	0.00	99.61	0.00	87.69	0.21	/workspace/coverage/default/15.sysrst_ctrl_combo_detect.1007788138
97.11	0.03	99.23	0.00	96.44	0.00	100.00	0.00	98.08	0.00	98.52	0.00	99.61	0.00	87.90	0.21	/workspace/coverage/default/25.sysrst_ctrl_pin_override_test.1655382610
97.14	0.03	99.23	0.00	96.64	0.20	100.00	0.00	98.08	0.00	98.52	0.00	99.61	0.00	87.90	0.00	/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.368594572
97.17	0.02	99.23	0.00	96.66	0.03	100.00	0.00	98.08	0.00	98.52	0.00	99.71	0.10	87.95	0.05	/workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.3367177478
97.19	0.02	99.25	0.02	96.66	0.00	100.00	0.00	98.08	0.00	98.56	0.04	99.71	0.00	88.06	0.10	/workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.1671935231
97.21	0.02	99.25	0.00	96.66	0.00	100.00	0.00	98.08	0.00	98.56	0.00	99.71	0.00	88.21	0.16	/workspace/coverage/default/40.sysrst_ctrl_combo_detect.2871249743
97.23	0.02	99.29	0.04	96.66	0.00	100.00	0.00	98.08	0.00	98.63	0.07	99.71	0.00	88.21	0.00	/workspace/coverage/default/17.sysrst_ctrl_edge_detect.2660443812
97.24	0.02	99.33	0.04	96.66	0.00	100.00	0.00	98.08	0.00	98.71	0.07	99.71	0.00	88.21	0.00	/workspace/coverage/default/38.sysrst_ctrl_stress_all.3866855722
97.26	0.02	99.37	0.04	96.66	0.00	100.00	0.00	98.08	0.00	98.78	0.07	99.71	0.00	88.21	0.00	/workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.3418633280
97.27	0.01	99.37	0.00	96.66	0.00	100.00	0.00	98.08	0.00	98.78	0.00	99.71	0.00	88.32	0.10	/workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.255775761
97.29	0.01	99.37	0.00	96.66	0.00	100.00	0.00	98.08	0.00	98.78	0.00	99.71	0.00	88.42	0.10	/workspace/coverage/default/32.sysrst_ctrl_pin_override_test.3277125411
97.30	0.01	99.37	0.00	96.69	0.03	100.00	0.00	98.08	0.00	98.78	0.00	99.71	0.00	88.47	0.05	/workspace/coverage/default/19.sysrst_ctrl_stress_all.2557882489
97.31	0.01	99.38	0.02	96.69	0.00	100.00	0.00	98.08	0.00	98.82	0.04	99.71	0.00	88.47	0.00	/workspace/coverage/default/0.sysrst_ctrl_edge_detect.3859337042
97.32	0.01	99.40	0.02	96.69	0.00	100.00	0.00	98.08	0.00	98.85	0.04	99.71	0.00	88.47	0.00	/workspace/coverage/default/13.sysrst_ctrl_edge_detect.2528246071
97.32	0.01	99.42	0.02	96.69	0.00	100.00	0.00	98.08	0.00	98.89	0.04	99.71	0.00	88.47	0.00	/workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.77114626
97.33	0.01	99.42	0.00	96.69	0.00	100.00	0.00	98.08	0.00	98.89	0.00	99.71	0.00	88.53	0.05	/workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.1804384451
97.34	0.01	99.42	0.00	96.69	0.00	100.00	0.00	98.08	0.00	98.89	0.00	99.71	0.00	88.58	0.05	/workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.4143398713
97.35	0.01	99.42	0.00	96.69	0.00	100.00	0.00	98.08	0.00	98.89	0.00	99.71	0.00	88.63	0.05	/workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.3016465036
97.35	0.01	99.42	0.00	96.69	0.00	100.00	0.00	98.08	0.00	98.89	0.00	99.71	0.00	88.68	0.05	/workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.258682633
97.36	0.01	99.42	0.00	96.69	0.00	100.00	0.00	98.08	0.00	98.89	0.00	99.71	0.00	88.73	0.05	/workspace/coverage/default/22.sysrst_ctrl_combo_detect.3623125828
97.37	0.01	99.42	0.00	96.69	0.00	100.00	0.00	98.08	0.00	98.89	0.00	99.71	0.00	88.79	0.05	/workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.3239384937
97.38	0.01	99.42	0.00	96.69	0.00	100.00	0.00	98.08	0.00	98.89	0.00	99.71	0.00	88.84	0.05	/workspace/coverage/default/27.sysrst_ctrl_combo_detect.3842105994
97.38	0.01	99.42	0.00	96.69	0.00	100.00	0.00	98.08	0.00	98.89	0.00	99.71	0.00	88.89	0.05	/workspace/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.3975031402
97.39	0.01	99.42	0.00	96.69	0.00	100.00	0.00	98.08	0.00	98.89	0.00	99.71	0.00	88.94	0.05	/workspace/coverage/default/32.sysrst_ctrl_combo_detect.2172431950
97.40	0.01	99.42	0.00	96.69	0.00	100.00	0.00	98.08	0.00	98.89	0.00	99.71	0.00	88.99	0.05	/workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.2474277007
97.40	0.01	99.42	0.00	96.69	0.00	100.00	0.00	98.08	0.00	98.89	0.00	99.71	0.00	89.04	0.05	/workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.3945975968
97.41	0.01	99.42	0.00	96.69	0.00	100.00	0.00	98.08	0.00	98.89	0.00	99.71	0.00	89.10	0.05	/workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.2370635991
97.42	0.01	99.42	0.00	96.69	0.00	100.00	0.00	98.08	0.00	98.89	0.00	99.71	0.00	89.15	0.05	/workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.1367979967
97.43	0.01	99.42	0.00	96.69	0.00	100.00	0.00	98.08	0.00	98.89	0.00	99.71	0.00	89.20	0.05	/workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.2954661950
97.43	0.01	99.42	0.00	96.69	0.00	100.00	0.00	98.08	0.00	98.89	0.00	99.71	0.00	89.25	0.05	/workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.2648560157
97.44	0.01	99.42	0.00	96.71	0.03	100.00	0.00	98.08	0.00	98.89	0.00	99.71	0.00	89.25	0.00	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.1857875386
97.44	0.01	99.42	0.00	96.74	0.03	100.00	0.00	98.08	0.00	98.89	0.00	99.71	0.00	89.25	0.00	/workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.751751771

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.3835861371
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.4184760550
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.108888549
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.1698195232
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.2354954471
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.3119829452
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.2032011942
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.3279457863
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.2635817997
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.919327666
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.778323239
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.3509623804
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.3138775024
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.587929648
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.2679003124
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.4091884449
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.2435050820
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.2243985149
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.3750182707
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.2591917157
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.596383613
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.1479917419
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.1282212326
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.2565075940
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.3853721290
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.1731881985
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.2209034404
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.3809056640
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.896139744
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.3069761373
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.4164829689
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.2613570754
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.3517675295
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.478220431
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.318855014
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.3741077751
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.2159372962
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.1254396072
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.3934827166
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.3294846899
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.3624009320
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.3566219893
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.956273606
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.3985112372
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.402213958
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.1714654122
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.1720280047
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/workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.3148934344
/workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.917113692
/workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.1960703532
/workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.720769472
/workspace/coverage/default/4.sysrst_ctrl_edge_detect.2183408448
/workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.3293062357
/workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.4050541222
/workspace/coverage/default/4.sysrst_ctrl_pin_access_test.2872921773
/workspace/coverage/default/4.sysrst_ctrl_pin_override_test.2585544135
/workspace/coverage/default/4.sysrst_ctrl_sec_cm.3356900012
/workspace/coverage/default/4.sysrst_ctrl_smoke.1998291795
/workspace/coverage/default/4.sysrst_ctrl_stress_all.2340825867
/workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.1700064917
/workspace/coverage/default/40.sysrst_ctrl_alert_test.3945304357
/workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.1731614
/workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.933883892
/workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.2051988816
/workspace/coverage/default/40.sysrst_ctrl_edge_detect.2384111710
/workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.2893295989
/workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.1241752516
/workspace/coverage/default/40.sysrst_ctrl_pin_access_test.3727615034
/workspace/coverage/default/40.sysrst_ctrl_pin_override_test.1763555958
/workspace/coverage/default/40.sysrst_ctrl_smoke.847078187
/workspace/coverage/default/40.sysrst_ctrl_stress_all.513000934
/workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.1681008742
/workspace/coverage/default/41.sysrst_ctrl_alert_test.3852526461
/workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.1673216163
/workspace/coverage/default/41.sysrst_ctrl_combo_detect.2367350321
/workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.1527743485
/workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.223281780
/workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.4153891326
/workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.712604356
/workspace/coverage/default/41.sysrst_ctrl_pin_access_test.2310795971
/workspace/coverage/default/41.sysrst_ctrl_pin_override_test.39711519
/workspace/coverage/default/41.sysrst_ctrl_smoke.3808187819
/workspace/coverage/default/41.sysrst_ctrl_stress_all.2135480656
/workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.1086834391
/workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.982545353
/workspace/coverage/default/42.sysrst_ctrl_alert_test.2575566351
/workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.1000026398
/workspace/coverage/default/42.sysrst_ctrl_combo_detect.1058516374
/workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.3674675599
/workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.166575018
/workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.4262680811
/workspace/coverage/default/42.sysrst_ctrl_pin_access_test.3125178366
/workspace/coverage/default/42.sysrst_ctrl_pin_override_test.3934446853
/workspace/coverage/default/42.sysrst_ctrl_smoke.1121532002
/workspace/coverage/default/42.sysrst_ctrl_stress_all.2218416750
/workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.3205520303
/workspace/coverage/default/43.sysrst_ctrl_alert_test.430120200
/workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.3328844696
/workspace/coverage/default/43.sysrst_ctrl_combo_detect.170493709
/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.2657346993
/workspace/coverage/default/43.sysrst_ctrl_edge_detect.2156227084
/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.2475620971
/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.3198290298
/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.2821710985
/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.990559574
/workspace/coverage/default/43.sysrst_ctrl_smoke.1897748213
/workspace/coverage/default/43.sysrst_ctrl_stress_all.2015527878
/workspace/coverage/default/44.sysrst_ctrl_alert_test.1869117161
/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.407245385
/workspace/coverage/default/44.sysrst_ctrl_combo_detect.2180356511
/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.2511452350
/workspace/coverage/default/44.sysrst_ctrl_edge_detect.939774091
/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.1072821295
/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.4293886644
/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.1178526505
/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.3004110746
/workspace/coverage/default/44.sysrst_ctrl_smoke.1134188872
/workspace/coverage/default/44.sysrst_ctrl_stress_all.3987205344
/workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.3043388702
/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.2835625292
/workspace/coverage/default/45.sysrst_ctrl_alert_test.755182383
/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.3704201889
/workspace/coverage/default/45.sysrst_ctrl_combo_detect.177268370
/workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.75661360
/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.3334860635
/workspace/coverage/default/45.sysrst_ctrl_edge_detect.2084348698
/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.2911819829
/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.2777942974
/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.666766624
/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.1244026878
/workspace/coverage/default/45.sysrst_ctrl_smoke.3484861180
/workspace/coverage/default/45.sysrst_ctrl_stress_all.516935503
/workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.1221534499
/workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.3077457604
/workspace/coverage/default/46.sysrst_ctrl_alert_test.308668940
/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.1504300723
/workspace/coverage/default/46.sysrst_ctrl_combo_detect.4085934493
/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.2955006491
/workspace/coverage/default/46.sysrst_ctrl_edge_detect.3040772424
/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.3057248711
/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.3963345620
/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.322591102
/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.483132322
/workspace/coverage/default/46.sysrst_ctrl_smoke.373296883
/workspace/coverage/default/46.sysrst_ctrl_stress_all.1273884624
/workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.3251008710
/workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.3375343094
/workspace/coverage/default/47.sysrst_ctrl_alert_test.3743023027
/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.548502472
/workspace/coverage/default/47.sysrst_ctrl_combo_detect.657107033
/workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.4204286765
/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.1077772447
/workspace/coverage/default/47.sysrst_ctrl_edge_detect.2950403865
/workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.2685052655
/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.392797224
/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.4129427564
/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.2926925150
/workspace/coverage/default/47.sysrst_ctrl_smoke.1267751078
/workspace/coverage/default/47.sysrst_ctrl_stress_all.2755803041
/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.1279926706
/workspace/coverage/default/48.sysrst_ctrl_alert_test.2029407043
/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.2866852455
/workspace/coverage/default/48.sysrst_ctrl_combo_detect.3452162180
/workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.2153133572
/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.566704281
/workspace/coverage/default/48.sysrst_ctrl_edge_detect.946926521
/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.1106756128
/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.2033063286
/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.4001968630
/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.2349684554
/workspace/coverage/default/48.sysrst_ctrl_smoke.3534274439
/workspace/coverage/default/48.sysrst_ctrl_stress_all.1010114449
/workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.3873716710
/workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.2818752441
/workspace/coverage/default/49.sysrst_ctrl_alert_test.622873767
/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.3825967269
/workspace/coverage/default/49.sysrst_ctrl_combo_detect.345925085
/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.250901754
/workspace/coverage/default/49.sysrst_ctrl_edge_detect.3483296369
/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.4031988514
/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.2277943557
/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.2796231860
/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.102827544
/workspace/coverage/default/49.sysrst_ctrl_smoke.1175677207
/workspace/coverage/default/49.sysrst_ctrl_stress_all.3990976093
/workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.3099515552
/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.1136623143
/workspace/coverage/default/5.sysrst_ctrl_alert_test.843186733
/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.3716972942
/workspace/coverage/default/5.sysrst_ctrl_combo_detect.315823584
/workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.1865896797
/workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.1532152692
/workspace/coverage/default/5.sysrst_ctrl_edge_detect.2366089822
/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.4240295713
/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.3774542080
/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.4142384555
/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.354322296
/workspace/coverage/default/5.sysrst_ctrl_smoke.1996078532
/workspace/coverage/default/5.sysrst_ctrl_stress_all.2645178829
/workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.1189634492
/workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.3640776932
/workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.1323840271
/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.73675859
/workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.1445464801
/workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.1436855819
/workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.3142083401
/workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.1059414747
/workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.1294706634
/workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.2517104142
/workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.1227287206
/workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.1767540823
/workspace/coverage/default/6.sysrst_ctrl_alert_test.1474441719
/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.1608738955
/workspace/coverage/default/6.sysrst_ctrl_combo_detect.740703460
/workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.3334712137
/workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.3609062220
/workspace/coverage/default/6.sysrst_ctrl_edge_detect.1176358309
/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.2244880985
/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.1601304140
/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.2663197004
/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.1751574469
/workspace/coverage/default/6.sysrst_ctrl_smoke.918179097
/workspace/coverage/default/6.sysrst_ctrl_stress_all.4232101939
/workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.3668272248
/workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.2755852200
/workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.3923783480
/workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.2491875752
/workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.2588219928
/workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.4173911742
/workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.1375414684
/workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.739025370
/workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.2514019830
/workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.2772958211
/workspace/coverage/default/7.sysrst_ctrl_alert_test.1950791913
/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.3772286375
/workspace/coverage/default/7.sysrst_ctrl_combo_detect.194537520
/workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.4264287638
/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.2025811480
/workspace/coverage/default/7.sysrst_ctrl_edge_detect.327954752
/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.1584962201
/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.279368552
/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.2258355691
/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.407641063
/workspace/coverage/default/7.sysrst_ctrl_smoke.3831938562
/workspace/coverage/default/7.sysrst_ctrl_stress_all.1910152798
/workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.1529182483
/workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.3266699916
/workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.2796738394
/workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.4066664585
/workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.1274938951
/workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.2196140862
/workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.3069379894
/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.3973532927
/workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.1940647783
/workspace/coverage/default/8.sysrst_ctrl_alert_test.2572278654
/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.3391207693
/workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.2955305005
/workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.4027115348
/workspace/coverage/default/8.sysrst_ctrl_edge_detect.164034853
/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.1293879946
/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.4223315776
/workspace/coverage/default/8.sysrst_ctrl_pin_access_test.3923479730
/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.1263189411
/workspace/coverage/default/8.sysrst_ctrl_smoke.3824228554
/workspace/coverage/default/8.sysrst_ctrl_stress_all.1796226535
/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.2461955150
/workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.2450693437
/workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.2130379642
/workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.3059382280
/workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.2367584861
/workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.4284252029
/workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.2418986809
/workspace/coverage/default/9.sysrst_ctrl_alert_test.3036138482
/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.2658051159
/workspace/coverage/default/9.sysrst_ctrl_combo_detect.1085076989
/workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.155843968
/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.4094345863
/workspace/coverage/default/9.sysrst_ctrl_edge_detect.2747500264
/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.2655328791
/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.4220063406
/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.1274579854
/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.2917604545
/workspace/coverage/default/9.sysrst_ctrl_smoke.3302404537
/workspace/coverage/default/9.sysrst_ctrl_stress_all.138421334
/workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.1180305290
/workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.3115567942
/workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.2935709466
/workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.1207247921
/workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.1193805770
/workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.1940861133
/workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.1203301620
/workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.3415891502
/workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.2179424826

Total test records in report: 913

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.2332546892	Mar 19 01:03:04 PM PDT 24	Mar 19 01:03:07 PM PDT 24	6063279197 ps
T5	/workspace/coverage/default/32.sysrst_ctrl_pin_override_test.3277125411	Mar 19 01:02:40 PM PDT 24	Mar 19 01:02:48 PM PDT 24	2508908308 ps
T6	/workspace/coverage/default/39.sysrst_ctrl_smoke.1964946290	Mar 19 01:02:56 PM PDT 24	Mar 19 01:03:02 PM PDT 24	2112559881 ps
T13	/workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.1725810007	Mar 19 01:02:16 PM PDT 24	Mar 19 01:02:19 PM PDT 24	2469971601 ps
T2	/workspace/coverage/default/8.sysrst_ctrl_edge_detect.164034853	Mar 19 01:01:40 PM PDT 24	Mar 19 01:01:46 PM PDT 24	2579581289 ps
T3	/workspace/coverage/default/27.sysrst_ctrl_edge_detect.2826455864	Mar 19 01:02:35 PM PDT 24	Mar 19 01:02:39 PM PDT 24	2496254732 ps
T14	/workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.1182076263	Mar 19 01:02:27 PM PDT 24	Mar 19 01:02:30 PM PDT 24	2490657184 ps
T15	/workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.3328844696	Mar 19 01:03:05 PM PDT 24	Mar 19 01:03:09 PM PDT 24	3826168581 ps
T4	/workspace/coverage/default/43.sysrst_ctrl_edge_detect.2156227084	Mar 19 01:03:09 PM PDT 24	Mar 19 01:03:20 PM PDT 24	5316013711 ps
T16	/workspace/coverage/default/36.sysrst_ctrl_pin_override_test.3081756993	Mar 19 01:02:48 PM PDT 24	Mar 19 01:02:50 PM PDT 24	2536393862 ps
T49	/workspace/coverage/default/18.sysrst_ctrl_alert_test.1452932398	Mar 19 01:02:09 PM PDT 24	Mar 19 01:02:13 PM PDT 24	2024609284 ps
T23	/workspace/coverage/default/9.sysrst_ctrl_stress_all.138421334	Mar 19 01:01:42 PM PDT 24	Mar 19 01:01:52 PM PDT 24	9424441446 ps
T50	/workspace/coverage/default/16.sysrst_ctrl_pin_access_test.762976587	Mar 19 01:01:58 PM PDT 24	Mar 19 01:01:59 PM PDT 24	2324776421 ps
T51	/workspace/coverage/default/6.sysrst_ctrl_smoke.918179097	Mar 19 01:01:32 PM PDT 24	Mar 19 01:01:34 PM PDT 24	2125508047 ps
T52	/workspace/coverage/default/31.sysrst_ctrl_pin_access_test.759838090	Mar 19 01:02:38 PM PDT 24	Mar 19 01:02:43 PM PDT 24	2235425455 ps
T53	/workspace/coverage/default/5.sysrst_ctrl_alert_test.843186733	Mar 19 01:01:34 PM PDT 24	Mar 19 01:01:39 PM PDT 24	2019953036 ps
T54	/workspace/coverage/default/46.sysrst_ctrl_smoke.373296883	Mar 19 01:03:15 PM PDT 24	Mar 19 01:03:17 PM PDT 24	2137246413 ps
T22	/workspace/coverage/default/37.sysrst_ctrl_stress_all.4036991651	Mar 19 01:02:55 PM PDT 24	Mar 19 01:03:24 PM PDT 24	11246364001 ps
T60	/workspace/coverage/default/28.sysrst_ctrl_pin_access_test.2109632648	Mar 19 01:02:27 PM PDT 24	Mar 19 01:02:30 PM PDT 24	2104569881 ps
T7	/workspace/coverage/default/49.sysrst_ctrl_stress_all.3990976093	Mar 19 01:03:22 PM PDT 24	Mar 19 01:03:42 PM PDT 24	12699580881 ps
T8	/workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.2334976358	Mar 19 01:03:40 PM PDT 24	Mar 19 01:04:33 PM PDT 24	79842660170 ps
T9	/workspace/coverage/default/14.sysrst_ctrl_stress_all.56002562	Mar 19 01:01:59 PM PDT 24	Mar 19 01:05:19 PM PDT 24	78486564970 ps
T10	/workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.917113692	Mar 19 01:01:31 PM PDT 24	Mar 19 01:01:32 PM PDT 24	2641881441 ps
T26	/workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.4148064932	Mar 19 01:02:27 PM PDT 24	Mar 19 01:02:43 PM PDT 24	26117490009 ps
T11	/workspace/coverage/default/0.sysrst_ctrl_edge_detect.3859337042	Mar 19 01:01:31 PM PDT 24	Mar 19 01:01:40 PM PDT 24	4121493605 ps
T55	/workspace/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.22720075	Mar 19 01:02:51 PM PDT 24	Mar 19 01:02:54 PM PDT 24	4000197100 ps
T56	/workspace/coverage/default/17.sysrst_ctrl_pin_override_test.3227520667	Mar 19 01:02:01 PM PDT 24	Mar 19 01:02:09 PM PDT 24	2512138966 ps
T24	/workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.959070997	Mar 19 01:02:27 PM PDT 24	Mar 19 01:02:30 PM PDT 24	3528597395 ps
T57	/workspace/coverage/default/27.sysrst_ctrl_pin_access_test.1775616261	Mar 19 01:02:27 PM PDT 24	Mar 19 01:02:28 PM PDT 24	2210122726 ps
T25	/workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.548777702	Mar 19 01:02:38 PM PDT 24	Mar 19 01:02:39 PM PDT 24	3272518899 ps
T12	/workspace/coverage/default/35.sysrst_ctrl_edge_detect.2260034190	Mar 19 01:02:51 PM PDT 24	Mar 19 01:02:53 PM PDT 24	3919551452 ps
T32	/workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.1889043523	Mar 19 01:02:16 PM PDT 24	Mar 19 01:02:19 PM PDT 24	2520686184 ps
T212	/workspace/coverage/default/45.sysrst_ctrl_alert_test.755182383	Mar 19 01:03:16 PM PDT 24	Mar 19 01:03:19 PM PDT 24	2021375981 ps
T41	/workspace/coverage/default/17.sysrst_ctrl_combo_detect.4094781091	Mar 19 01:01:59 PM PDT 24	Mar 19 01:02:51 PM PDT 24	41743230855 ps
T33	/workspace/coverage/default/43.sysrst_ctrl_stress_all.2015527878	Mar 19 01:03:08 PM PDT 24	Mar 19 01:04:10 PM PDT 24	24980524010 ps
T27	/workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.2588219928	Mar 19 01:03:38 PM PDT 24	Mar 19 01:05:06 PM PDT 24	58593613820 ps
T42	/workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.2875363215	Mar 19 01:02:14 PM PDT 24	Mar 19 01:02:25 PM PDT 24	3746509580 ps
T59	/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.1077772447	Mar 19 01:03:28 PM PDT 24	Mar 19 01:03:37 PM PDT 24	2568509169 ps
T65	/workspace/coverage/default/2.sysrst_ctrl_in_out_inverted.4256236087	Mar 19 01:01:22 PM PDT 24	Mar 19 01:01:24 PM PDT 24	2509382930 ps
T66	/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.3774542080	Mar 19 01:01:31 PM PDT 24	Mar 19 01:01:34 PM PDT 24	2470448278 ps
T67	/workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.3150647541	Mar 19 01:01:31 PM PDT 24	Mar 19 01:01:32 PM PDT 24	2576059722 ps
T43	/workspace/coverage/default/27.sysrst_ctrl_stress_all.773585674	Mar 19 01:02:28 PM PDT 24	Mar 19 01:02:32 PM PDT 24	16112656027 ps
T68	/workspace/coverage/default/32.sysrst_ctrl_in_out_inverted.3917900305	Mar 19 01:02:41 PM PDT 24	Mar 19 01:02:43 PM PDT 24	2532248612 ps
T34	/workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.3556096723	Mar 19 01:01:58 PM PDT 24	Mar 19 01:06:41 PM PDT 24	113262682927 ps
T35	/workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.2891216403	Mar 19 01:02:03 PM PDT 24	Mar 19 01:05:59 PM PDT 24	85869089091 ps
T37	/workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.3048780134	Mar 19 01:01:44 PM PDT 24	Mar 19 01:03:01 PM PDT 24	108976935384 ps
T220	/workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.1145200186	Mar 19 01:02:07 PM PDT 24	Mar 19 01:02:15 PM PDT 24	2460449758 ps
T221	/workspace/coverage/default/14.sysrst_ctrl_pin_access_test.1029766544	Mar 19 01:01:50 PM PDT 24	Mar 19 01:01:53 PM PDT 24	2071001647 ps
T222	/workspace/coverage/default/39.sysrst_ctrl_pin_access_test.2691103192	Mar 19 01:02:59 PM PDT 24	Mar 19 01:03:01 PM PDT 24	2054725725 ps
T44	/workspace/coverage/default/16.sysrst_ctrl_combo_detect.2780261134	Mar 19 01:02:01 PM PDT 24	Mar 19 01:02:22 PM PDT 24	108850224395 ps
T223	/workspace/coverage/default/22.sysrst_ctrl_smoke.1767494916	Mar 19 01:02:21 PM PDT 24	Mar 19 01:02:24 PM PDT 24	2113916195 ps
T224	/workspace/coverage/default/42.sysrst_ctrl_alert_test.2575566351	Mar 19 01:03:07 PM PDT 24	Mar 19 01:03:14 PM PDT 24	2038691377 ps
T40	/workspace/coverage/default/3.sysrst_ctrl_edge_detect.1405396138	Mar 19 01:01:30 PM PDT 24	Mar 19 01:01:40 PM PDT 24	4473865264 ps
T225	/workspace/coverage/default/28.sysrst_ctrl_alert_test.4050177288	Mar 19 01:02:40 PM PDT 24	Mar 19 01:02:44 PM PDT 24	2026288709 ps
T20	/workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.3450878540	Mar 19 01:02:55 PM PDT 24	Mar 19 01:03:10 PM PDT 24	345328080640 ps
T126	/workspace/coverage/default/15.sysrst_ctrl_alert_test.2926127819	Mar 19 01:01:58 PM PDT 24	Mar 19 01:02:01 PM PDT 24	2014730789 ps
T127	/workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.537830729	Mar 19 01:01:21 PM PDT 24	Mar 19 01:01:25 PM PDT 24	2615911508 ps
T128	/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.2475620971	Mar 19 01:03:05 PM PDT 24	Mar 19 01:03:09 PM PDT 24	2623489611 ps
T45	/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.3825967269	Mar 19 01:03:27 PM PDT 24	Mar 19 01:03:33 PM PDT 24	3430956799 ps
T61	/workspace/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.2172036635	Mar 19 01:02:48 PM PDT 24	Mar 19 01:03:35 PM PDT 24	26908662704 ps
T129	/workspace/coverage/default/1.sysrst_ctrl_sec_cm.1005529147	Mar 19 01:01:21 PM PDT 24	Mar 19 01:03:09 PM PDT 24	42012442170 ps
T46	/workspace/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.3975031402	Mar 19 01:02:34 PM PDT 24	Mar 19 01:03:14 PM PDT 24	54923657880 ps
T62	/workspace/coverage/default/21.sysrst_ctrl_ultra_low_pwr.3840739609	Mar 19 01:02:14 PM PDT 24	Mar 19 01:16:20 PM PDT 24	2779993230273 ps
T21	/workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.3640776932	Mar 19 01:01:31 PM PDT 24	Mar 19 01:01:35 PM PDT 24	4770842311 ps
T142	/workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.1873832313	Mar 19 01:01:50 PM PDT 24	Mar 19 01:01:57 PM PDT 24	2458826793 ps
T143	/workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.84885489	Mar 19 01:01:48 PM PDT 24	Mar 19 01:01:52 PM PDT 24	2630979265 ps
T63	/workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.3239384937	Mar 19 01:02:17 PM PDT 24	Mar 19 01:03:20 PM PDT 24	2811191934003 ps
T144	/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.1072821295	Mar 19 01:03:05 PM PDT 24	Mar 19 01:03:08 PM PDT 24	2624061215 ps
T145	/workspace/coverage/default/33.sysrst_ctrl_pin_access_test.4189436572	Mar 19 01:02:43 PM PDT 24	Mar 19 01:02:50 PM PDT 24	2053154607 ps
T146	/workspace/coverage/default/22.sysrst_ctrl_pin_override_test.1385851160	Mar 19 01:02:19 PM PDT 24	Mar 19 01:02:23 PM PDT 24	2520192629 ps
T147	/workspace/coverage/default/11.sysrst_ctrl_pin_access_test.67273721	Mar 19 01:01:50 PM PDT 24	Mar 19 01:01:52 PM PDT 24	2122392911 ps
T47	/workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3068116349	Mar 19 01:01:20 PM PDT 24	Mar 19 01:01:22 PM PDT 24	2568565759 ps
T90	/workspace/coverage/default/47.sysrst_ctrl_combo_detect.657107033	Mar 19 01:03:24 PM PDT 24	Mar 19 01:03:56 PM PDT 24	126369627000 ps
T48	/workspace/coverage/default/3.sysrst_ctrl_stress_all.3448711417	Mar 19 01:01:34 PM PDT 24	Mar 19 01:02:08 PM PDT 24	11659834052 ps
T91	/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.407245385	Mar 19 01:03:10 PM PDT 24	Mar 19 01:03:16 PM PDT 24	3912127638 ps
T108	/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.1274579854	Mar 19 01:01:44 PM PDT 24	Mar 19 01:01:47 PM PDT 24	2153181616 ps
T109	/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.483132322	Mar 19 01:03:17 PM PDT 24	Mar 19 01:03:19 PM PDT 24	2523611571 ps
T64	/workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.3326688281	Mar 19 01:03:05 PM PDT 24	Mar 19 01:05:27 PM PDT 24	124200046159 ps
T110	/workspace/coverage/default/49.sysrst_ctrl_edge_detect.3483296369	Mar 19 01:03:22 PM PDT 24	Mar 19 01:03:30 PM PDT 24	3230573920 ps
T111	/workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.3251008710	Mar 19 01:03:14 PM PDT 24	Mar 19 01:03:53 PM PDT 24	14232668760 ps
T112	/workspace/coverage/default/34.sysrst_ctrl_pin_override_test.97934955	Mar 19 01:02:47 PM PDT 24	Mar 19 01:02:50 PM PDT 24	2535306791 ps
T38	/workspace/coverage/default/11.sysrst_ctrl_edge_detect.2640566545	Mar 19 01:01:48 PM PDT 24	Mar 19 01:04:35 PM PDT 24	665261824260 ps
T401	/workspace/coverage/default/37.sysrst_ctrl_alert_test.3231315460	Mar 19 01:02:55 PM PDT 24	Mar 19 01:02:56 PM PDT 24	2065724579 ps
T402	/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.3334860635	Mar 19 01:03:16 PM PDT 24	Mar 19 01:03:19 PM PDT 24	3410982699 ps
T403	/workspace/coverage/default/21.sysrst_ctrl_auto_blk_key_output.456413727	Mar 19 01:02:21 PM PDT 24	Mar 19 01:02:31 PM PDT 24	4063710848 ps
T92	/workspace/coverage/default/10.sysrst_ctrl_combo_detect.4182211214	Mar 19 01:01:45 PM PDT 24	Mar 19 01:02:04 PM PDT 24	31032930799 ps
T73	/workspace/coverage/default/29.sysrst_ctrl_ultra_low_pwr.3019758293	Mar 19 01:02:37 PM PDT 24	Mar 19 01:02:44 PM PDT 24	5261569960 ps
T404	/workspace/coverage/default/9.sysrst_ctrl_alert_test.3036138482	Mar 19 01:01:40 PM PDT 24	Mar 19 01:01:46 PM PDT 24	2010585612 ps
T387	/workspace/coverage/default/32.sysrst_ctrl_stress_all.3362212990	Mar 19 01:02:43 PM PDT 24	Mar 19 01:03:20 PM PDT 24	13209529984 ps
T398	/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.1244026878	Mar 19 01:03:15 PM PDT 24	Mar 19 01:03:23 PM PDT 24	2511836871 ps
T122	/workspace/coverage/default/21.sysrst_ctrl_combo_detect.304790975	Mar 19 01:02:20 PM PDT 24	Mar 19 01:11:34 PM PDT 24	225116587996 ps
T400	/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.3004110746	Mar 19 01:03:06 PM PDT 24	Mar 19 01:03:11 PM PDT 24	2514465999 ps
T405	/workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.1322177824	Mar 19 01:02:56 PM PDT 24	Mar 19 01:02:59 PM PDT 24	3435872605 ps
T406	/workspace/coverage/default/19.sysrst_ctrl_alert_test.3509510941	Mar 19 01:02:06 PM PDT 24	Mar 19 01:02:12 PM PDT 24	2015092928 ps
T407	/workspace/coverage/default/22.sysrst_ctrl_pin_access_test.3417671160	Mar 19 01:02:14 PM PDT 24	Mar 19 01:02:16 PM PDT 24	2235465826 ps
T36	/workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.4143398713	Mar 19 01:01:46 PM PDT 24	Mar 19 01:04:41 PM PDT 24	69031166070 ps
T395	/workspace/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.2640203742	Mar 19 01:02:48 PM PDT 24	Mar 19 01:08:31 PM PDT 24	574441593493 ps
T81	/workspace/coverage/default/41.sysrst_ctrl_edge_detect.109019556	Mar 19 01:03:04 PM PDT 24	Mar 19 01:03:08 PM PDT 24	3656359449 ps
T213	/workspace/coverage/default/42.sysrst_ctrl_pin_access_test.3125178366	Mar 19 01:03:07 PM PDT 24	Mar 19 01:03:14 PM PDT 24	2157907255 ps
T214	/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.566704281	Mar 19 01:03:24 PM PDT 24	Mar 19 01:03:44 PM PDT 24	4754064648 ps
T69	/workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.2717072440	Mar 19 01:02:50 PM PDT 24	Mar 19 01:07:23 PM PDT 24	106549601484 ps
T215	/workspace/coverage/default/17.sysrst_ctrl_smoke.1352950753	Mar 19 01:02:01 PM PDT 24	Mar 19 01:02:07 PM PDT 24	2108474532 ps
T216	/workspace/coverage/default/33.sysrst_ctrl_ultra_low_pwr.97782286	Mar 19 01:02:47 PM PDT 24	Mar 19 01:02:52 PM PDT 24	5675885037 ps
T39	/workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.1671935231	Mar 19 01:02:36 PM PDT 24	Mar 19 01:03:27 PM PDT 24	73517777740 ps
T217	/workspace/coverage/default/27.sysrst_ctrl_pin_override_test.1742809941	Mar 19 01:02:25 PM PDT 24	Mar 19 01:02:27 PM PDT 24	2526846239 ps
T218	/workspace/coverage/default/25.sysrst_ctrl_alert_test.754874772	Mar 19 01:02:31 PM PDT 24	Mar 19 01:02:36 PM PDT 24	2011388015 ps
T93	/workspace/coverage/default/33.sysrst_ctrl_combo_detect.2287916597	Mar 19 01:02:54 PM PDT 24	Mar 19 01:04:07 PM PDT 24	58122689556 ps
T70	/workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.2772958211	Mar 19 01:03:32 PM PDT 24	Mar 19 01:06:10 PM PDT 24	141204615100 ps
T408	/workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.201299168	Mar 19 01:01:23 PM PDT 24	Mar 19 01:02:17 PM PDT 24	81317932691 ps
T409	/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.4293886644	Mar 19 01:03:09 PM PDT 24	Mar 19 01:03:21 PM PDT 24	2471832403 ps
T399	/workspace/coverage/default/40.sysrst_ctrl_pin_override_test.1763555958	Mar 19 01:03:00 PM PDT 24	Mar 19 01:03:07 PM PDT 24	2513728745 ps
T410	/workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.1097168326	Mar 19 01:01:59 PM PDT 24	Mar 19 01:02:07 PM PDT 24	2608971203 ps
T411	/workspace/coverage/default/11.sysrst_ctrl_alert_test.4129624499	Mar 19 01:01:48 PM PDT 24	Mar 19 01:01:51 PM PDT 24	2046294620 ps
T412	/workspace/coverage/default/1.sysrst_ctrl_pin_access_test.601689373	Mar 19 01:01:19 PM PDT 24	Mar 19 01:01:23 PM PDT 24	2126184358 ps
T413	/workspace/coverage/default/1.sysrst_ctrl_smoke.1791790759	Mar 19 01:01:21 PM PDT 24	Mar 19 01:01:29 PM PDT 24	2110469608 ps
T196	/workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.1657317775	Mar 19 01:02:51 PM PDT 24	Mar 19 01:05:55 PM PDT 24	309637263508 ps
T414	/workspace/coverage/default/6.sysrst_ctrl_alert_test.1474441719	Mar 19 01:01:48 PM PDT 24	Mar 19 01:01:56 PM PDT 24	2011868926 ps
T415	/workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.2796656634	Mar 19 01:01:51 PM PDT 24	Mar 19 01:01:58 PM PDT 24	2614927012 ps
T416	/workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.1730976951	Mar 19 01:02:57 PM PDT 24	Mar 19 01:02:59 PM PDT 24	2483328508 ps
T417	/workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.131703239	Mar 19 01:01:34 PM PDT 24	Mar 19 01:01:41 PM PDT 24	2401316501 ps
T71	/workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.3334712137	Mar 19 01:01:42 PM PDT 24	Mar 19 01:01:56 PM PDT 24	34600098687 ps
T275	/workspace/coverage/default/30.sysrst_ctrl_combo_detect.855995954	Mar 19 01:02:39 PM PDT 24	Mar 19 01:04:35 PM PDT 24	46218465154 ps
T154	/workspace/coverage/default/5.sysrst_ctrl_edge_detect.2366089822	Mar 19 01:01:31 PM PDT 24	Mar 19 01:01:36 PM PDT 24	4408159166 ps
T86	/workspace/coverage/default/36.sysrst_ctrl_stress_all.2666163739	Mar 19 01:02:51 PM PDT 24	Mar 19 01:03:08 PM PDT 24	12042661377 ps
T202	/workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.1159088169	Mar 19 01:02:16 PM PDT 24	Mar 19 01:02:19 PM PDT 24	2470484114 ps
T203	/workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.1098611013	Mar 19 01:01:22 PM PDT 24	Mar 19 01:09:18 PM PDT 24	190732160092 ps
T204	/workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.826719813	Mar 19 01:02:38 PM PDT 24	Mar 19 01:02:41 PM PDT 24	2621243283 ps
T72	/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.3973532927	Mar 19 01:03:39 PM PDT 24	Mar 19 01:04:49 PM PDT 24	47199943442 ps
T205	/workspace/coverage/default/19.sysrst_ctrl_smoke.2482454056	Mar 19 01:02:08 PM PDT 24	Mar 19 01:02:09 PM PDT 24	2209935596 ps
T201	/workspace/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.753274138	Mar 19 01:01:22 PM PDT 24	Mar 19 01:05:41 PM PDT 24	102576689575 ps
T74	/workspace/coverage/default/19.sysrst_ctrl_stress_all.2557882489	Mar 19 01:02:09 PM PDT 24	Mar 19 01:02:45 PM PDT 24	13888428987 ps
T206	/workspace/coverage/default/12.sysrst_ctrl_combo_detect.2295608893	Mar 19 01:01:49 PM PDT 24	Mar 19 01:06:23 PM PDT 24	153577465579 ps
T207	/workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.3881553871	Mar 19 01:01:48 PM PDT 24	Mar 19 01:01:57 PM PDT 24	2443796583 ps
T289	/workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.4275290954	Mar 19 01:02:39 PM PDT 24	Mar 19 01:02:40 PM PDT 24	2661572589 ps
T178	/workspace/coverage/default/45.sysrst_ctrl_edge_detect.2084348698	Mar 19 01:03:16 PM PDT 24	Mar 19 01:03:24 PM PDT 24	3225026497 ps
T208	/workspace/coverage/default/48.sysrst_ctrl_edge_detect.946926521	Mar 19 01:03:28 PM PDT 24	Mar 19 01:03:33 PM PDT 24	3385503625 ps
T155	/workspace/coverage/default/19.sysrst_ctrl_edge_detect.3692796430	Mar 19 01:02:09 PM PDT 24	Mar 19 01:02:16 PM PDT 24	4383131172 ps
T290	/workspace/coverage/default/37.sysrst_ctrl_pin_access_test.2806941927	Mar 19 01:02:59 PM PDT 24	Mar 19 01:03:00 PM PDT 24	2093744142 ps
T291	/workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.2488569619	Mar 19 01:01:45 PM PDT 24	Mar 19 01:01:47 PM PDT 24	4191415375 ps
T271	/workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.1059414747	Mar 19 01:03:23 PM PDT 24	Mar 19 01:04:15 PM PDT 24	37842331660 ps
T75	/workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.3464361880	Mar 19 01:02:13 PM PDT 24	Mar 19 01:02:21 PM PDT 24	6974647020 ps
T134	/workspace/coverage/default/36.sysrst_ctrl_pin_access_test.3145238905	Mar 19 01:02:50 PM PDT 24	Mar 19 01:02:56 PM PDT 24	2120046459 ps
T135	/workspace/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.980454263	Mar 19 01:01:52 PM PDT 24	Mar 19 01:01:54 PM PDT 24	2880528560 ps
T136	/workspace/coverage/default/46.sysrst_ctrl_stress_all.1273884624	Mar 19 01:03:16 PM PDT 24	Mar 19 01:03:22 PM PDT 24	9202081492 ps
T94	/workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.3367177478	Mar 19 01:03:22 PM PDT 24	Mar 19 01:05:45 PM PDT 24	80600994003 ps
T95	/workspace/coverage/default/36.sysrst_ctrl_combo_detect.588970218	Mar 19 01:02:47 PM PDT 24	Mar 19 01:05:48 PM PDT 24	141606789245 ps
T137	/workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.4032112972	Mar 19 01:02:55 PM PDT 24	Mar 19 01:02:58 PM PDT 24	2493130412 ps
T138	/workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.462568692	Mar 19 01:02:40 PM PDT 24	Mar 19 01:02:50 PM PDT 24	3247356795 ps
T139	/workspace/coverage/default/31.sysrst_ctrl_smoke.2704469095	Mar 19 01:02:40 PM PDT 24	Mar 19 01:02:46 PM PDT 24	2111404507 ps
T76	/workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.3115567942	Mar 19 01:01:46 PM PDT 24	Mar 19 01:01:55 PM PDT 24	10226585155 ps
T312	/workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.3521395624	Mar 19 01:02:15 PM PDT 24	Mar 19 01:02:24 PM PDT 24	3403111765 ps
T77	/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.1136623143	Mar 19 01:03:24 PM PDT 24	Mar 19 01:03:36 PM PDT 24	5654436425 ps
T418	/workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.2742226621	Mar 19 01:02:56 PM PDT 24	Mar 19 01:03:03 PM PDT 24	2478090310 ps
T272	/workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.1940861133	Mar 19 01:03:41 PM PDT 24	Mar 19 01:06:26 PM PDT 24	58408360678 ps
T397	/workspace/coverage/default/28.sysrst_ctrl_ultra_low_pwr.4216950215	Mar 19 01:02:42 PM PDT 24	Mar 19 01:04:22 PM PDT 24	1433529653574 ps
T284	/workspace/coverage/default/23.sysrst_ctrl_stress_all.1248259455	Mar 19 01:02:15 PM PDT 24	Mar 19 01:16:20 PM PDT 24	347583326480 ps
T419	/workspace/coverage/default/20.sysrst_ctrl_smoke.199467173	Mar 19 01:02:09 PM PDT 24	Mar 19 01:02:11 PM PDT 24	2151689622 ps
T353	/workspace/coverage/default/29.sysrst_ctrl_combo_detect.2076145261	Mar 19 01:02:40 PM PDT 24	Mar 19 01:03:41 PM PDT 24	93612200968 ps
T96	/workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.1940647783	Mar 19 01:03:45 PM PDT 24	Mar 19 01:06:07 PM PDT 24	57639771939 ps
T420	/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.2821710985	Mar 19 01:03:11 PM PDT 24	Mar 19 01:03:18 PM PDT 24	2174642569 ps
T82	/workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.3418633280	Mar 19 01:02:59 PM PDT 24	Mar 19 01:04:48 PM PDT 24	41307541167 ps
T78	/workspace/coverage/default/0.sysrst_ctrl_feature_disable.3081600762	Mar 19 01:01:25 PM PDT 24	Mar 19 01:01:35 PM PDT 24	29991825072 ps
T197	/workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.1222966881	Mar 19 01:02:38 PM PDT 24	Mar 19 01:02:39 PM PDT 24	2539425239 ps
T156	/workspace/coverage/default/36.sysrst_ctrl_edge_detect.2518087127	Mar 19 01:02:51 PM PDT 24	Mar 19 01:02:54 PM PDT 24	3409651257 ps
T173	/workspace/coverage/default/4.sysrst_ctrl_edge_detect.2183408448	Mar 19 01:01:32 PM PDT 24	Mar 19 01:01:43 PM PDT 24	3371378964 ps
T198	/workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.4153656161	Mar 19 01:01:40 PM PDT 24	Mar 19 01:01:48 PM PDT 24	4959711044 ps
T157	/workspace/coverage/default/38.sysrst_ctrl_edge_detect.1130245347	Mar 19 01:02:56 PM PDT 24	Mar 19 01:03:06 PM PDT 24	4696269904 ps
T199	/workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.1568758616	Mar 19 01:01:32 PM PDT 24	Mar 19 01:01:45 PM PDT 24	4058699538 ps
T200	/workspace/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.3962696219	Mar 19 01:02:16 PM PDT 24	Mar 19 01:02:19 PM PDT 24	3817325507 ps
T123	/workspace/coverage/default/7.sysrst_ctrl_stress_all.1910152798	Mar 19 01:01:41 PM PDT 24	Mar 19 01:02:05 PM PDT 24	10900843781 ps
T285	/workspace/coverage/default/25.sysrst_ctrl_combo_detect.4100236305	Mar 19 01:02:26 PM PDT 24	Mar 19 01:08:55 PM PDT 24	164607748156 ps
T421	/workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.3603380295	Mar 19 01:02:28 PM PDT 24	Mar 19 01:02:30 PM PDT 24	2626735714 ps
T316	/workspace/coverage/default/15.sysrst_ctrl_pin_override_test.1828622175	Mar 19 01:02:01 PM PDT 24	Mar 19 01:02:03 PM PDT 24	2542635027 ps
T422	/workspace/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.1445698697	Mar 19 01:02:39 PM PDT 24	Mar 19 01:02:47 PM PDT 24	4651074305 ps
T158	/workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.2906507157	Mar 19 01:01:48 PM PDT 24	Mar 19 01:03:08 PM PDT 24	117208590783 ps
T226	/workspace/coverage/default/26.sysrst_ctrl_pin_override_test.3021185959	Mar 19 01:02:27 PM PDT 24	Mar 19 01:02:29 PM PDT 24	2555633481 ps
T227	/workspace/coverage/default/1.sysrst_ctrl_edge_detect.105323738	Mar 19 01:01:22 PM PDT 24	Mar 19 01:01:24 PM PDT 24	2445261001 ps
T228	/workspace/coverage/default/47.sysrst_ctrl_alert_test.3743023027	Mar 19 01:03:23 PM PDT 24	Mar 19 01:03:29 PM PDT 24	2027690500 ps
T85	/workspace/coverage/default/34.sysrst_ctrl_stress_all.1556500944	Mar 19 01:02:48 PM PDT 24	Mar 19 01:04:17 PM PDT 24	147423756443 ps
T229	/workspace/coverage/default/38.sysrst_ctrl_alert_test.261093413	Mar 19 01:02:57 PM PDT 24	Mar 19 01:03:00 PM PDT 24	2022551852 ps
T219	/workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.2995445679	Mar 19 01:02:07 PM PDT 24	Mar 19 01:02:39 PM PDT 24	46024911746 ps
T230	/workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.74053914	Mar 19 01:02:02 PM PDT 24	Mar 19 01:02:07 PM PDT 24	1023597298381 ps
T231	/workspace/coverage/default/35.sysrst_ctrl_smoke.175574014	Mar 19 01:02:56 PM PDT 24	Mar 19 01:02:58 PM PDT 24	2133679424 ps
T232	/workspace/coverage/default/24.sysrst_ctrl_combo_detect.2013524092	Mar 19 01:02:23 PM PDT 24	Mar 19 01:07:17 PM PDT 24	118941872843 ps
T153	/workspace/coverage/default/38.sysrst_ctrl_stress_all.3866855722	Mar 19 01:02:59 PM PDT 24	Mar 19 01:04:32 PM PDT 24	155616259239 ps
T423	/workspace/coverage/default/25.sysrst_ctrl_pin_override_test.1655382610	Mar 19 01:02:16 PM PDT 24	Mar 19 01:02:17 PM PDT 24	2534948912 ps
T234	/workspace/coverage/default/33.sysrst_ctrl_edge_detect.3978610412	Mar 19 01:02:48 PM PDT 24	Mar 19 01:02:50 PM PDT 24	3762183839 ps
T279	/workspace/coverage/default/24.sysrst_ctrl_stress_all.3694381297	Mar 19 01:02:17 PM PDT 24	Mar 19 01:02:36 PM PDT 24	87079207374 ps
T424	/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.2657346993	Mar 19 01:03:08 PM PDT 24	Mar 19 01:03:16 PM PDT 24	3741018215 ps
T97	/workspace/coverage/default/8.sysrst_ctrl_combo_detect.1912195752	Mar 19 01:01:42 PM PDT 24	Mar 19 01:03:05 PM PDT 24	40968676716 ps
T317	/workspace/coverage/default/29.sysrst_ctrl_pin_override_test.3220455077	Mar 19 01:02:43 PM PDT 24	Mar 19 01:02:50 PM PDT 24	2513774906 ps
T425	/workspace/coverage/default/14.sysrst_ctrl_smoke.775995296	Mar 19 01:01:48 PM PDT 24	Mar 19 01:01:57 PM PDT 24	2112061571 ps
T426	/workspace/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.4126778016	Mar 19 01:01:22 PM PDT 24	Mar 19 01:01:31 PM PDT 24	3091957770 ps
T427	/workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.3674675599	Mar 19 01:03:08 PM PDT 24	Mar 19 01:03:17 PM PDT 24	2885190984 ps
T428	/workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.1992357020	Mar 19 01:01:58 PM PDT 24	Mar 19 01:02:03 PM PDT 24	4151928816 ps
T269	/workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.2935709466	Mar 19 01:03:58 PM PDT 24	Mar 19 01:05:43 PM PDT 24	40333185328 ps
T276	/workspace/coverage/default/23.sysrst_ctrl_combo_detect.4138266768	Mar 19 01:02:21 PM PDT 24	Mar 19 01:02:31 PM PDT 24	29028752103 ps
T429	/workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.2893295989	Mar 19 01:02:56 PM PDT 24	Mar 19 01:02:59 PM PDT 24	2628346875 ps
T286	/workspace/coverage/default/9.sysrst_ctrl_combo_detect.1085076989	Mar 19 01:01:42 PM PDT 24	Mar 19 01:04:09 PM PDT 24	117687706558 ps
T430	/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.2511452350	Mar 19 01:03:10 PM PDT 24	Mar 19 01:34:32 PM PDT 24	1364063870493 ps
T431	/workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.1241752516	Mar 19 01:02:59 PM PDT 24	Mar 19 01:03:04 PM PDT 24	2459721594 ps
T432	/workspace/coverage/default/23.sysrst_ctrl_smoke.3276095865	Mar 19 01:02:20 PM PDT 24	Mar 19 01:02:26 PM PDT 24	2113957464 ps
T433	/workspace/coverage/default/41.sysrst_ctrl_alert_test.3852526461	Mar 19 01:03:11 PM PDT 24	Mar 19 01:03:16 PM PDT 24	2038317823 ps
T245	/workspace/coverage/default/48.sysrst_ctrl_stress_all.1010114449	Mar 19 01:03:24 PM PDT 24	Mar 19 01:03:40 PM PDT 24	14675240858 ps
T434	/workspace/coverage/default/34.sysrst_ctrl_smoke.4075113480	Mar 19 01:02:46 PM PDT 24	Mar 19 01:02:49 PM PDT 24	2115745150 ps
T267	/workspace/coverage/default/22.sysrst_ctrl_edge_detect.136674082	Mar 19 01:02:20 PM PDT 24	Mar 19 01:02:21 PM PDT 24	3202237143 ps
T435	/workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.987697246	Mar 19 01:02:06 PM PDT 24	Mar 19 01:02:09 PM PDT 24	2473736253 ps
T436	/workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.3277690406	Mar 19 01:01:42 PM PDT 24	Mar 19 01:01:51 PM PDT 24	3224737047 ps
T437	/workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.4027115348	Mar 19 01:01:42 PM PDT 24	Mar 19 01:01:56 PM PDT 24	4474263442 ps
T174	/workspace/coverage/default/17.sysrst_ctrl_edge_detect.2660443812	Mar 19 01:02:05 PM PDT 24	Mar 19 01:02:13 PM PDT 24	4484125681 ps
T438	/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.2244880985	Mar 19 01:01:33 PM PDT 24	Mar 19 01:01:36 PM PDT 24	2628048996 ps
T313	/workspace/coverage/default/26.sysrst_ctrl_stress_all.1491236403	Mar 19 01:02:26 PM PDT 24	Mar 19 01:02:57 PM PDT 24	11931456133 ps
T439	/workspace/coverage/default/38.sysrst_ctrl_pin_access_test.1219464758	Mar 19 01:02:57 PM PDT 24	Mar 19 01:02:59 PM PDT 24	2159766216 ps
T247	/workspace/coverage/default/20.sysrst_ctrl_edge_detect.4101328609	Mar 19 01:02:07 PM PDT 24	Mar 19 01:02:10 PM PDT 24	2349555892 ps
T83	/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.73675859	Mar 19 01:03:25 PM PDT 24	Mar 19 01:04:18 PM PDT 24	52366896896 ps
T440	/workspace/coverage/default/23.sysrst_ctrl_pin_override_test.928992099	Mar 19 01:02:20 PM PDT 24	Mar 19 01:02:22 PM PDT 24	2526789847 ps
T441	/workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.712604356	Mar 19 01:03:07 PM PDT 24	Mar 19 01:03:15 PM PDT 24	2456796094 ps
T355	/workspace/coverage/default/2.sysrst_ctrl_stress_all.3097454277	Mar 19 01:01:31 PM PDT 24	Mar 19 01:06:56 PM PDT 24	126035629625 ps
T442	/workspace/coverage/default/17.sysrst_ctrl_ultra_low_pwr.1655843122	Mar 19 01:02:00 PM PDT 24	Mar 19 01:02:04 PM PDT 24	5034984693 ps
T366	/workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.4202784124	Mar 19 01:03:44 PM PDT 24	Mar 19 01:11:16 PM PDT 24	161114042012 ps
T443	/workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.1608391100	Mar 19 01:02:38 PM PDT 24	Mar 19 01:02:40 PM PDT 24	2627763765 ps
T444	/workspace/coverage/default/19.sysrst_ctrl_pin_access_test.1231755849	Mar 19 01:02:11 PM PDT 24	Mar 19 01:02:13 PM PDT 24	2088379590 ps
T445	/workspace/coverage/default/44.sysrst_ctrl_smoke.1134188872	Mar 19 01:03:08 PM PDT 24	Mar 19 01:03:16 PM PDT 24	2125871695 ps
T446	/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.4142384555	Mar 19 01:01:30 PM PDT 24	Mar 19 01:01:37 PM PDT 24	2215746796 ps
T124	/workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.1181897035	Mar 19 01:02:57 PM PDT 24	Mar 19 01:02:59 PM PDT 24	4342223281 ps
T447	/workspace/coverage/default/13.sysrst_ctrl_smoke.3834875091	Mar 19 01:01:49 PM PDT 24	Mar 19 01:01:56 PM PDT 24	2113145950 ps
T448	/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.3704201889	Mar 19 01:03:15 PM PDT 24	Mar 19 01:03:25 PM PDT 24	3274980160 ps
T449	/workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.3409579922	Mar 19 01:02:48 PM PDT 24	Mar 19 01:02:50 PM PDT 24	2513536110 ps
T98	/workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.2783092880	Mar 19 01:02:23 PM PDT 24	Mar 19 01:02:50 PM PDT 24	41213016858 ps
T450	/workspace/coverage/default/44.sysrst_ctrl_combo_detect.2180356511	Mar 19 01:03:08 PM PDT 24	Mar 19 01:08:54 PM PDT 24	124500024759 ps
T451	/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.2835625292	Mar 19 01:03:10 PM PDT 24	Mar 19 01:03:16 PM PDT 24	2573419562 ps
T452	/workspace/coverage/default/17.sysrst_ctrl_alert_test.551587462	Mar 19 01:01:58 PM PDT 24	Mar 19 01:02:00 PM PDT 24	2048728181 ps
T453	/workspace/coverage/default/1.sysrst_ctrl_alert_test.1116517794	Mar 19 01:01:24 PM PDT 24	Mar 19 01:01:26 PM PDT 24	2023334534 ps
T454	/workspace/coverage/default/28.sysrst_ctrl_pin_override_test.268675025	Mar 19 01:02:36 PM PDT 24	Mar 19 01:02:39 PM PDT 24	2536484036 ps
T368	/workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.2288518843	Mar 19 01:02:09 PM PDT 24	Mar 19 01:03:02 PM PDT 24	76040553239 ps
T375	/workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.1436855819	Mar 19 01:03:25 PM PDT 24	Mar 19 01:04:41 PM PDT 24	52576910226 ps
T99	/workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.1445464801	Mar 19 01:03:22 PM PDT 24	Mar 19 01:03:36 PM PDT 24	26786490179 ps
T455	/workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.4138538294	Mar 19 01:01:52 PM PDT 24	Mar 19 01:01:54 PM PDT 24	2503510958 ps
T456	/workspace/coverage/default/43.sysrst_ctrl_smoke.1897748213	Mar 19 01:03:06 PM PDT 24	Mar 19 01:03:13 PM PDT 24	2108363898 ps
T457	/workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.535322676	Mar 19 01:01:58 PM PDT 24	Mar 19 01:02:01 PM PDT 24	3837450903 ps
T84	/workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.751751771	Mar 19 01:02:50 PM PDT 24	Mar 19 01:03:19 PM PDT 24	50950842126 ps
T458	/workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.1001987587	Mar 19 01:01:51 PM PDT 24	Mar 19 01:01:54 PM PDT 24	2631426447 ps
T459	/workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.1291160051	Mar 19 01:02:08 PM PDT 24	Mar 19 01:02:16 PM PDT 24	2612781671 ps
T233	/workspace/coverage/default/28.sysrst_ctrl_edge_detect.3198164021	Mar 19 01:02:39 PM PDT 24	Mar 19 01:02:41 PM PDT 24	3330283299 ps
T460	/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.990559574	Mar 19 01:03:08 PM PDT 24	Mar 19 01:03:17 PM PDT 24	2536344132 ps
T461	/workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.3335571749	Mar 19 01:02:07 PM PDT 24	Mar 19 01:02:09 PM PDT 24	2630888296 ps
T318	/workspace/coverage/default/37.sysrst_ctrl_pin_override_test.2507118137	Mar 19 01:03:01 PM PDT 24	Mar 19 01:03:08 PM PDT 24	2511482426 ps
T462	/workspace/coverage/default/24.sysrst_ctrl_pin_override_test.2553696315	Mar 19 01:02:17 PM PDT 24	Mar 19 01:02:24 PM PDT 24	2509533642 ps
T188	/workspace/coverage/default/25.sysrst_ctrl_edge_detect.116295169	Mar 19 01:02:24 PM PDT 24	Mar 19 01:02:26 PM PDT 24	2909608995 ps
T270	/workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.2514019830	Mar 19 01:03:37 PM PDT 24	Mar 19 01:04:13 PM PDT 24	23836789690 ps