Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

927

1

T5

9

T16

10

T56

8

auto[1]

895

1

T5

11

T16

10

T56

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

435

1

T5

4

T16

3

T56

5

from_0to1

439

1

T5

4

T16

3

T56

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

904

1

T5

11

T16

12

T56

8

auto[1]

918

1

T5

9

T16

8

T56

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

917

1

T5

15

T16

8

T56

12

auto[1]

905

1

T5

5

T16

12

T56

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

64

1

T5

1

T16

1

T35

1

auto[0]

from_1to0

auto[0]

auto[1]

55

1

T35

1

T61

2

T109

1

auto[0]

from_1to0

auto[1]

auto[0]

59

1

T56

1

T61

3

T146

1

auto[0]

from_1to0

auto[1]

auto[1]

58

1

T56

2

T61

2

T146

1

auto[0]

from_0to1

auto[0]

auto[0]

51

1

T5

2

T56

1

T61

3

auto[0]

from_0to1

auto[0]

auto[1]

61

1

T56

2

T61

5

T109

1

auto[0]

from_0to1

auto[1]

auto[0]

55

1

T5

1

T37

1

T61

1

auto[0]

from_0to1

auto[1]

auto[1]

58

1

T5

1

T16

1

T35

1

auto[1]

from_1to0

auto[0]

auto[0]

49

1

T5

1

T35

1

T37

1

auto[1]

from_1to0

auto[0]

auto[1]

41

1

T37

1

T61

1

T109

1

auto[1]

from_1to0

auto[1]

auto[0]

61

1

T5

2

T16

1

T56

2

auto[1]

from_1to0

auto[1]

auto[1]

48

1

T16

1

T146

2

T112

1

auto[1]

from_0to1

auto[0]

auto[0]

54

1

T16

2

T61

1

T146

1

auto[1]

from_0to1

auto[0]

auto[1]

59

1

T56

1

T35

1

T37

1

auto[1]

from_0to1

auto[1]

auto[0]

54

1

T37

2

T61

2

T109

1

auto[1]

from_0to1

auto[1]

auto[1]

47

1

T56

1

T35

2

T146

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

893

1

T5

10

T16

11

T56

10

auto[1]

929

1

T5

10

T16

9

T56

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

434

1

T5

4

T16

6

T56

2

from_0to1

432

1

T5

4

T16

5

T56

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

878

1

T5

9

T16

10

T56

11

auto[1]

944

1

T5

11

T16

10

T56

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

896

1

T5

9

T16

11

T56

11

auto[1]

926

1

T5

11

T16

9

T56

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

50

1

T5

2

T35

1

T37

2

auto[0]

from_1to0

auto[0]

auto[1]

64

1

T16

1

T111

3

T112

2

auto[0]

from_1to0

auto[1]

auto[0]

45

1

T61

2

T146

1

T109

2

auto[0]

from_1to0

auto[1]

auto[1]

44

1

T16

1

T37

2

T146

1

auto[0]

from_0to1

auto[0]

auto[0]

53

1

T16

1

T56

2

T37

1

auto[0]

from_0to1

auto[0]

auto[1]

51

1

T56

1

T37

2

T61

1

auto[0]

from_0to1

auto[1]

auto[0]

50

1

T16

1

T35

1

T61

1

auto[0]

from_0to1

auto[1]

auto[1]

52

1

T5

1

T16

1

T61

3

auto[1]

from_1to0

auto[0]

auto[0]

55

1

T5

1

T16

1

T61

3

auto[1]

from_1to0

auto[0]

auto[1]

46

1

T16

1

T56

1

T61

2

auto[1]

from_1to0

auto[1]

auto[0]

68

1

T5

1

T16

1

T56

1

auto[1]

from_1to0

auto[1]

auto[1]

62

1

T16

1

T37

1

T61

1

auto[1]

from_0to1

auto[0]

auto[0]

59

1

T109

1

T112

2

T398

1

auto[1]

from_0to1

auto[0]

auto[1]

50

1

T5

1

T16

2

T146

1

auto[1]

from_0to1

auto[1]

auto[0]

60

1

T146

1

T109

1

T111

1

auto[1]

from_0to1

auto[1]

auto[1]

57

1

T5

2

T35

1

T37

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

881

1

T5

12

T16

13

T56

9

auto[1]

941

1

T5

8

T16

7

T56

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

439

1

T5

3

T16

7

T56

5

from_0to1

434

1

T5

3

T16

6

T56

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

887

1

T5

8

T16

12

T56

8

auto[1]

935

1

T5

12

T16

8

T56

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

895

1

T5

9

T16

9

T56

10

auto[1]

927

1

T5

11

T16

11

T56

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

36

1

T35

1

T61

2

T112

1

auto[0]

from_1to0

auto[0]

auto[1]

49

1

T16

3

T35

1

T37

2

auto[0]

from_1to0

auto[1]

auto[0]

74

1

T5

1

T16

2

T56

1

auto[0]

from_1to0

auto[1]

auto[1]

46

1

T5

2

T16

1

T56

1

auto[0]

from_0to1

auto[0]

auto[0]

60

1

T16

1

T35

1

T37

1

auto[0]

from_0to1

auto[0]

auto[1]

57

1

T16

1

T37

1

T61

3

auto[0]

from_0to1

auto[1]

auto[0]

45

1

T5

1

T56

1

T61

2

auto[0]

from_0to1

auto[1]

auto[1]

51

1

T16

2

T35

2

T37

2

auto[1]

from_1to0

auto[0]

auto[0]

48

1

T16

1

T61

1

T109

1

auto[1]

from_1to0

auto[0]

auto[1]

74

1

T37

1

T61

1

T146

2

auto[1]

from_1to0

auto[1]

auto[0]

53

1

T61

1

T146

1

T109

1

auto[1]

from_1to0

auto[1]

auto[1]

59

1

T56

3

T35

1

T61

1

auto[1]

from_0to1

auto[0]

auto[0]

44

1

T16

1

T37

1

T217

1

auto[1]

from_0to1

auto[0]

auto[1]

48

1

T5

1

T16

1

T56

2

auto[1]

from_0to1

auto[1]

auto[0]

66

1

T5

1

T56

2

T111

2

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T37

2

T61

4

T109

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

908

1

T5

11

T16

13

T56

11

auto[1]

914

1

T5

9

T16

7

T56

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

456

1

T5

5

T16

5

T56

6

from_0to1

444

1

T5

4

T16

6

T56

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

927

1

T5

7

T16

6

T56

9

auto[1]

895

1

T5

13

T16

14

T56

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

911

1

T5

11

T16

12

T56

8

auto[1]

911

1

T5

9

T16

8

T56

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

49

1

T5

1

T61

1

T146

1

auto[0]

from_1to0

auto[0]

auto[1]

60

1

T5

1

T16

1

T37

1

auto[0]

from_1to0

auto[1]

auto[0]

61

1

T16

2

T56

1

T35

1

auto[0]

from_1to0

auto[1]

auto[1]

58

1

T5

1

T16

1

T35

1

auto[0]

from_0to1

auto[0]

auto[0]

59

1

T16

1

T56

1

T37

1

auto[0]

from_0to1

auto[0]

auto[1]

55

1

T5

1

T16

1

T56

1

auto[0]

from_0to1

auto[1]

auto[0]

49

1

T16

1

T56

1

T61

1

auto[0]

from_0to1

auto[1]

auto[1]

58

1

T5

1

T16

1

T56

2

auto[1]

from_1to0

auto[0]

auto[0]

54

1

T56

1

T37

2

T61

1

auto[1]

from_1to0

auto[0]

auto[1]

63

1

T16

1

T56

2

T35

2

auto[1]

from_1to0

auto[1]

auto[0]

58

1

T5

2

T56

1

T37

1

auto[1]

from_1to0

auto[1]

auto[1]

53

1

T56

1

T399

1

T196

1

auto[1]

from_0to1

auto[0]

auto[0]

55

1

T61

1

T146

1

T112

1

auto[1]

from_0to1

auto[0]

auto[1]

72

1

T35

1

T37

1

T61

2

auto[1]

from_0to1

auto[1]

auto[0]

49

1

T5

1

T16

1

T37

2

auto[1]

from_0to1

auto[1]

auto[1]

47

1

T5

1

T16

1

T35

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

919

1

T5

9

T16

11

T56

9

auto[1]

903

1

T5

11

T16

9

T56

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

429

1

T5

7

T16

4

T56

6

from_0to1

437

1

T5

6

T16

4

T56

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

896

1

T5

8

T16

7

T56

7

auto[1]

926

1

T5

12

T16

13

T56

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

938

1

T5

9

T16

6

T56

10

auto[1]

884

1

T5

11

T16

14

T56

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

56

1

T37

2

T61

2

T146

2

auto[0]

from_1to0

auto[0]

auto[1]

51

1

T5

1

T35

2

T61

1

auto[0]

from_1to0

auto[1]

auto[0]

77

1

T16

2

T35

1

T61

1

auto[0]

from_1to0

auto[1]

auto[1]

47

1

T16

1

T56

1

T61

1

auto[0]

from_0to1

auto[0]

auto[0]

59

1

T56

1

T35

2

T37

2

auto[0]

from_0to1

auto[0]

auto[1]

61

1

T5

1

T16

1

T56

1

auto[0]

from_0to1

auto[1]

auto[0]

45

1

T5

1

T56

2

T61

3

auto[0]

from_0to1

auto[1]

auto[1]

54

1

T5

1

T37

2

T109

1

auto[1]

from_1to0

auto[0]

auto[0]

46

1

T5

1

T56

3

T35

2

auto[1]

from_1to0

auto[0]

auto[1]

47

1

T5

3

T16

1

T35

1

auto[1]

from_1to0

auto[1]

auto[0]

51

1

T5

1

T56

1

T37

1

auto[1]

from_1to0

auto[1]

auto[1]

54

1

T5

1

T56

1

T61

1

auto[1]

from_0to1

auto[0]

auto[0]

55

1

T16

1

T35

1

T37

1

auto[1]

from_0to1

auto[0]

auto[1]

60

1

T35

1

T111

2

T398

1

auto[1]

from_0to1

auto[1]

auto[0]

51

1

T5

1

T16

1

T56

1

auto[1]

from_0to1

auto[1]

auto[1]

52

1

T5

2

T16

1

T35

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

929

1

T5

12

T16

7

T56

11

auto[1]

893

1

T5

8

T16

13

T56

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

432

1

T5

5

T16

6

T56

4

from_0to1

430

1

T5

5

T16

6

T56

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

958

1

T5

9

T16

10

T56

11

auto[1]

864

1

T5

11

T16

10

T56

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

918

1

T5

9

T16

10

T56

11

auto[1]

904

1

T5

11

T16

10

T56

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

56

1

T5

1

T35

2

T61

5

auto[0]

from_1to0

auto[0]

auto[1]

59

1

T56

1

T37

1

T146

2

auto[0]

from_1to0

auto[1]

auto[0]

45

1

T5

1

T16

1

T37

1

auto[0]

from_1to0

auto[1]

auto[1]

58

1

T5

1

T56

1

T146

1

auto[0]

from_0to1

auto[0]

auto[0]

59

1

T5

1

T61

2

T146

1

auto[0]

from_0to1

auto[0]

auto[1]

60

1

T5

2

T35

1

T61

5

auto[0]

from_0to1

auto[1]

auto[0]

55

1

T16

1

T56

2

T35

1

auto[0]

from_0to1

auto[1]

auto[1]

50

1

T5

1

T16

1

T56

1

auto[1]

from_1to0

auto[0]

auto[0]

51

1

T16

2

T37

1

T61

3

auto[1]

from_1to0

auto[0]

auto[1]

57

1

T5

1

T16

1

T56

1

auto[1]

from_1to0

auto[1]

auto[0]

57

1

T61

3

T109

1

T111

2

auto[1]

from_1to0

auto[1]

auto[1]

49

1

T5

1

T16

2

T56

1

auto[1]

from_0to1

auto[0]

auto[0]

52

1

T16

1

T35

3

T37

1

auto[1]

from_0to1

auto[0]

auto[1]

52

1

T5

1

T16

1

T56

1

auto[1]

from_0to1

auto[1]

auto[0]

48

1

T16

1

T35

1

T61

1

auto[1]

from_0to1

auto[1]

auto[1]

54

1

T16

1

T37

1

T61

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

890

1

T5

9

T16

8

T56

9

auto[1]

932

1

T5

11

T16

12

T56

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

435

1

T5

5

T16

5

T56

4

from_0to1

440

1

T5

4

T16

5

T56

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

903

1

T5

8

T16

9

T56

8

auto[1]

919

1

T5

12

T16

11

T56

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

897

1

T5

10

T16

14

T56

11

auto[1]

925

1

T5

10

T16

6

T56

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

47

1

T56

1

T61

1

T146

1

auto[0]

from_1to0

auto[0]

auto[1]

55

1

T16

1

T61

1

T111

1

auto[0]

from_1to0

auto[1]

auto[0]

39

1

T16

1

T56

1

T146

1

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T5

1

T16

1

T35

1

auto[0]

from_0to1

auto[0]

auto[0]

51

1

T5

1

T16

1

T35

1

auto[0]

from_0to1

auto[0]

auto[1]

55

1

T56

1

T37

1

T61

3

auto[0]

from_0to1

auto[1]

auto[0]

59

1

T16

1

T37

1

T61

1

auto[0]

from_0to1

auto[1]

auto[1]

51

1

T5

1

T61

1

T146

2

auto[1]

from_1to0

auto[0]

auto[0]

67

1

T5

1

T16

1

T35

1

auto[1]

from_1to0

auto[0]

auto[1]

50

1

T5

1

T35

1

T37

3

auto[1]

from_1to0

auto[1]

auto[0]

46

1

T5

1

T16

1

T56

1

auto[1]

from_1to0

auto[1]

auto[1]

67

1

T5

1

T56

1

T61

3

auto[1]

from_0to1

auto[0]

auto[0]

60

1

T16

1

T56

1

T35

1

auto[1]

from_0to1

auto[0]

auto[1]

49

1

T5

1

T16

2

T56

1

auto[1]

from_0to1

auto[1]

auto[0]

58

1

T35

2

T61

1

T109

1

auto[1]

from_0to1

auto[1]

auto[1]

57

1

T5

1

T37

3

T61

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

917

1

T5

12

T16

8

T56

9

auto[1]

905

1

T5

8

T16

12

T56

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

447

1

T5

6

T16

5

T56

4

from_0to1

443

1

T5

6

T16

5

T56

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

913

1

T5

7

T16

10

T56

13

auto[1]

909

1

T5

13

T16

10

T56

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

916

1

T5

10

T16

13

T56

10

auto[1]

906

1

T5

10

T16

7

T56

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

45

1

T16

2

T56

1

T35

1

auto[0]

from_1to0

auto[0]

auto[1]

62

1

T5

3

T146

2

T109

1

auto[0]

from_1to0

auto[1]

auto[0]

56

1

T35

1

T61

3

T146

1

auto[0]

from_1to0

auto[1]

auto[1]

57

1

T16

1

T37

1

T146

1

auto[0]

from_0to1

auto[0]

auto[0]

72

1

T5

1

T16

1

T56

1

auto[0]

from_0to1

auto[0]

auto[1]

65

1

T5

1

T109

1

T398

2

auto[0]

from_0to1

auto[1]

auto[0]

50

1

T5

1

T16

1

T56

1

auto[0]

from_0to1

auto[1]

auto[1]

45

1

T5

1

T37

1

T146

1

auto[1]

from_1to0

auto[0]

auto[0]

54

1

T16

1

T61

4

T112

1

auto[1]

from_1to0

auto[0]

auto[1]

59

1

T5

1

T16

1

T56

2

auto[1]

from_1to0

auto[1]

auto[0]

71

1

T5

2

T56

1

T37

1

auto[1]

from_1to0

auto[1]

auto[1]

43

1

T35

1

T109

2

T400

1

auto[1]

from_0to1

auto[0]

auto[0]

60

1

T5

1

T16

1

T56

1

auto[1]

from_0to1

auto[0]

auto[1]

45

1

T56

1

T35

2

T61

1

auto[1]

from_0to1

auto[1]

auto[0]

57

1

T5

1

T16

1

T146

1

auto[1]

from_0to1

auto[1]

auto[1]

49

1

T16

1

T35

1

T37

1