Group : sysrst_ctrl_env_pkg::sysrst_ctrl_wakeup_event_obj::sysrst_ctrl_wkup_event_cg
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Group : sysrst_ctrl_env_pkg::sysrst_ctrl_wakeup_event_obj::sysrst_ctrl_wkup_event_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
51.52 51.52 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
sysrst_ctrl_wkup_event_cg 51.52 1 100 1 64 64




Group Instance : sysrst_ctrl_wkup_event_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
51.52 1 100 1 64 64




Summary for Group Instance sysrst_ctrl_wkup_event_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 1 9 90.00
Crosses 23 15 8 34.78


Variables for Group Instance sysrst_ctrl_wkup_event_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_h2l_pwrb 2 0 2 100.00 100 1 1 2
cp_h_ac_present 2 0 2 100.00 100 1 1 2
cp_interrupt_gen 2 1 1 50.00 100 1 1 2
cp_l2h_lid_open 2 0 2 100.00 100 1 1 2
cp_wakeup_sts 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sysrst_ctrl_wkup_event_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cross_wkup_sts 23 15 8 34.78 100 1 1 0


Summary for Variable cp_h2l_pwrb

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_h2l_pwrb

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 839 1 T1 3 T13 2 T14 3
auto[1] 765 1 T1 3 T13 2 T14 3



Summary for Variable cp_h_ac_present

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_h_ac_present

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1006 1 T1 3 T13 1 T14 3
auto[1] 598 1 T1 3 T13 3 T14 3



Summary for Variable cp_interrupt_gen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_interrupt_gen

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1604 1 T1 6 T13 4 T14 6



Summary for Variable cp_l2h_lid_open

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_l2h_lid_open

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 969 1 T1 3 T13 2 T14 4
auto[1] 635 1 T1 3 T13 2 T14 2



Summary for Variable cp_wakeup_sts

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_wakeup_sts

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1546 1 T1 3 T13 4 T14 6
auto[1] 58 1 T1 3 T20 1 T21 1



Summary for Cross cross_wkup_sts

Samples crossed: cp_wakeup_sts cp_h2l_pwrb cp_l2h_lid_open cp_h_ac_present cp_interrupt_gen
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 23 15 8 34.78 15
Automatically Generated Cross Bins 23 15 8 34.78 15
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cross_wkup_sts

Element holes
cp_wakeup_stscp_h2l_pwrbcp_l2h_lid_opencp_h_ac_presentcp_interrupt_genCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[0]] * * * -- -- 8
[auto[1]] [auto[1]] [auto[0]] [auto[1]] * -- -- 2
[auto[1]] [auto[1]] [auto[1]] * * -- -- 4


Uncovered bins
cp_wakeup_stscp_h2l_pwrbcp_l2h_lid_opencp_h_ac_presentcp_interrupt_genCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[1]] [auto[0]] [auto[0]] [auto[1]] 0 1 1


Covered bins
cp_wakeup_stscp_h2l_pwrbcp_l2h_lid_opencp_h_ac_presentcp_interrupt_genCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 383 1 T14 1 T23 1 T7 2
auto[0] auto[0] auto[0] auto[1] auto[0] 157 1 T14 1 T7 2 T33 1
auto[0] auto[0] auto[1] auto[0] auto[0] 151 1 T13 1 T23 1 T22 3
auto[0] auto[0] auto[1] auto[1] auto[0] 148 1 T1 3 T13 1 T14 1
auto[0] auto[1] auto[0] auto[0] auto[0] 232 1 T14 2 T16 1 T7 2
auto[0] auto[1] auto[0] auto[1] auto[0] 139 1 T13 2 T22 1 T65 1
auto[0] auto[1] auto[1] auto[0] auto[0] 182 1 T22 2 T7 1 T56 1
auto[0] auto[1] auto[1] auto[1] auto[0] 154 1 T14 1 T7 1 T67 1


User Defined Cross Bins for cross_wkup_sts

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid0 0 Excluded
invalid1 0 Excluded

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