Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	153981	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

118199

1

T1

21

T5

51

T6

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	140678	1			T1	29		T5	62		T6	2
values[0x0]	65266	1			T1	10		T5	39		T13	13
values[0x1]	66236	1			T1	12		T5	22		T13	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	124485	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

147695

1

T1

24

T5

58

T6

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1071	1			T16	2		T22	1		T60	1
valid_sources[0x01]	880	1			T1	1		T9	4		T26	1
valid_sources[0x02]	824	1			T1	1		T16	1		T23	3
valid_sources[0x03]	806	1			T1	1		T7	3		T9	3
valid_sources[0x04]	847	1			T9	3		T56	1		T41	2
valid_sources[0x05]	815	1			T16	1		T56	2		T41	3
valid_sources[0x06]	796	1			T1	1		T16	3		T9	2
valid_sources[0x07]	854	1			T1	1		T16	1		T9	3
valid_sources[0x08]	1430	1			T23	1		T7	2		T9	6
valid_sources[0x09]	925	1			T9	3		T56	1		T41	2
valid_sources[0x0a]	745	1			T16	1		T9	2		T41	2
valid_sources[0x0b]	829	1			T16	1		T7	1		T9	3
valid_sources[0x0c]	1009	1			T49	1		T7	1		T9	2
valid_sources[0x0d]	898	1			T1	1		T5	2		T9	4
valid_sources[0x0e]	946	1			T1	2		T53	1		T9	2
valid_sources[0x0f]	731	1			T9	4		T26	5		T56	1
valid_sources[0x10]	781	1			T23	3		T7	1		T9	3
valid_sources[0x11]	1082	1			T5	1		T16	1		T60	1
valid_sources[0x12]	1078	1			T6	1		T23	2		T7	1
valid_sources[0x13]	1625	1			T7	2		T9	1		T34	1
valid_sources[0x14]	826	1			T7	1		T9	3		T26	1
valid_sources[0x15]	805	1			T7	1		T9	3		T26	11
valid_sources[0x16]	839	1			T16	1		T9	1		T26	1
valid_sources[0x17]	1149	1			T23	1		T22	6		T7	1
valid_sources[0x18]	1206	1			T23	3		T7	1		T9	1
valid_sources[0x19]	1427	1			T5	3		T22	3		T9	1
valid_sources[0x1a]	1097	1			T26	9		T56	1		T25	1
valid_sources[0x1b]	948	1			T1	1		T5	1		T52	2
valid_sources[0x1c]	895	1			T16	1		T56	1		T41	5
valid_sources[0x1d]	983	1			T9	3		T26	9		T41	4
valid_sources[0x1e]	839	1			T5	1		T16	1		T23	1
valid_sources[0x1f]	1306	1			T9	3		T56	1		T25	3
valid_sources[0x20]	756	1			T5	1		T23	3		T50	4
valid_sources[0x21]	937	1			T5	5		T52	1		T7	2
valid_sources[0x22]	1313	1			T49	1		T23	1		T53	1
valid_sources[0x23]	1311	1			T1	1		T3	12		T9	2
valid_sources[0x24]	1197	1			T23	1		T7	1		T9	2
valid_sources[0x25]	910	1			T1	1		T5	3		T7	2
valid_sources[0x26]	760	1			T16	1		T9	2		T41	1
valid_sources[0x27]	761	1			T16	2		T51	1		T56	1
valid_sources[0x28]	846	1			T16	2		T54	1		T7	1
valid_sources[0x29]	943	1			T9	4		T56	2		T65	1
valid_sources[0x2a]	1041	1			T53	1		T9	3		T24	2
valid_sources[0x2b]	1091	1			T5	4		T7	1		T9	2
valid_sources[0x2c]	1505	1			T16	1		T52	8		T9	2
valid_sources[0x2d]	938	1			T49	1		T23	1		T9	4
valid_sources[0x2e]	892	1			T7	3		T9	3		T32	2
valid_sources[0x2f]	1047	1			T1	1		T4	22		T7	1
valid_sources[0x30]	854	1			T16	1		T22	10		T7	1
valid_sources[0x31]	946	1			T22	2		T9	2		T41	3
valid_sources[0x32]	930	1			T1	1		T5	1		T16	1
valid_sources[0x33]	967	1			T5	1		T9	8		T26	1
valid_sources[0x34]	878	1			T16	2		T7	1		T9	1
valid_sources[0x35]	895	1			T22	2		T9	2		T34	5
valid_sources[0x36]	889	1			T49	1		T9	5		T43	1
valid_sources[0x37]	822	1			T7	1		T9	2		T56	2
valid_sources[0x38]	820	1			T7	1		T9	1		T26	7
valid_sources[0x39]	1073	1			T1	1		T16	1		T7	1
valid_sources[0x3a]	793	1			T16	1		T22	1		T9	3
valid_sources[0x3b]	797	1			T1	1		T16	1		T7	1
valid_sources[0x3c]	910	1			T1	1		T22	2		T7	1
valid_sources[0x3d]	902	1			T9	2		T56	1		T41	2
valid_sources[0x3e]	2588	1			T9	2		T41	5		T44	3
valid_sources[0x3f]	1041	1			T7	1		T9	1		T41	2
valid_sources[0x40]	1050	1			T9	4		T32	1		T41	1
valid_sources[0x41]	944	1			T56	1		T32	1		T41	2
valid_sources[0x42]	1040	1			T9	4		T41	2		T34	5
valid_sources[0x43]	960	1			T23	3		T9	3		T56	1
valid_sources[0x44]	829	1			T22	1		T9	2		T41	1
valid_sources[0x45]	934	1			T16	1		T7	1		T9	4
valid_sources[0x46]	898	1			T16	1		T23	1		T9	1
valid_sources[0x47]	890	1			T1	1		T5	1		T16	1
valid_sources[0x48]	1100	1			T53	1		T9	1		T56	1
valid_sources[0x49]	1276	1			T23	2		T51	1		T7	3
valid_sources[0x4a]	862	1			T1	1		T5	3		T9	4
valid_sources[0x4b]	786	1			T5	3		T52	5		T9	1
valid_sources[0x4c]	1117	1			T23	1		T22	1		T41	2
valid_sources[0x4d]	877	1			T1	2		T9	2		T26	31
valid_sources[0x4e]	856	1			T5	3		T16	3		T60	1
valid_sources[0x4f]	1804	1			T16	1		T23	5		T7	1
valid_sources[0x50]	956	1			T5	1		T7	1		T9	2
valid_sources[0x51]	806	1			T5	2		T16	1		T9	2
valid_sources[0x52]	1062	1			T16	2		T23	5		T9	1
valid_sources[0x53]	910	1			T5	1		T23	4		T7	2
valid_sources[0x54]	914	1			T1	2		T7	1		T9	3
valid_sources[0x55]	996	1			T5	1		T7	1		T9	1
valid_sources[0x56]	852	1			T9	3		T41	3		T43	1
valid_sources[0x57]	892	1			T16	1		T9	1		T26	2
valid_sources[0x58]	1109	1			T7	4		T9	1		T24	1
valid_sources[0x59]	882	1			T5	1		T9	4		T26	6
valid_sources[0x5a]	1594	1			T9	1		T26	3		T41	1
valid_sources[0x5b]	939	1			T7	2		T9	5		T56	2
valid_sources[0x5c]	990	1			T5	1		T60	1		T7	2
valid_sources[0x5d]	948	1			T11	1		T34	9		T44	1
valid_sources[0x5e]	1937	1			T23	2		T9	2		T26	6
valid_sources[0x5f]	2450	1			T1	1		T9	4		T41	1
valid_sources[0x60]	1842	1			T23	1		T9	3		T41	1
valid_sources[0x61]	1242	1			T5	2		T16	1		T9	4
valid_sources[0x62]	783	1			T2	1		T16	2		T7	1
valid_sources[0x63]	1078	1			T16	1		T22	5		T7	1
valid_sources[0x64]	953	1			T16	1		T23	7		T54	1
valid_sources[0x65]	1208	1			T16	1		T22	1		T7	2
valid_sources[0x66]	883	1			T1	1		T15	16		T16	2
valid_sources[0x67]	1118	1			T23	2		T9	2		T56	1
valid_sources[0x68]	1323	1			T1	1		T5	2		T22	1
valid_sources[0x69]	942	1			T9	3		T41	2		T34	7
valid_sources[0x6a]	810	1			T7	1		T9	3		T41	4
valid_sources[0x6b]	894	1			T49	2		T7	1		T9	2
valid_sources[0x6c]	2176	1			T16	1		T7	2		T8	905
valid_sources[0x6d]	1595	1			T5	2		T9	4		T26	25
valid_sources[0x6e]	1947	1			T1	1		T5	1		T50	25
valid_sources[0x6f]	906	1			T23	2		T7	3		T9	3
valid_sources[0x70]	735	1			T23	1		T9	3		T56	1
valid_sources[0x71]	848	1			T52	1		T7	1		T9	1
valid_sources[0x72]	916	1			T16	1		T22	3		T41	1
valid_sources[0x73]	950	1			T60	1		T9	1		T55	6
valid_sources[0x74]	924	1			T22	1		T7	1		T9	1
valid_sources[0x75]	1072	1			T7	4		T11	1		T24	1
valid_sources[0x76]	736	1			T16	1		T23	1		T9	3
valid_sources[0x77]	939	1			T23	2		T9	1		T41	4
valid_sources[0x78]	853	1			T16	2		T23	1		T9	1
valid_sources[0x79]	1930	1			T23	4		T9	2		T41	1
valid_sources[0x7a]	846	1			T9	1		T26	7		T56	2
valid_sources[0x7b]	832	1			T5	1		T16	2		T54	1
valid_sources[0x7c]	951	1			T1	1		T5	1		T23	3
valid_sources[0x7d]	1098	1			T23	1		T7	4		T9	3
valid_sources[0x7e]	951	1			T23	3		T7	1		T56	1
valid_sources[0x7f]	1821	1			T5	2		T23	2		T9	4
valid_sources[0x80]	781	1			T9	5		T41	1		T65	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

63942

1

T1

14

T5

32

T6

1

values[0x0]

all_enables

biggest_size

31820

1

T1

5

T5

14

T13

8

values[0x1]

all_enables

biggest_size

22437

1

T1

2

T5

5

T13

3