Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T15,T24,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T15,T24,T25

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T15,T24,T25

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T24,T25
1	0	Covered	T1,T5,T6
1	1	Covered	T15,T24,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T24,T25
0	1	Covered	T103
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T24,T25
0	1	Covered	T15,T24,T25
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T24,T25
1	-	Covered	T15,T24,T25

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T15,T24,T25
DetectSt	168	Covered	T15,T24,T25
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T15,T24,T25

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T15,T24,T25
DebounceSt->IdleSt	163	Covered	T24,T25,T37
DetectSt->IdleSt	186	Covered	T103
DetectSt->StableSt	191	Covered	T15,T24,T25
IdleSt->DebounceSt	148	Covered	T15,T24,T25
StableSt->IdleSt	206	Covered	T15,T24,T25

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T15,T24,T25
0	1	Covered	T15,T24,T25
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T24,T25
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T15,T24,T25
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T24,T25
DebounceSt	-	0	1	0	-	-	-	Covered	T24,T25,T37
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T24,T25
DetectSt	-	-	-	-	1	-	-	Covered	T103
DetectSt	-	-	-	-	0	1	-	Covered	T15,T24,T25
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T15,T24,T25
StableSt	-	-	-	-	-	-	0	Covered	T15,T24,T25
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7712811	346	0	0
CntIncr_A	7712811	194487	0	0
CntNoWrap_A	7712811	7041658	0	0
DetectStDropOut_A	7712811	1	0	0
DetectedOut_A	7712811	1063	0	0
DetectedPulseOut_A	7712811	158	0	0
DisabledIdleSt_A	7712811	6839436	0	0
DisabledNoDetection_A	7712811	6841781	0	0
EnterDebounceSt_A	7712811	191	0	0
EnterDetectSt_A	7712811	159	0	0
EnterStableSt_A	7712811	158	0	0
PulseIsPulse_A	7712811	158	0	0
StayInStableSt	7712811	905	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7712811	7011	0	0
gen_low_level_sva.LowLevelEvent_A	7712811	7044416	0	0
gen_not_sticky_sva.StableStDropOut_A	7712811	158	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	346	0	0
T4	1063	0	0	0
T15	764	2	0	0
T16	507	0	0	0
T23	1885	0	0	0
T24	0	3	0	0
T25	0	5	0	0
T33	0	6	0	0
T37	0	7	0	0
T42	0	4	0	0
T43	0	2	0	0
T45	0	4	0	0
T48	0	4	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T53	403	0	0	0
T54	427	0	0	0
T91	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	194487	0	0
T4	1063	0	0	0
T15	764	94	0	0
T16	507	0	0	0
T23	1885	0	0	0
T24	0	105	0	0
T25	0	146	0	0
T33	0	1499	0	0
T37	0	1556	0	0
T42	0	179	0	0
T43	0	41	0	0
T45	0	136	0	0
T48	0	58	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T53	403	0	0	0
T54	427	0	0	0
T91	0	66	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7041658	0	0
T1	1212	811	0	0
T2	516	115	0	0
T3	499	98	0	0
T4	1063	662	0	0
T5	502	101	0	0
T6	422	21	0	0
T13	494	93	0	0
T14	498	97	0	0
T15	764	361	0	0
T16	507	106	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	1	0	0
T103	4034	1	0	0
T113	26489	0	0	0
T114	14760	0	0	0
T115	10838	0	0	0
T116	937	0	0	0
T117	449	0	0	0
T118	407	0	0	0
T119	423	0	0	0
T120	860	0	0	0
T121	1110	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	1063	0	0
T4	1063	0	0	0
T15	764	3	0	0
T16	507	0	0	0
T23	1885	0	0	0
T24	0	10	0	0
T25	0	5	0	0
T33	0	19	0	0
T37	0	24	0	0
T42	0	21	0	0
T43	0	7	0	0
T45	0	16	0	0
T48	0	13	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T53	403	0	0	0
T54	427	0	0	0
T91	0	7	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	158	0	0
T4	1063	0	0	0
T15	764	1	0	0
T16	507	0	0	0
T23	1885	0	0	0
T24	0	1	0	0
T25	0	2	0	0
T33	0	3	0	0
T37	0	3	0	0
T42	0	2	0	0
T43	0	1	0	0
T45	0	2	0	0
T48	0	2	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T53	403	0	0	0
T54	427	0	0	0
T91	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	6839436	0	0
T1	1212	811	0	0
T2	516	115	0	0
T3	499	98	0	0
T4	1063	662	0	0
T5	502	101	0	0
T6	422	21	0	0
T13	494	93	0	0
T14	498	97	0	0
T15	764	217	0	0
T16	507	106	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	6841781	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	217	0	0
T16	507	107	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	191	0	0
T4	1063	0	0	0
T15	764	1	0	0
T16	507	0	0	0
T23	1885	0	0	0
T24	0	2	0	0
T25	0	3	0	0
T33	0	3	0	0
T37	0	5	0	0
T42	0	2	0	0
T43	0	1	0	0
T45	0	2	0	0
T48	0	2	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T53	403	0	0	0
T54	427	0	0	0
T91	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	159	0	0
T4	1063	0	0	0
T15	764	1	0	0
T16	507	0	0	0
T23	1885	0	0	0
T24	0	1	0	0
T25	0	2	0	0
T33	0	3	0	0
T37	0	3	0	0
T42	0	2	0	0
T43	0	1	0	0
T45	0	2	0	0
T48	0	2	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T53	403	0	0	0
T54	427	0	0	0
T91	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	158	0	0
T4	1063	0	0	0
T15	764	1	0	0
T16	507	0	0	0
T23	1885	0	0	0
T24	0	1	0	0
T25	0	2	0	0
T33	0	3	0	0
T37	0	3	0	0
T42	0	2	0	0
T43	0	1	0	0
T45	0	2	0	0
T48	0	2	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T53	403	0	0	0
T54	427	0	0	0
T91	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	158	0	0
T4	1063	0	0	0
T15	764	1	0	0
T16	507	0	0	0
T23	1885	0	0	0
T24	0	1	0	0
T25	0	2	0	0
T33	0	3	0	0
T37	0	3	0	0
T42	0	2	0	0
T43	0	1	0	0
T45	0	2	0	0
T48	0	2	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T53	403	0	0	0
T54	427	0	0	0
T91	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	905	0	0
T4	1063	0	0	0
T15	764	2	0	0
T16	507	0	0	0
T23	1885	0	0	0
T24	0	9	0	0
T25	0	3	0	0
T33	0	16	0	0
T37	0	21	0	0
T42	0	19	0	0
T43	0	6	0	0
T45	0	14	0	0
T48	0	11	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T53	403	0	0	0
T54	427	0	0	0
T91	0	6	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7011	0	0
T1	1212	8	0	0
T2	516	0	0	0
T3	499	0	0	0
T4	1063	1	0	0
T5	502	5	0	0
T6	422	2	0	0
T13	494	11	0	0
T14	498	7	0	0
T15	764	3	0	0
T16	507	4	0	0
T23	0	16	0	0
T50	0	7	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7044416	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	158	0	0
T4	1063	0	0	0
T15	764	1	0	0
T16	507	0	0	0
T23	1885	0	0	0
T24	0	1	0	0
T25	0	2	0	0
T33	0	3	0	0
T37	0	3	0	0
T42	0	2	0	0
T43	0	1	0	0
T45	0	2	0	0
T48	0	2	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T53	403	0	0	0
T54	427	0	0	0
T91	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T20,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T1,T20,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T20,T21,T64

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T20,T21
1	0	Covered	T5,T6,T13
1	1	Covered	T1,T20,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T64
0	1	Covered	T75,T88,T89
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T64
0	1	Unreachable
1	0	Covered	T20,T21,T64

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T20,T21
DetectSt	168	Covered	T20,T21,T64
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T20,T21,T64

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T20,T21,T64
DebounceSt->IdleSt	163	Covered	T1,T63,T74
DetectSt->IdleSt	186	Covered	T75,T88,T89
DetectSt->StableSt	191	Covered	T20,T21,T64
IdleSt->DebounceSt	148	Covered	T1,T20,T21
StableSt->IdleSt	206	Covered	T20,T21,T64

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T20,T21
0	1	Covered	T1,T20,T21
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T64
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T20,T21
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T20,T21,T64
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T63,T74
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T20,T21
DetectSt	-	-	-	-	1	-	-	Covered	T75,T88,T89
DetectSt	-	-	-	-	0	1	-	Covered	T20,T21,T64
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T20,T21,T64
StableSt	-	-	-	-	-	-	0	Covered	T20,T21,T64
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7712811	173	0	0
CntIncr_A	7712811	171408	0	0
CntNoWrap_A	7712811	7041831	0	0
DetectStDropOut_A	7712811	19	0	0
DetectedOut_A	7712811	585133	0	0
DetectedPulseOut_A	7712811	36	0	0
DisabledIdleSt_A	7712811	5770061	0	0
DisabledNoDetection_A	7712811	5772470	0	0
EnterDebounceSt_A	7712811	118	0	0
EnterDetectSt_A	7712811	55	0	0
EnterStableSt_A	7712811	36	0	0
PulseIsPulse_A	7712811	36	0	0
StayInStableSt	7712811	585097	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7712811	7011	0	0
gen_low_level_sva.LowLevelEvent_A	7712811	7044416	0	0
gen_sticky_sva.StableStDropOut_A	7712811	17781	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	173	0	0
T1	1212	8	0	0
T2	516	0	0	0
T3	499	0	0	0
T4	1063	0	0	0
T5	502	0	0	0
T6	422	0	0	0
T13	494	0	0	0
T14	498	0	0	0
T15	764	0	0	0
T16	507	0	0	0
T20	0	2	0	0
T21	0	2	0	0
T63	0	3	0	0
T64	0	4	0	0
T73	0	2	0	0
T74	0	2	0	0
T75	0	7	0	0
T76	0	2	0	0
T77	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	171408	0	0
T1	1212	336	0	0
T2	516	0	0	0
T3	499	0	0	0
T4	1063	0	0	0
T5	502	0	0	0
T6	422	0	0	0
T13	494	0	0	0
T14	498	0	0	0
T15	764	0	0	0
T16	507	0	0	0
T20	0	11093	0	0
T21	0	43	0	0
T63	0	201	0	0
T64	0	57	0	0
T73	0	41	0	0
T74	0	126	0	0
T75	0	264	0	0
T76	0	47	0	0
T77	0	56	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7041831	0	0
T1	1212	803	0	0
T2	516	115	0	0
T3	499	98	0	0
T4	1063	662	0	0
T5	502	101	0	0
T6	422	21	0	0
T13	494	93	0	0
T14	498	97	0	0
T15	764	363	0	0
T16	507	106	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	19	0	0
T75	1395	2	0	0
T76	2045	0	0	0
T88	0	7	0	0
T89	0	1	0	0
T94	16120	0	0	0
T95	28321	0	0	0
T130	0	1	0	0
T131	0	2	0	0
T132	0	4	0	0
T133	0	2	0	0
T134	424	0	0	0
T135	575	0	0	0
T136	1840	0	0	0
T137	498	0	0	0
T138	649	0	0	0
T139	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	585133	0	0
T20	69065	30005	0	0
T21	954	185	0	0
T45	686	0	0	0
T46	10984	0	0	0
T61	5381	0	0	0
T62	555999	0	0	0
T64	0	272	0	0
T73	0	173	0	0
T75	0	68	0	0
T76	0	208	0	0
T77	0	134	0	0
T85	0	5	0	0
T123	0	97	0	0
T124	0	30	0	0
T126	403	0	0	0
T127	523	0	0	0
T128	525	0	0	0
T129	8402	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	36	0	0
T20	69065	1	0	0
T21	954	1	0	0
T45	686	0	0	0
T46	10984	0	0	0
T61	5381	0	0	0
T62	555999	0	0	0
T64	0	2	0	0
T73	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T85	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0
T126	403	0	0	0
T127	523	0	0	0
T128	525	0	0	0
T129	8402	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	5770061	0	0
T1	1212	75	0	0
T2	516	115	0	0
T3	499	98	0	0
T4	1063	662	0	0
T5	502	101	0	0
T6	422	21	0	0
T13	494	93	0	0
T14	498	97	0	0
T15	764	363	0	0
T16	507	106	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	5772470	0	0
T1	1212	76	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	118	0	0
T1	1212	8	0	0
T2	516	0	0	0
T3	499	0	0	0
T4	1063	0	0	0
T5	502	0	0	0
T6	422	0	0	0
T13	494	0	0	0
T14	498	0	0	0
T15	764	0	0	0
T16	507	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T63	0	3	0	0
T64	0	2	0	0
T73	0	1	0	0
T74	0	2	0	0
T75	0	4	0	0
T76	0	1	0	0
T77	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	55	0	0
T20	69065	1	0	0
T21	954	1	0	0
T45	686	0	0	0
T46	10984	0	0	0
T61	5381	0	0	0
T62	555999	0	0	0
T64	0	2	0	0
T73	0	1	0	0
T75	0	3	0	0
T76	0	1	0	0
T77	0	1	0	0
T85	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0
T126	403	0	0	0
T127	523	0	0	0
T128	525	0	0	0
T129	8402	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	36	0	0
T20	69065	1	0	0
T21	954	1	0	0
T45	686	0	0	0
T46	10984	0	0	0
T61	5381	0	0	0
T62	555999	0	0	0
T64	0	2	0	0
T73	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T85	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0
T126	403	0	0	0
T127	523	0	0	0
T128	525	0	0	0
T129	8402	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	36	0	0
T20	69065	1	0	0
T21	954	1	0	0
T45	686	0	0	0
T46	10984	0	0	0
T61	5381	0	0	0
T62	555999	0	0	0
T64	0	2	0	0
T73	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T85	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0
T126	403	0	0	0
T127	523	0	0	0
T128	525	0	0	0
T129	8402	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	585097	0	0
T20	69065	30004	0	0
T21	954	184	0	0
T45	686	0	0	0
T46	10984	0	0	0
T61	5381	0	0	0
T62	555999	0	0	0
T64	0	270	0	0
T73	0	172	0	0
T75	0	67	0	0
T76	0	207	0	0
T77	0	133	0	0
T85	0	4	0	0
T123	0	96	0	0
T124	0	29	0	0
T126	403	0	0	0
T127	523	0	0	0
T128	525	0	0	0
T129	8402	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7011	0	0
T1	1212	8	0	0
T2	516	0	0	0
T3	499	0	0	0
T4	1063	1	0	0
T5	502	5	0	0
T6	422	2	0	0
T13	494	11	0	0
T14	498	7	0	0
T15	764	3	0	0
T16	507	4	0	0
T23	0	16	0	0
T50	0	7	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7044416	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	17781	0	0
T20	69065	72	0	0
T21	954	188	0	0
T45	686	0	0	0
T46	10984	0	0	0
T61	5381	0	0	0
T62	555999	0	0	0
T64	0	659	0	0
T73	0	396	0	0
T75	0	77	0	0
T76	0	396	0	0
T77	0	69	0	0
T85	0	98	0	0
T123	0	211	0	0
T124	0	233	0	0
T126	403	0	0	0
T127	523	0	0	0
T128	525	0	0	0
T129	8402	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T20,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T1,T20,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T20,T21,T64

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T20,T21
1	0	Covered	T5,T6,T13
1	1	Covered	T1,T20,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T64
0	1	Covered	T21,T64,T87
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T64
0	1	Unreachable
1	0	Covered	T20,T21,T64

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T20,T21
DetectSt	168	Covered	T20,T21,T64
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T20,T21,T64

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T20,T21,T64
DebounceSt->IdleSt	163	Covered	T1,T21,T63
DetectSt->IdleSt	186	Covered	T21,T64,T87
DetectSt->StableSt	191	Covered	T20,T21,T64
IdleSt->DebounceSt	148	Covered	T1,T20,T21
StableSt->IdleSt	206	Covered	T20,T21,T64

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T20,T21
0	1	Covered	T1,T20,T21
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T64
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T20,T21
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T20,T21,T64
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T21,T63
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T20,T21
DetectSt	-	-	-	-	1	-	-	Covered	T21,T64,T87
DetectSt	-	-	-	-	0	1	-	Covered	T20,T21,T64
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T20,T21,T64
StableSt	-	-	-	-	-	-	0	Covered	T20,T21,T64
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7712811	180	0	0
CntIncr_A	7712811	333276	0	0
CntNoWrap_A	7712811	7041824	0	0
DetectStDropOut_A	7712811	14	0	0
DetectedOut_A	7712811	132763	0	0
DetectedPulseOut_A	7712811	37	0	0
DisabledIdleSt_A	7712811	5770061	0	0
DisabledNoDetection_A	7712811	5772470	0	0
EnterDebounceSt_A	7712811	129	0	0
EnterDetectSt_A	7712811	51	0	0
EnterStableSt_A	7712811	37	0	0
PulseIsPulse_A	7712811	37	0	0
StayInStableSt	7712811	132726	0	0
gen_high_level_sva.HighLevelEvent_A	7712811	7044416	0	0
gen_sticky_sva.StableStDropOut_A	7712811	388003	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	180	0	0
T1	1212	8	0	0
T2	516	0	0	0
T3	499	0	0	0
T4	1063	0	0	0
T5	502	0	0	0
T6	422	0	0	0
T13	494	0	0	0
T14	498	0	0	0
T15	764	0	0	0
T16	507	0	0	0
T20	0	2	0	0
T21	0	5	0	0
T63	0	3	0	0
T64	0	6	0	0
T73	0	3	0	0
T74	0	2	0	0
T75	0	2	0	0
T76	0	5	0	0
T77	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	333276	0	0
T1	1212	464	0	0
T2	516	0	0	0
T3	499	0	0	0
T4	1063	0	0	0
T5	502	0	0	0
T6	422	0	0	0
T13	494	0	0	0
T14	498	0	0	0
T15	764	0	0	0
T16	507	0	0	0
T20	0	63	0	0
T21	0	231	0	0
T63	0	173097	0	0
T64	0	278	0	0
T73	0	225	0	0
T74	0	11	0	0
T75	0	39	0	0
T76	0	335	0	0
T77	0	86	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7041824	0	0
T1	1212	803	0	0
T2	516	115	0	0
T3	499	98	0	0
T4	1063	662	0	0
T5	502	101	0	0
T6	422	21	0	0
T13	494	93	0	0
T14	498	97	0	0
T15	764	363	0	0
T16	507	106	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	14	0	0
T21	954	1	0	0
T47	513	0	0	0
T63	562238	0	0	0
T64	0	1	0	0
T87	0	2	0	0
T88	0	2	0	0
T90	25273	0	0	0
T103	0	1	0	0
T125	0	1	0	0
T132	0	3	0	0
T140	0	2	0	0
T141	0	1	0	0
T142	491	0	0	0
T143	526	0	0	0
T144	525	0	0	0
T145	410	0	0	0
T146	503	0	0	0
T147	424	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	132763	0	0
T20	69065	304	0	0
T21	954	78	0	0
T45	686	0	0	0
T46	10984	0	0	0
T61	5381	0	0	0
T62	555999	0	0	0
T64	0	489	0	0
T74	0	31	0	0
T75	0	301	0	0
T77	0	88	0	0
T85	0	14	0	0
T123	0	208	0	0
T124	0	167	0	0
T125	0	495	0	0
T126	403	0	0	0
T127	523	0	0	0
T128	525	0	0	0
T129	8402	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	37	0	0
T20	69065	1	0	0
T21	954	1	0	0
T45	686	0	0	0
T46	10984	0	0	0
T61	5381	0	0	0
T62	555999	0	0	0
T64	0	2	0	0
T74	0	1	0	0
T75	0	1	0	0
T77	0	1	0	0
T85	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0
T126	403	0	0	0
T127	523	0	0	0
T128	525	0	0	0
T129	8402	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	5770061	0	0
T1	1212	75	0	0
T2	516	115	0	0
T3	499	98	0	0
T4	1063	662	0	0
T5	502	101	0	0
T6	422	21	0	0
T13	494	93	0	0
T14	498	97	0	0
T15	764	363	0	0
T16	507	106	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	5772470	0	0
T1	1212	76	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	129	0	0
T1	1212	8	0	0
T2	516	0	0	0
T3	499	0	0	0
T4	1063	0	0	0
T5	502	0	0	0
T6	422	0	0	0
T13	494	0	0	0
T14	498	0	0	0
T15	764	0	0	0
T16	507	0	0	0
T20	0	1	0	0
T21	0	3	0	0
T63	0	3	0	0
T64	0	3	0	0
T73	0	3	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	5	0	0
T77	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	51	0	0
T20	69065	1	0	0
T21	954	2	0	0
T45	686	0	0	0
T46	10984	0	0	0
T61	5381	0	0	0
T62	555999	0	0	0
T64	0	3	0	0
T74	0	1	0	0
T75	0	1	0	0
T77	0	1	0	0
T85	0	1	0	0
T87	0	2	0	0
T123	0	1	0	0
T124	0	1	0	0
T126	403	0	0	0
T127	523	0	0	0
T128	525	0	0	0
T129	8402	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	37	0	0
T20	69065	1	0	0
T21	954	1	0	0
T45	686	0	0	0
T46	10984	0	0	0
T61	5381	0	0	0
T62	555999	0	0	0
T64	0	2	0	0
T74	0	1	0	0
T75	0	1	0	0
T77	0	1	0	0
T85	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0
T126	403	0	0	0
T127	523	0	0	0
T128	525	0	0	0
T129	8402	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	37	0	0
T20	69065	1	0	0
T21	954	1	0	0
T45	686	0	0	0
T46	10984	0	0	0
T61	5381	0	0	0
T62	555999	0	0	0
T64	0	2	0	0
T74	0	1	0	0
T75	0	1	0	0
T77	0	1	0	0
T85	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0
T126	403	0	0	0
T127	523	0	0	0
T128	525	0	0	0
T129	8402	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	132726	0	0
T20	69065	303	0	0
T21	954	77	0	0
T45	686	0	0	0
T46	10984	0	0	0
T61	5381	0	0	0
T62	555999	0	0	0
T64	0	487	0	0
T74	0	30	0	0
T75	0	300	0	0
T77	0	87	0	0
T85	0	13	0	0
T123	0	207	0	0
T124	0	166	0	0
T125	0	494	0	0
T126	403	0	0	0
T127	523	0	0	0
T128	525	0	0	0
T129	8402	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7044416	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	388003	0	0
T20	69065	40802	0	0
T21	954	56	0	0
T45	686	0	0	0
T46	10984	0	0	0
T61	5381	0	0	0
T62	555999	0	0	0
T64	0	204	0	0
T74	0	121	0	0
T75	0	185	0	0
T77	0	99	0	0
T85	0	28	0	0
T123	0	47	0	0
T124	0	38	0	0
T125	0	83	0	0
T126	403	0	0	0
T127	523	0	0	0
T128	525	0	0	0
T129	8402	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T20,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T1,T20,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T20,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T20,T21
1	0	Covered	T5,T6,T13
1	1	Covered	T1,T20,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T20,T21
0	1	Covered	T21,T74,T85
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T20,T21
0	1	Unreachable
1	0	Covered	T1,T20,T21

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T20,T21
DetectSt	168	Covered	T1,T20,T21
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T1,T20,T21

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T20,T21
DebounceSt->IdleSt	163	Covered	T21,T63,T64
DetectSt->IdleSt	186	Covered	T21,T74,T85
DetectSt->StableSt	191	Covered	T1,T20,T21
IdleSt->DebounceSt	148	Covered	T1,T20,T21
StableSt->IdleSt	206	Covered	T1,T20,T21

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T20,T21
0	1	Covered	T1,T20,T21
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T20,T21
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T20,T21
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T20,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T21,T63,T64
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T20,T21
DetectSt	-	-	-	-	1	-	-	Covered	T21,T74,T85
DetectSt	-	-	-	-	0	1	-	Covered	T1,T20,T21
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T20,T21
StableSt	-	-	-	-	-	-	0	Covered	T1,T20,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7712811	159	0	0
CntIncr_A	7712811	138479	0	0
CntNoWrap_A	7712811	7041845	0	0
DetectStDropOut_A	7712811	14	0	0
DetectedOut_A	7712811	8164	0	0
DetectedPulseOut_A	7712811	46	0	0
DisabledIdleSt_A	7712811	5770061	0	0
DisabledNoDetection_A	7712811	5772470	0	0
EnterDebounceSt_A	7712811	99	0	0
EnterDetectSt_A	7712811	60	0	0
EnterStableSt_A	7712811	46	0	0
PulseIsPulse_A	7712811	46	0	0
StayInStableSt	7712811	8118	0	0
gen_high_event_sva.HighLevelEvent_A	7712811	7044416	0	0
gen_high_level_sva.HighLevelEvent_A	7712811	7044416	0	0
gen_sticky_sva.StableStDropOut_A	7712811	932540	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	159	0	0
T1	1212	6	0	0
T2	516	0	0	0
T3	499	0	0	0
T4	1063	0	0	0
T5	502	0	0	0
T6	422	0	0	0
T13	494	0	0	0
T14	498	0	0	0
T15	764	0	0	0
T16	507	0	0	0
T20	0	2	0	0
T21	0	5	0	0
T63	0	3	0	0
T64	0	6	0	0
T73	0	2	0	0
T74	0	4	0	0
T75	0	2	0	0
T76	0	2	0	0
T77	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	138479	0	0
T1	1212	69	0	0
T2	516	0	0	0
T3	499	0	0	0
T4	1063	0	0	0
T5	502	0	0	0
T6	422	0	0	0
T13	494	0	0	0
T14	498	0	0	0
T15	764	0	0	0
T16	507	0	0	0
T20	0	12	0	0
T21	0	270	0	0
T63	0	121533	0	0
T64	0	423	0	0
T73	0	91	0	0
T74	0	44	0	0
T75	0	57	0	0
T76	0	31	0	0
T77	0	60	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7041845	0	0
T1	1212	805	0	0
T2	516	115	0	0
T3	499	98	0	0
T4	1063	662	0	0
T5	502	101	0	0
T6	422	21	0	0
T13	494	93	0	0
T14	498	97	0	0
T15	764	363	0	0
T16	507	106	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	14	0	0
T21	954	1	0	0
T47	513	0	0	0
T63	562238	0	0	0
T74	0	1	0	0
T85	0	1	0	0
T90	25273	0	0	0
T131	0	2	0	0
T142	491	0	0	0
T143	526	0	0	0
T144	525	0	0	0
T145	410	0	0	0
T146	503	0	0	0
T147	424	0	0	0
T148	0	2	0	0
T149	0	4	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	8164	0	0
T1	1212	143	0	0
T2	516	0	0	0
T3	499	0	0	0
T4	1063	0	0	0
T5	502	0	0	0
T6	422	0	0	0
T13	494	0	0	0
T14	498	0	0	0
T15	764	0	0	0
T16	507	0	0	0
T20	0	60	0	0
T21	0	95	0	0
T64	0	241	0	0
T73	0	359	0	0
T74	0	1	0	0
T75	0	423	0	0
T76	0	206	0	0
T123	0	179	0	0
T124	0	30	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	46	0	0
T1	1212	3	0	0
T2	516	0	0	0
T3	499	0	0	0
T4	1063	0	0	0
T5	502	0	0	0
T6	422	0	0	0
T13	494	0	0	0
T14	498	0	0	0
T15	764	0	0	0
T16	507	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T64	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	5770061	0	0
T1	1212	75	0	0
T2	516	115	0	0
T3	499	98	0	0
T4	1063	662	0	0
T5	502	101	0	0
T6	422	21	0	0
T13	494	93	0	0
T14	498	97	0	0
T15	764	363	0	0
T16	507	106	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	5772470	0	0
T1	1212	76	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	99	0	0
T1	1212	3	0	0
T2	516	0	0	0
T3	499	0	0	0
T4	1063	0	0	0
T5	502	0	0	0
T6	422	0	0	0
T13	494	0	0	0
T14	498	0	0	0
T15	764	0	0	0
T16	507	0	0	0
T20	0	1	0	0
T21	0	3	0	0
T63	0	3	0	0
T64	0	5	0	0
T73	0	1	0	0
T74	0	2	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	60	0	0
T1	1212	3	0	0
T2	516	0	0	0
T3	499	0	0	0
T4	1063	0	0	0
T5	502	0	0	0
T6	422	0	0	0
T13	494	0	0	0
T14	498	0	0	0
T15	764	0	0	0
T16	507	0	0	0
T20	0	1	0	0
T21	0	2	0	0
T64	0	1	0	0
T73	0	1	0	0
T74	0	2	0	0
T75	0	1	0	0
T76	0	1	0	0
T85	0	1	0	0
T123	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	46	0	0
T1	1212	3	0	0
T2	516	0	0	0
T3	499	0	0	0
T4	1063	0	0	0
T5	502	0	0	0
T6	422	0	0	0
T13	494	0	0	0
T14	498	0	0	0
T15	764	0	0	0
T16	507	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T64	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	46	0	0
T1	1212	3	0	0
T2	516	0	0	0
T3	499	0	0	0
T4	1063	0	0	0
T5	502	0	0	0
T6	422	0	0	0
T13	494	0	0	0
T14	498	0	0	0
T15	764	0	0	0
T16	507	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T64	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	8118	0	0
T1	1212	140	0	0
T2	516	0	0	0
T3	499	0	0	0
T4	1063	0	0	0
T5	502	0	0	0
T6	422	0	0	0
T13	494	0	0	0
T14	498	0	0	0
T15	764	0	0	0
T16	507	0	0	0
T20	0	59	0	0
T21	0	94	0	0
T64	0	240	0	0
T73	0	358	0	0
T75	0	422	0	0
T76	0	205	0	0
T87	0	172	0	0
T123	0	178	0	0
T124	0	29	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7044416	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7044416	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	932540	0	0
T1	1212	505	0	0
T2	516	0	0	0
T3	499	0	0	0
T4	1063	0	0	0
T5	502	0	0	0
T6	422	0	0	0
T13	494	0	0	0
T14	498	0	0	0
T15	764	0	0	0
T16	507	0	0	0
T20	0	41114	0	0
T21	0	31	0	0
T64	0	51	0	0
T73	0	166	0	0
T74	0	72	0	0
T75	0	45	0	0
T76	0	422	0	0
T123	0	126	0	0
T124	0	233	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T33,T35,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T33,T35,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T33,T35,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T12
1	0	Covered	T1,T5,T6
1	1	Covered	T33,T35,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T33,T35,T37
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T33,T35,T37
0	1	Covered	T33,T35,T37
1	0	Covered	T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T33,T35,T37
1	-	Covered	T33,T35,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T33,T35,T37
DetectSt	168	Covered	T33,T35,T37
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T33,T35,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T33,T35,T37
DebounceSt->IdleSt	163	Covered	T38,T78,T153
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T33,T35,T37
IdleSt->DebounceSt	148	Covered	T33,T35,T37
StableSt->IdleSt	206	Covered	T33,T35,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T33,T35,T37
0	1	Covered	T33,T35,T37
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T33,T35,T37
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T33,T35,T37
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T33,T35,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T38,T153,T125
DebounceSt	-	0	0	-	-	-	-	Covered	T33,T35,T37
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T33,T35,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T33,T35,T37
StableSt	-	-	-	-	-	-	0	Covered	T33,T35,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7712811	82	0	0
CntIncr_A	7712811	61268	0	0
CntNoWrap_A	7712811	7041922	0	0
DetectStDropOut_A	7712811	0	0	0
DetectedOut_A	7712811	14455	0	0
DetectedPulseOut_A	7712811	39	0	0
DisabledIdleSt_A	7712811	6779592	0	0
DisabledNoDetection_A	7712811	6781950	0	0
EnterDebounceSt_A	7712811	43	0	0
EnterDetectSt_A	7712811	39	0	0
EnterStableSt_A	7712811	39	0	0
PulseIsPulse_A	7712811	39	0	0
StayInStableSt	7712811	14396	0	0
gen_high_level_sva.HighLevelEvent_A	7712811	7044416	0	0
gen_not_sticky_sva.StableStDropOut_A	7712811	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	82	0	0
T27	11718	0	0	0
T33	4996	2	0	0
T34	22653	0	0	0
T35	0	4	0	0
T37	0	4	0	0
T38	0	3	0	0
T42	749	0	0	0
T43	3222	0	0	0
T59	513	0	0	0
T65	501	0	0	0
T66	493	0	0	0
T67	515	0	0	0
T68	506	0	0	0
T78	0	1	0	0
T154	0	2	0	0
T155	0	2	0	0
T156	0	4	0	0
T157	0	4	0	0
T158	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	61268	0	0
T27	11718	0	0	0
T33	4996	62	0	0
T34	22653	0	0	0
T35	0	66	0	0
T37	0	196	0	0
T38	0	56456	0	0
T42	749	0	0	0
T43	3222	0	0	0
T59	513	0	0	0
T65	501	0	0	0
T66	493	0	0	0
T67	515	0	0	0
T68	506	0	0	0
T78	0	19	0	0
T154	0	46	0	0
T155	0	96	0	0
T156	0	44	0	0
T157	0	116	0	0
T158	0	126	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7041922	0	0
T1	1212	811	0	0
T2	516	115	0	0
T3	499	98	0	0
T4	1063	662	0	0
T5	502	101	0	0
T6	422	21	0	0
T13	494	93	0	0
T14	498	97	0	0
T15	764	363	0	0
T16	507	106	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	14455	0	0
T27	11718	0	0	0
T33	4996	43	0	0
T34	22653	0	0	0
T35	0	81	0	0
T37	0	228	0	0
T38	0	11586	0	0
T42	749	0	0	0
T43	3222	0	0	0
T59	513	0	0	0
T65	501	0	0	0
T66	493	0	0	0
T67	515	0	0	0
T68	506	0	0	0
T153	0	123	0	0
T154	0	92	0	0
T155	0	39	0	0
T156	0	60	0	0
T157	0	145	0	0
T158	0	88	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	39	0	0
T27	11718	0	0	0
T33	4996	1	0	0
T34	22653	0	0	0
T35	0	2	0	0
T37	0	2	0	0
T38	0	1	0	0
T42	749	0	0	0
T43	3222	0	0	0
T59	513	0	0	0
T65	501	0	0	0
T66	493	0	0	0
T67	515	0	0	0
T68	506	0	0	0
T153	0	3	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	6779592	0	0
T1	1212	811	0	0
T2	516	3	0	0
T3	499	4	0	0
T4	1063	662	0	0
T5	502	101	0	0
T6	422	21	0	0
T13	494	93	0	0
T14	498	97	0	0
T15	764	363	0	0
T16	507	106	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	6781950	0	0
T1	1212	812	0	0
T2	516	3	0	0
T3	499	4	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	43	0	0
T27	11718	0	0	0
T33	4996	1	0	0
T34	22653	0	0	0
T35	0	2	0	0
T37	0	2	0	0
T38	0	2	0	0
T42	749	0	0	0
T43	3222	0	0	0
T59	513	0	0	0
T65	501	0	0	0
T66	493	0	0	0
T67	515	0	0	0
T68	506	0	0	0
T78	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	39	0	0
T27	11718	0	0	0
T33	4996	1	0	0
T34	22653	0	0	0
T35	0	2	0	0
T37	0	2	0	0
T38	0	1	0	0
T42	749	0	0	0
T43	3222	0	0	0
T59	513	0	0	0
T65	501	0	0	0
T66	493	0	0	0
T67	515	0	0	0
T68	506	0	0	0
T153	0	3	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	39	0	0
T27	11718	0	0	0
T33	4996	1	0	0
T34	22653	0	0	0
T35	0	2	0	0
T37	0	2	0	0
T38	0	1	0	0
T42	749	0	0	0
T43	3222	0	0	0
T59	513	0	0	0
T65	501	0	0	0
T66	493	0	0	0
T67	515	0	0	0
T68	506	0	0	0
T153	0	3	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	39	0	0
T27	11718	0	0	0
T33	4996	1	0	0
T34	22653	0	0	0
T35	0	2	0	0
T37	0	2	0	0
T38	0	1	0	0
T42	749	0	0	0
T43	3222	0	0	0
T59	513	0	0	0
T65	501	0	0	0
T66	493	0	0	0
T67	515	0	0	0
T68	506	0	0	0
T153	0	3	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	14396	0	0
T27	11718	0	0	0
T33	4996	42	0	0
T34	22653	0	0	0
T35	0	78	0	0
T37	0	225	0	0
T38	0	11585	0	0
T42	749	0	0	0
T43	3222	0	0	0
T59	513	0	0	0
T65	501	0	0	0
T66	493	0	0	0
T67	515	0	0	0
T68	506	0	0	0
T153	0	119	0	0
T154	0	91	0	0
T155	0	37	0	0
T156	0	57	0	0
T157	0	142	0	0
T158	0	84	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7044416	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	18	0	0
T27	11718	0	0	0
T33	4996	1	0	0
T34	22653	0	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T42	749	0	0	0
T43	3222	0	0	0
T59	513	0	0	0
T65	501	0	0	0
T66	493	0	0	0
T67	515	0	0	0
T68	506	0	0	0
T153	0	2	0	0
T154	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T159	0	1	0	0
T160	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T7,T11,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T7,T11,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T7,T11,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T11
1	0	Covered	T5,T6,T13
1	1	Covered	T7,T11,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T11,T12
0	1	Covered	T161
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T11,T12
0	1	Covered	T33,T35,T40
1	0	Covered	T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T11,T12
1	-	Covered	T33,T35,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T11,T12
DetectSt	168	Covered	T7,T11,T12
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T7,T11,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T11,T12
DebounceSt->IdleSt	163	Covered	T78,T159,T162
DetectSt->IdleSt	186	Covered	T161
DetectSt->StableSt	191	Covered	T7,T11,T12
IdleSt->DebounceSt	148	Covered	T7,T11,T12
StableSt->IdleSt	206	Covered	T7,T33,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T11,T12
0	1	Covered	T7,T11,T12
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T11,T12
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T11,T12
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T11,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T159,T162,T163
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T11,T12
DetectSt	-	-	-	-	1	-	-	Covered	T161
DetectSt	-	-	-	-	0	1	-	Covered	T7,T11,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T33,T35,T40
StableSt	-	-	-	-	-	-	0	Covered	T7,T11,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7712811	114	0	0
CntIncr_A	7712811	87668	0	0
CntNoWrap_A	7712811	7041890	0	0
DetectStDropOut_A	7712811	1	0	0
DetectedOut_A	7712811	5081	0	0
DetectedPulseOut_A	7712811	54	0	0
DisabledIdleSt_A	7712811	6791839	0	0
DisabledNoDetection_A	7712811	6794200	0	0
EnterDebounceSt_A	7712811	59	0	0
EnterDetectSt_A	7712811	55	0	0
EnterStableSt_A	7712811	54	0	0
PulseIsPulse_A	7712811	54	0	0
StayInStableSt	7712811	5002	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7712811	2627	0	0
gen_low_level_sva.LowLevelEvent_A	7712811	7044416	0	0
gen_not_sticky_sva.StableStDropOut_A	7712811	28	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	114	0	0
T7	2540	2	0	0
T8	15968	0	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	2	0	0
T12	0	2	0	0
T24	705	0	0	0
T26	5223	0	0	0
T33	0	4	0	0
T35	0	4	0	0
T38	0	6	0	0
T39	0	2	0	0
T40	0	2	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T154	0	4	0	0
T155	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	87668	0	0
T7	2540	75	0	0
T8	15968	0	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	44	0	0
T12	0	59	0	0
T24	705	0	0	0
T26	5223	0	0	0
T33	0	124	0	0
T35	0	66	0	0
T38	0	84684	0	0
T39	0	18	0	0
T40	0	100	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T154	0	92	0	0
T155	0	96	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7041890	0	0
T1	1212	811	0	0
T2	516	115	0	0
T3	499	98	0	0
T4	1063	662	0	0
T5	502	101	0	0
T6	422	21	0	0
T13	494	93	0	0
T14	498	97	0	0
T15	764	363	0	0
T16	507	106	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	1	0	0
T161	608	1	0	0
T164	435	0	0	0
T165	6153	0	0	0
T166	402	0	0	0
T167	689	0	0	0
T168	502	0	0	0
T169	850	0	0	0
T170	1829	0	0	0
T171	605	0	0	0
T172	5009	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	5081	0	0
T7	2540	114	0	0
T8	15968	0	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	230	0	0
T12	0	155	0	0
T24	705	0	0	0
T26	5223	0	0	0
T33	0	189	0	0
T35	0	95	0	0
T38	0	497	0	0
T39	0	40	0	0
T40	0	39	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T154	0	239	0	0
T155	0	234	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	54	0	0
T7	2540	1	0	0
T8	15968	0	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	1	0	0
T12	0	1	0	0
T24	705	0	0	0
T26	5223	0	0	0
T33	0	2	0	0
T35	0	2	0	0
T38	0	3	0	0
T39	0	1	0	0
T40	0	1	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T154	0	2	0	0
T155	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	6791839	0	0
T1	1212	811	0	0
T2	516	115	0	0
T3	499	4	0	0
T4	1063	662	0	0
T5	502	101	0	0
T6	422	21	0	0
T13	494	93	0	0
T14	498	97	0	0
T15	764	363	0	0
T16	507	106	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	6794200	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	4	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	59	0	0
T7	2540	1	0	0
T8	15968	0	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	1	0	0
T12	0	1	0	0
T24	705	0	0	0
T26	5223	0	0	0
T33	0	2	0	0
T35	0	2	0	0
T38	0	3	0	0
T39	0	1	0	0
T40	0	1	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T154	0	2	0	0
T155	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	55	0	0
T7	2540	1	0	0
T8	15968	0	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	1	0	0
T12	0	1	0	0
T24	705	0	0	0
T26	5223	0	0	0
T33	0	2	0	0
T35	0	2	0	0
T38	0	3	0	0
T39	0	1	0	0
T40	0	1	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T154	0	2	0	0
T155	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	54	0	0
T7	2540	1	0	0
T8	15968	0	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	1	0	0
T12	0	1	0	0
T24	705	0	0	0
T26	5223	0	0	0
T33	0	2	0	0
T35	0	2	0	0
T38	0	3	0	0
T39	0	1	0	0
T40	0	1	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T154	0	2	0	0
T155	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	54	0	0
T7	2540	1	0	0
T8	15968	0	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	1	0	0
T12	0	1	0	0
T24	705	0	0	0
T26	5223	0	0	0
T33	0	2	0	0
T35	0	2	0	0
T38	0	3	0	0
T39	0	1	0	0
T40	0	1	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T154	0	2	0	0
T155	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	5002	0	0
T7	2540	112	0	0
T8	15968	0	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	228	0	0
T12	0	153	0	0
T24	705	0	0	0
T26	5223	0	0	0
T33	0	186	0	0
T35	0	93	0	0
T38	0	493	0	0
T39	0	38	0	0
T40	0	38	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T154	0	236	0	0
T155	0	233	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	2627	0	0
T2	516	0	0	0
T3	499	0	0	0
T4	1063	2	0	0
T5	502	4	0	0
T6	422	2	0	0
T13	494	4	0	0
T14	498	5	0	0
T15	764	0	0	0
T16	507	6	0	0
T23	0	14	0	0
T49	404	0	0	0
T50	0	5	0	0
T51	0	2	0	0
T52	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7044416	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	28	0	0
T27	11718	0	0	0
T33	4996	1	0	0
T34	22653	0	0	0
T35	0	2	0	0
T38	0	2	0	0
T40	0	1	0	0
T42	749	0	0	0
T43	3222	0	0	0
T59	513	0	0	0
T65	501	0	0	0
T66	493	0	0	0
T67	515	0	0	0
T68	506	0	0	0
T153	0	2	0	0
T154	0	1	0	0
T155	0	1	0	0
T173	0	1	0	0
T174	0	2	0	0
T175	0	1	0	0