Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T3,T4,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T3,T4,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T3,T4,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T12
1	0	Covered	T1,T5,T6
1	1	Covered	T3,T4,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T12
0	1	Covered	T176,T177
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T12
0	1	Covered	T4,T39,T156
1	0	Covered	T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T4,T12
1	-	Covered	T4,T39,T156

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T4,T12
DetectSt	168	Covered	T3,T4,T12
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T3,T4,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T4,T12
DebounceSt->IdleSt	163	Covered	T78,T153
DetectSt->IdleSt	186	Covered	T176,T177
DetectSt->StableSt	191	Covered	T3,T4,T12
IdleSt->DebounceSt	148	Covered	T3,T4,T12
StableSt->IdleSt	206	Covered	T4,T35,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T4,T12
0	1	Covered	T3,T4,T12
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T12
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T4,T12
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T4,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T153
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T4,T12
DetectSt	-	-	-	-	1	-	-	Covered	T176,T177
DetectSt	-	-	-	-	0	1	-	Covered	T3,T4,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T39,T156
StableSt	-	-	-	-	-	-	0	Covered	T3,T4,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7712811	78	0	0
CntIncr_A	7712811	2273	0	0
CntNoWrap_A	7712811	7041926	0	0
DetectStDropOut_A	7712811	3	0	0
DetectedOut_A	7712811	2737	0	0
DetectedPulseOut_A	7712811	35	0	0
DisabledIdleSt_A	7712811	6832252	0	0
DisabledNoDetection_A	7712811	6834606	0	0
EnterDebounceSt_A	7712811	40	0	0
EnterDetectSt_A	7712811	38	0	0
EnterStableSt_A	7712811	35	0	0
PulseIsPulse_A	7712811	35	0	0
StayInStableSt	7712811	2681	0	0
gen_high_level_sva.HighLevelEvent_A	7712811	7044416	0	0
gen_not_sticky_sva.StableStDropOut_A	7712811	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	78	0	0
T3	499	2	0	0
T4	1063	4	0	0
T12	0	2	0	0
T14	498	0	0	0
T15	764	0	0	0
T16	507	0	0	0
T23	1885	0	0	0
T35	0	2	0	0
T39	0	4	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T78	0	1	0	0
T153	0	3	0	0
T156	0	2	0	0
T157	0	4	0	0
T178	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	2273	0	0
T3	499	20	0	0
T4	1063	174	0	0
T12	0	59	0	0
T14	498	0	0	0
T15	764	0	0	0
T16	507	0	0	0
T23	1885	0	0	0
T35	0	64	0	0
T39	0	36	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T78	0	19	0	0
T153	0	196	0	0
T156	0	22	0	0
T157	0	116	0	0
T178	0	87	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7041926	0	0
T1	1212	811	0	0
T2	516	115	0	0
T3	499	96	0	0
T4	1063	658	0	0
T5	502	101	0	0
T6	422	21	0	0
T13	494	93	0	0
T14	498	97	0	0
T15	764	363	0	0
T16	507	106	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	3	0	0
T176	703	1	0	0
T177	0	2	0	0
T179	970	0	0	0
T180	636	0	0	0
T181	31780	0	0	0
T182	16113	0	0	0
T183	503	0	0	0
T184	493	0	0	0
T185	1356	0	0	0
T186	491	0	0	0
T187	426	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	2737	0	0
T3	499	44	0	0
T4	1063	180	0	0
T12	0	155	0	0
T14	498	0	0	0
T15	764	0	0	0
T16	507	0	0	0
T23	1885	0	0	0
T35	0	38	0	0
T39	0	46	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T153	0	4	0	0
T156	0	56	0	0
T157	0	288	0	0
T178	0	42	0	0
T188	0	44	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	35	0	0
T3	499	1	0	0
T4	1063	2	0	0
T12	0	1	0	0
T14	498	0	0	0
T15	764	0	0	0
T16	507	0	0	0
T23	1885	0	0	0
T35	0	1	0	0
T39	0	2	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T153	0	1	0	0
T156	0	1	0	0
T157	0	2	0	0
T178	0	1	0	0
T188	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	6832252	0	0
T1	1212	811	0	0
T2	516	115	0	0
T3	499	4	0	0
T4	1063	4	0	0
T5	502	101	0	0
T6	422	21	0	0
T13	494	93	0	0
T14	498	97	0	0
T15	764	363	0	0
T16	507	106	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	6834606	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	4	0	0
T4	1063	4	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	40	0	0
T3	499	1	0	0
T4	1063	2	0	0
T12	0	1	0	0
T14	498	0	0	0
T15	764	0	0	0
T16	507	0	0	0
T23	1885	0	0	0
T35	0	1	0	0
T39	0	2	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T78	0	1	0	0
T153	0	2	0	0
T156	0	1	0	0
T157	0	2	0	0
T178	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	38	0	0
T3	499	1	0	0
T4	1063	2	0	0
T12	0	1	0	0
T14	498	0	0	0
T15	764	0	0	0
T16	507	0	0	0
T23	1885	0	0	0
T35	0	1	0	0
T39	0	2	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T153	0	1	0	0
T156	0	1	0	0
T157	0	2	0	0
T178	0	1	0	0
T188	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	35	0	0
T3	499	1	0	0
T4	1063	2	0	0
T12	0	1	0	0
T14	498	0	0	0
T15	764	0	0	0
T16	507	0	0	0
T23	1885	0	0	0
T35	0	1	0	0
T39	0	2	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T153	0	1	0	0
T156	0	1	0	0
T157	0	2	0	0
T178	0	1	0	0
T188	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	35	0	0
T3	499	1	0	0
T4	1063	2	0	0
T12	0	1	0	0
T14	498	0	0	0
T15	764	0	0	0
T16	507	0	0	0
T23	1885	0	0	0
T35	0	1	0	0
T39	0	2	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T153	0	1	0	0
T156	0	1	0	0
T157	0	2	0	0
T178	0	1	0	0
T188	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	2681	0	0
T3	499	42	0	0
T4	1063	177	0	0
T12	0	153	0	0
T14	498	0	0	0
T15	764	0	0	0
T16	507	0	0	0
T23	1885	0	0	0
T35	0	36	0	0
T39	0	43	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T153	0	3	0	0
T156	0	55	0	0
T157	0	285	0	0
T178	0	40	0	0
T188	0	42	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7044416	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	13	0	0
T4	1063	1	0	0
T16	507	0	0	0
T22	2248	0	0	0
T23	1885	0	0	0
T39	0	1	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T53	403	0	0	0
T54	427	0	0	0
T153	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T189	0	2	0	0
T190	0	1	0	0
T191	0	2	0	0
T192	0	1	0	0
T193	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T4,T11,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T4,T11,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T4,T11,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T11
1	0	Covered	T5,T6,T13
1	1	Covered	T4,T11,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T11,T12
0	1	Covered	T82,T193,T194
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T11,T12
0	1	Covered	T4,T11,T12
1	0	Covered	T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T11,T12
1	-	Covered	T4,T11,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T11,T12
DetectSt	168	Covered	T4,T11,T12
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T4,T11,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T11,T12
DebounceSt->IdleSt	163	Covered	T35,T82,T78
DetectSt->IdleSt	186	Covered	T82,T193,T194
DetectSt->StableSt	191	Covered	T4,T11,T12
IdleSt->DebounceSt	148	Covered	T4,T11,T12
StableSt->IdleSt	206	Covered	T4,T11,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T11,T12
0	1	Covered	T4,T11,T12
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T11,T12
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T11,T12
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T11,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T35,T82,T195
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T11,T12
DetectSt	-	-	-	-	1	-	-	Covered	T82,T193,T194
DetectSt	-	-	-	-	0	1	-	Covered	T4,T11,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T11,T12
StableSt	-	-	-	-	-	-	0	Covered	T4,T11,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7712811	160	0	0
CntIncr_A	7712811	96686	0	0
CntNoWrap_A	7712811	7041844	0	0
DetectStDropOut_A	7712811	3	0	0
DetectedOut_A	7712811	131717	0	0
DetectedPulseOut_A	7712811	75	0	0
DisabledIdleSt_A	7712811	6697349	0	0
DisabledNoDetection_A	7712811	6699700	0	0
EnterDebounceSt_A	7712811	83	0	0
EnterDetectSt_A	7712811	78	0	0
EnterStableSt_A	7712811	75	0	0
PulseIsPulse_A	7712811	75	0	0
StayInStableSt	7712811	131610	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7712811	3083	0	0
gen_low_level_sva.LowLevelEvent_A	7712811	7044416	0	0
gen_not_sticky_sva.StableStDropOut_A	7712811	42	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	160	0	0
T4	1063	4	0	0
T11	0	2	0	0
T12	0	2	0	0
T16	507	0	0	0
T22	2248	0	0	0
T23	1885	0	0	0
T33	0	2	0	0
T35	0	5	0	0
T37	0	4	0	0
T38	0	4	0	0
T40	0	4	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T53	403	0	0	0
T54	427	0	0	0
T81	0	4	0	0
T196	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	96686	0	0
T4	1063	174	0	0
T11	0	44	0	0
T12	0	59	0	0
T16	507	0	0	0
T22	2248	0	0	0
T23	1885	0	0	0
T33	0	62	0	0
T35	0	130	0	0
T37	0	196	0	0
T38	0	56456	0	0
T40	0	200	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T53	403	0	0	0
T54	427	0	0	0
T81	0	58	0	0
T196	0	106	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7041844	0	0
T1	1212	811	0	0
T2	516	115	0	0
T3	499	98	0	0
T4	1063	658	0	0
T5	502	101	0	0
T6	422	21	0	0
T13	494	93	0	0
T14	498	97	0	0
T15	764	363	0	0
T16	507	106	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	3	0	0
T78	5998	0	0	0
T82	8261	1	0	0
T123	2180	0	0	0
T156	681	0	0	0
T157	939	0	0	0
T173	674	0	0	0
T193	0	1	0	0
T194	0	1	0	0
T197	508	0	0	0
T198	991	0	0	0
T199	811	0	0	0
T200	763	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	131717	0	0
T4	1063	85	0	0
T11	0	285	0	0
T12	0	100	0	0
T16	507	0	0	0
T22	2248	0	0	0
T23	1885	0	0	0
T33	0	357	0	0
T35	0	83	0	0
T37	0	409	0	0
T38	0	68543	0	0
T40	0	82	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T53	403	0	0	0
T54	427	0	0	0
T81	0	54	0	0
T196	0	163	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	75	0	0
T4	1063	2	0	0
T11	0	1	0	0
T12	0	1	0	0
T16	507	0	0	0
T22	2248	0	0	0
T23	1885	0	0	0
T33	0	1	0	0
T35	0	2	0	0
T37	0	2	0	0
T38	0	2	0	0
T40	0	2	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T53	403	0	0	0
T54	427	0	0	0
T81	0	2	0	0
T196	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	6697349	0	0
T1	1212	811	0	0
T2	516	115	0	0
T3	499	98	0	0
T4	1063	4	0	0
T5	502	101	0	0
T6	422	21	0	0
T13	494	93	0	0
T14	498	97	0	0
T15	764	363	0	0
T16	507	106	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	6699700	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	4	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	83	0	0
T4	1063	2	0	0
T11	0	1	0	0
T12	0	1	0	0
T16	507	0	0	0
T22	2248	0	0	0
T23	1885	0	0	0
T33	0	1	0	0
T35	0	3	0	0
T37	0	2	0	0
T38	0	2	0	0
T40	0	2	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T53	403	0	0	0
T54	427	0	0	0
T81	0	2	0	0
T196	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	78	0	0
T4	1063	2	0	0
T11	0	1	0	0
T12	0	1	0	0
T16	507	0	0	0
T22	2248	0	0	0
T23	1885	0	0	0
T33	0	1	0	0
T35	0	2	0	0
T37	0	2	0	0
T38	0	2	0	0
T40	0	2	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T53	403	0	0	0
T54	427	0	0	0
T81	0	2	0	0
T196	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	75	0	0
T4	1063	2	0	0
T11	0	1	0	0
T12	0	1	0	0
T16	507	0	0	0
T22	2248	0	0	0
T23	1885	0	0	0
T33	0	1	0	0
T35	0	2	0	0
T37	0	2	0	0
T38	0	2	0	0
T40	0	2	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T53	403	0	0	0
T54	427	0	0	0
T81	0	2	0	0
T196	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	75	0	0
T4	1063	2	0	0
T11	0	1	0	0
T12	0	1	0	0
T16	507	0	0	0
T22	2248	0	0	0
T23	1885	0	0	0
T33	0	1	0	0
T35	0	2	0	0
T37	0	2	0	0
T38	0	2	0	0
T40	0	2	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T53	403	0	0	0
T54	427	0	0	0
T81	0	2	0	0
T196	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	131610	0	0
T4	1063	83	0	0
T11	0	284	0	0
T12	0	99	0	0
T16	507	0	0	0
T22	2248	0	0	0
T23	1885	0	0	0
T33	0	355	0	0
T35	0	81	0	0
T37	0	407	0	0
T38	0	68540	0	0
T40	0	79	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T53	403	0	0	0
T54	427	0	0	0
T81	0	52	0	0
T196	0	160	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	3083	0	0
T2	516	0	0	0
T3	499	1	0	0
T4	1063	2	0	0
T5	502	6	0	0
T6	422	5	0	0
T13	494	4	0	0
T14	498	6	0	0
T15	764	0	0	0
T16	507	6	0	0
T23	0	13	0	0
T49	404	0	0	0
T50	0	5	0	0
T51	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7044416	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	42	0	0
T4	1063	2	0	0
T11	0	1	0	0
T12	0	1	0	0
T16	507	0	0	0
T22	2248	0	0	0
T23	1885	0	0	0
T35	0	2	0	0
T37	0	2	0	0
T38	0	1	0	0
T40	0	1	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T53	403	0	0	0
T54	427	0	0	0
T81	0	2	0	0
T196	0	1	0	0
T201	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T3,T4,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T3,T4,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T3,T4,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T11
1	0	Covered	T1,T5,T6
1	1	Covered	T3,T4,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T11
0	1	Covered	T86,T158
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T11
0	1	Covered	T3,T4,T11
1	0	Covered	T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T4,T11
1	-	Covered	T3,T4,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T4,T11
DetectSt	168	Covered	T3,T4,T11
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T3,T4,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T4,T11
DebounceSt->IdleSt	163	Covered	T78,T174
DetectSt->IdleSt	186	Covered	T86,T158
DetectSt->StableSt	191	Covered	T3,T4,T11
IdleSt->DebounceSt	148	Covered	T3,T4,T11
StableSt->IdleSt	206	Covered	T3,T4,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T4,T11
0	1	Covered	T3,T4,T11
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T11
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T4,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T4,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T174
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T4,T11
DetectSt	-	-	-	-	1	-	-	Covered	T86,T158
DetectSt	-	-	-	-	0	1	-	Covered	T3,T4,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T4,T11
StableSt	-	-	-	-	-	-	0	Covered	T3,T4,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7712811	118	0	0
CntIncr_A	7712811	33701	0	0
CntNoWrap_A	7712811	7041886	0	0
DetectStDropOut_A	7712811	2	0	0
DetectedOut_A	7712811	6779	0	0
DetectedPulseOut_A	7712811	56	0	0
DisabledIdleSt_A	7712811	6795131	0	0
DisabledNoDetection_A	7712811	6797491	0	0
EnterDebounceSt_A	7712811	60	0	0
EnterDetectSt_A	7712811	58	0	0
EnterStableSt_A	7712811	56	0	0
PulseIsPulse_A	7712811	56	0	0
StayInStableSt	7712811	6699	0	0
gen_high_level_sva.HighLevelEvent_A	7712811	7044416	0	0
gen_not_sticky_sva.StableStDropOut_A	7712811	31	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	118	0	0
T3	499	2	0	0
T4	1063	4	0	0
T11	0	4	0	0
T12	0	2	0	0
T14	498	0	0	0
T15	764	0	0	0
T16	507	0	0	0
T23	1885	0	0	0
T33	0	2	0	0
T38	0	2	0	0
T40	0	2	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T86	0	4	0	0
T196	0	2	0	0
T201	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	33701	0	0
T3	499	20	0	0
T4	1063	174	0	0
T11	0	88	0	0
T12	0	59	0	0
T14	498	0	0	0
T15	764	0	0	0
T16	507	0	0	0
T23	1885	0	0	0
T33	0	62	0	0
T38	0	28228	0	0
T40	0	100	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T86	0	32	0	0
T196	0	53	0	0
T201	0	70	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7041886	0	0
T1	1212	811	0	0
T2	516	115	0	0
T3	499	96	0	0
T4	1063	658	0	0
T5	502	101	0	0
T6	422	21	0	0
T13	494	93	0	0
T14	498	97	0	0
T15	764	363	0	0
T16	507	106	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	2	0	0
T72	9440	0	0	0
T74	2777	0	0	0
T86	2408	1	0	0
T158	0	1	0	0
T201	20515	0	0	0
T202	493	0	0	0
T203	38146	0	0	0
T204	524	0	0	0
T205	441	0	0	0
T206	30715	0	0	0
T207	489	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	6779	0	0
T3	499	4	0	0
T4	1063	124	0	0
T11	0	209	0	0
T12	0	316	0	0
T14	498	0	0	0
T15	764	0	0	0
T16	507	0	0	0
T23	1885	0	0	0
T33	0	42	0	0
T38	0	42	0	0
T40	0	242	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T86	0	39	0	0
T196	0	285	0	0
T201	0	65	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	56	0	0
T3	499	1	0	0
T4	1063	2	0	0
T11	0	2	0	0
T12	0	1	0	0
T14	498	0	0	0
T15	764	0	0	0
T16	507	0	0	0
T23	1885	0	0	0
T33	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T86	0	1	0	0
T196	0	1	0	0
T201	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	6795131	0	0
T1	1212	811	0	0
T2	516	115	0	0
T3	499	4	0	0
T4	1063	4	0	0
T5	502	101	0	0
T6	422	21	0	0
T13	494	93	0	0
T14	498	97	0	0
T15	764	363	0	0
T16	507	106	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	6797491	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	4	0	0
T4	1063	4	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	60	0	0
T3	499	1	0	0
T4	1063	2	0	0
T11	0	2	0	0
T12	0	1	0	0
T14	498	0	0	0
T15	764	0	0	0
T16	507	0	0	0
T23	1885	0	0	0
T33	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T86	0	2	0	0
T196	0	1	0	0
T201	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	58	0	0
T3	499	1	0	0
T4	1063	2	0	0
T11	0	2	0	0
T12	0	1	0	0
T14	498	0	0	0
T15	764	0	0	0
T16	507	0	0	0
T23	1885	0	0	0
T33	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T86	0	2	0	0
T196	0	1	0	0
T201	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	56	0	0
T3	499	1	0	0
T4	1063	2	0	0
T11	0	2	0	0
T12	0	1	0	0
T14	498	0	0	0
T15	764	0	0	0
T16	507	0	0	0
T23	1885	0	0	0
T33	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T86	0	1	0	0
T196	0	1	0	0
T201	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	56	0	0
T3	499	1	0	0
T4	1063	2	0	0
T11	0	2	0	0
T12	0	1	0	0
T14	498	0	0	0
T15	764	0	0	0
T16	507	0	0	0
T23	1885	0	0	0
T33	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T86	0	1	0	0
T196	0	1	0	0
T201	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	6699	0	0
T3	499	3	0	0
T4	1063	122	0	0
T11	0	206	0	0
T12	0	314	0	0
T14	498	0	0	0
T15	764	0	0	0
T16	507	0	0	0
T23	1885	0	0	0
T33	0	41	0	0
T38	0	41	0	0
T40	0	241	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T86	0	37	0	0
T196	0	283	0	0
T201	0	64	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7044416	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	31	0	0
T3	499	1	0	0
T4	1063	2	0	0
T11	0	1	0	0
T14	498	0	0	0
T15	764	0	0	0
T16	507	0	0	0
T23	1885	0	0	0
T33	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T82	0	1	0	0
T155	0	1	0	0
T201	0	1	0	0
T208	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T3,T4,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T3,T4,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T3,T4,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T5,T6
1	1	Covered	T3,T4,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T11
0	1	Covered	T4,T81
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T11
0	1	Covered	T11,T86,T158
1	0	Covered	T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T4,T11
1	-	Covered	T11,T86,T158

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T4,T11
DetectSt	168	Covered	T3,T4,T11
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T3,T4,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T4,T11
DebounceSt->IdleSt	163	Covered	T82,T78,T163
DetectSt->IdleSt	186	Covered	T4,T81
DetectSt->StableSt	191	Covered	T3,T4,T11
IdleSt->DebounceSt	148	Covered	T3,T4,T11
StableSt->IdleSt	206	Covered	T11,T35,T86

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T4,T11
0	1	Covered	T3,T4,T11
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T11
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T4,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T4,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T82,T163
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T4,T11
DetectSt	-	-	-	-	1	-	-	Covered	T4,T81
DetectSt	-	-	-	-	0	1	-	Covered	T3,T4,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T86,T158
StableSt	-	-	-	-	-	-	0	Covered	T3,T4,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7712811	73	0	0
CntIncr_A	7712811	68693	0	0
CntNoWrap_A	7712811	7041931	0	0
DetectStDropOut_A	7712811	2	0	0
DetectedOut_A	7712811	2088	0	0
DetectedPulseOut_A	7712811	33	0	0
DisabledIdleSt_A	7712811	6742055	0	0
DisabledNoDetection_A	7712811	6744413	0	0
EnterDebounceSt_A	7712811	38	0	0
EnterDetectSt_A	7712811	35	0	0
EnterStableSt_A	7712811	33	0	0
PulseIsPulse_A	7712811	33	0	0
StayInStableSt	7712811	2035	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7712811	6597	0	0
gen_low_level_sva.LowLevelEvent_A	7712811	7044416	0	0
gen_not_sticky_sva.StableStDropOut_A	7712811	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	73	0	0
T3	499	2	0	0
T4	1063	4	0	0
T11	0	2	0	0
T14	498	0	0	0
T15	764	0	0	0
T16	507	0	0	0
T23	1885	0	0	0
T35	0	2	0	0
T40	0	2	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T81	0	2	0	0
T86	0	2	0	0
T110	0	2	0	0
T154	0	2	0	0
T208	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	68693	0	0
T3	499	20	0	0
T4	1063	174	0	0
T11	0	44	0	0
T14	498	0	0	0
T15	764	0	0	0
T16	507	0	0	0
T23	1885	0	0	0
T35	0	33	0	0
T40	0	100	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T81	0	29	0	0
T86	0	16	0	0
T110	0	77	0	0
T154	0	46	0	0
T208	0	41	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7041931	0	0
T1	1212	811	0	0
T2	516	115	0	0
T3	499	96	0	0
T4	1063	658	0	0
T5	502	101	0	0
T6	422	21	0	0
T13	494	93	0	0
T14	498	97	0	0
T15	764	363	0	0
T16	507	106	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	2	0	0
T4	1063	1	0	0
T16	507	0	0	0
T22	2248	0	0	0
T23	1885	0	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T53	403	0	0	0
T54	427	0	0	0
T81	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	2088	0	0
T3	499	44	0	0
T4	1063	179	0	0
T11	0	16	0	0
T14	498	0	0	0
T15	764	0	0	0
T16	507	0	0	0
T23	1885	0	0	0
T35	0	39	0	0
T40	0	41	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T86	0	68	0	0
T110	0	41	0	0
T154	0	108	0	0
T156	0	162	0	0
T208	0	85	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	33	0	0
T3	499	1	0	0
T4	1063	1	0	0
T11	0	1	0	0
T14	498	0	0	0
T15	764	0	0	0
T16	507	0	0	0
T23	1885	0	0	0
T35	0	1	0	0
T40	0	1	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T86	0	1	0	0
T110	0	1	0	0
T154	0	1	0	0
T156	0	1	0	0
T208	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	6742055	0	0
T1	1212	811	0	0
T2	516	3	0	0
T3	499	4	0	0
T4	1063	4	0	0
T5	502	101	0	0
T6	422	21	0	0
T13	494	93	0	0
T14	498	97	0	0
T15	764	363	0	0
T16	507	106	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	6744413	0	0
T1	1212	812	0	0
T2	516	3	0	0
T3	499	4	0	0
T4	1063	4	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	38	0	0
T3	499	1	0	0
T4	1063	2	0	0
T11	0	1	0	0
T14	498	0	0	0
T15	764	0	0	0
T16	507	0	0	0
T23	1885	0	0	0
T35	0	1	0	0
T40	0	1	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T81	0	1	0	0
T86	0	1	0	0
T110	0	1	0	0
T154	0	1	0	0
T208	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	35	0	0
T3	499	1	0	0
T4	1063	2	0	0
T11	0	1	0	0
T14	498	0	0	0
T15	764	0	0	0
T16	507	0	0	0
T23	1885	0	0	0
T35	0	1	0	0
T40	0	1	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T81	0	1	0	0
T86	0	1	0	0
T110	0	1	0	0
T154	0	1	0	0
T208	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	33	0	0
T3	499	1	0	0
T4	1063	1	0	0
T11	0	1	0	0
T14	498	0	0	0
T15	764	0	0	0
T16	507	0	0	0
T23	1885	0	0	0
T35	0	1	0	0
T40	0	1	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T86	0	1	0	0
T110	0	1	0	0
T154	0	1	0	0
T156	0	1	0	0
T208	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	33	0	0
T3	499	1	0	0
T4	1063	1	0	0
T11	0	1	0	0
T14	498	0	0	0
T15	764	0	0	0
T16	507	0	0	0
T23	1885	0	0	0
T35	0	1	0	0
T40	0	1	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T86	0	1	0	0
T110	0	1	0	0
T154	0	1	0	0
T156	0	1	0	0
T208	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	2035	0	0
T3	499	42	0	0
T4	1063	177	0	0
T11	0	15	0	0
T14	498	0	0	0
T15	764	0	0	0
T16	507	0	0	0
T23	1885	0	0	0
T35	0	37	0	0
T40	0	39	0	0
T49	404	0	0	0
T50	465	0	0	0
T51	425	0	0	0
T52	447	0	0	0
T86	0	67	0	0
T110	0	39	0	0
T154	0	106	0	0
T156	0	160	0	0
T208	0	83	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	6597	0	0
T1	1212	8	0	0
T2	516	0	0	0
T3	499	1	0	0
T4	1063	2	0	0
T5	502	5	0	0
T6	422	1	0	0
T13	494	8	0	0
T14	498	7	0	0
T15	764	0	0	0
T16	507	5	0	0
T23	0	14	0	0
T50	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7044416	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	12	0	0
T11	824	1	0	0
T12	784	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T32	504	0	0	0
T41	8348	0	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T86	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T158	0	3	0	0
T190	0	1	0	0
T192	0	1	0	0
T209	0	1	0	0
T210	0	1	0	0
T211	0	1	0	0
T212	403	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T5,T6,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T5,T6,T13
1	1	Covered	T5,T6,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T7,T33,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T7,T33,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T33,T35,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T33,T35
1	0	Covered	T5,T6,T13
1	1	Covered	T7,T33,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T33,T35,T37
0	1	Covered	T81
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T33,T35,T37
0	1	Covered	T35,T37,T38
1	0	Covered	T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T33,T35,T37
1	-	Covered	T35,T37,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T33,T35
DetectSt	168	Covered	T33,T35,T37
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T33,T35,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T33,T35,T37
DebounceSt->IdleSt	163	Covered	T7,T38,T39
DetectSt->IdleSt	186	Covered	T81
DetectSt->StableSt	191	Covered	T33,T35,T37
IdleSt->DebounceSt	148	Covered	T7,T33,T35
StableSt->IdleSt	206	Covered	T33,T35,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T33,T35
0	1	Covered	T7,T33,T35
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T33,T35,T37
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T33,T35
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T33,T35,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T38,T39
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T33,T35
DetectSt	-	-	-	-	1	-	-	Covered	T81
DetectSt	-	-	-	-	0	1	-	Covered	T33,T35,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T35,T37,T38
StableSt	-	-	-	-	-	-	0	Covered	T33,T35,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7712811	117	0	0
CntIncr_A	7712811	92206	0	0
CntNoWrap_A	7712811	7041887	0	0
DetectStDropOut_A	7712811	1	0	0
DetectedOut_A	7712811	108967	0	0
DetectedPulseOut_A	7712811	54	0	0
DisabledIdleSt_A	7712811	6803797	0	0
DisabledNoDetection_A	7712811	6806157	0	0
EnterDebounceSt_A	7712811	62	0	0
EnterDetectSt_A	7712811	55	0	0
EnterStableSt_A	7712811	54	0	0
PulseIsPulse_A	7712811	54	0	0
StayInStableSt	7712811	108889	0	0
gen_high_level_sva.HighLevelEvent_A	7712811	7044416	0	0
gen_not_sticky_sva.StableStDropOut_A	7712811	29	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	117	0	0
T7	2540	1	0	0
T8	15968	0	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T26	5223	0	0	0
T33	0	2	0	0
T35	0	4	0	0
T37	0	4	0	0
T38	0	3	0	0
T39	0	3	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T78	0	1	0	0
T81	0	4	0	0
T155	0	2	0	0
T156	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	92206	0	0
T7	2540	75	0	0
T8	15968	0	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T26	5223	0	0	0
T33	0	62	0	0
T35	0	66	0	0
T37	0	196	0	0
T38	0	56456	0	0
T39	0	96	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T78	0	19	0	0
T81	0	58	0	0
T155	0	96	0	0
T156	0	44	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7041887	0	0
T1	1212	811	0	0
T2	516	115	0	0
T3	499	98	0	0
T4	1063	662	0	0
T5	502	101	0	0
T6	422	21	0	0
T13	494	93	0	0
T14	498	97	0	0
T15	764	363	0	0
T16	507	106	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	1	0	0
T39	14703	0	0	0
T69	21309	0	0	0
T81	731	1	0	0
T93	11625	0	0	0
T213	431	0	0	0
T214	951	0	0	0
T215	422	0	0	0
T216	1134	0	0	0
T217	505	0	0	0
T218	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	108967	0	0
T27	11718	0	0	0
T33	4996	235	0	0
T34	22653	0	0	0
T35	0	146	0	0
T37	0	114	0	0
T38	0	47500	0	0
T39	0	46	0	0
T42	749	0	0	0
T43	3222	0	0	0
T59	513	0	0	0
T65	501	0	0	0
T66	493	0	0	0
T67	515	0	0	0
T68	506	0	0	0
T81	0	47	0	0
T155	0	137	0	0
T156	0	66	0	0
T158	0	454	0	0
T219	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	54	0	0
T27	11718	0	0	0
T33	4996	1	0	0
T34	22653	0	0	0
T35	0	2	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	749	0	0	0
T43	3222	0	0	0
T59	513	0	0	0
T65	501	0	0	0
T66	493	0	0	0
T67	515	0	0	0
T68	506	0	0	0
T81	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T158	0	6	0	0
T219	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	6803797	0	0
T1	1212	811	0	0
T2	516	115	0	0
T3	499	98	0	0
T4	1063	662	0	0
T5	502	101	0	0
T6	422	21	0	0
T13	494	93	0	0
T14	498	97	0	0
T15	764	363	0	0
T16	507	106	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	6806157	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	62	0	0
T7	2540	1	0	0
T8	15968	0	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T26	5223	0	0	0
T33	0	1	0	0
T35	0	2	0	0
T37	0	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T78	0	1	0	0
T81	0	2	0	0
T155	0	1	0	0
T156	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	55	0	0
T27	11718	0	0	0
T33	4996	1	0	0
T34	22653	0	0	0
T35	0	2	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	749	0	0	0
T43	3222	0	0	0
T59	513	0	0	0
T65	501	0	0	0
T66	493	0	0	0
T67	515	0	0	0
T68	506	0	0	0
T81	0	2	0	0
T155	0	1	0	0
T156	0	1	0	0
T158	0	6	0	0
T219	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	54	0	0
T27	11718	0	0	0
T33	4996	1	0	0
T34	22653	0	0	0
T35	0	2	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	749	0	0	0
T43	3222	0	0	0
T59	513	0	0	0
T65	501	0	0	0
T66	493	0	0	0
T67	515	0	0	0
T68	506	0	0	0
T81	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T158	0	6	0	0
T219	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	54	0	0
T27	11718	0	0	0
T33	4996	1	0	0
T34	22653	0	0	0
T35	0	2	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	749	0	0	0
T43	3222	0	0	0
T59	513	0	0	0
T65	501	0	0	0
T66	493	0	0	0
T67	515	0	0	0
T68	506	0	0	0
T81	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T158	0	6	0	0
T219	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	108889	0	0
T27	11718	0	0	0
T33	4996	233	0	0
T34	22653	0	0	0
T35	0	144	0	0
T37	0	111	0	0
T38	0	47499	0	0
T39	0	45	0	0
T42	749	0	0	0
T43	3222	0	0	0
T59	513	0	0	0
T65	501	0	0	0
T66	493	0	0	0
T67	515	0	0	0
T68	506	0	0	0
T81	0	45	0	0
T155	0	135	0	0
T156	0	65	0	0
T158	0	445	0	0
T219	0	41	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7044416	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	29	0	0
T35	17173	2	0	0
T37	21795	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	894	0	0	0
T44	21769	0	0	0
T87	0	1	0	0
T156	0	1	0	0
T158	0	3	0	0
T174	0	1	0	0
T175	0	1	0	0
T219	0	1	0	0
T220	492	0	0	0
T221	413	0	0	0
T222	411	0	0	0
T223	422	0	0	0
T224	407	0	0	0
T225	405	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T13
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T13
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T11,T12,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T11,T12,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T11,T12,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T12
1	0	Covered	T5,T6,T13
1	1	Covered	T11,T12,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T35
0	1	Covered	T158
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T35
0	1	Covered	T11,T81,T196
1	0	Covered	T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T12,T35
1	-	Covered	T11,T81,T196

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T12,T35
DetectSt	168	Covered	T11,T12,T35
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T11,T12,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T12,T35
DebounceSt->IdleSt	163	Covered	T82,T78
DetectSt->IdleSt	186	Covered	T158
DetectSt->StableSt	191	Covered	T11,T12,T35
IdleSt->DebounceSt	148	Covered	T11,T12,T35
StableSt->IdleSt	206	Covered	T11,T35,T81

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T12,T35
0	1	Covered	T11,T12,T35
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T35
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T12,T35
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T78
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T12,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T82
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T12,T35
DetectSt	-	-	-	-	1	-	-	Covered	T158
DetectSt	-	-	-	-	0	1	-	Covered	T11,T12,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T81,T196
StableSt	-	-	-	-	-	-	0	Covered	T11,T12,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7712811	92	0	0
CntIncr_A	7712811	34546	0	0
CntNoWrap_A	7712811	7041912	0	0
DetectStDropOut_A	7712811	1	0	0
DetectedOut_A	7712811	54537	0	0
DetectedPulseOut_A	7712811	44	0	0
DisabledIdleSt_A	7712811	6658482	0	0
DisabledNoDetection_A	7712811	6660830	0	0
EnterDebounceSt_A	7712811	47	0	0
EnterDetectSt_A	7712811	45	0	0
EnterStableSt_A	7712811	44	0	0
PulseIsPulse_A	7712811	44	0	0
StayInStableSt	7712811	54474	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7712811	6308	0	0
gen_low_level_sva.LowLevelEvent_A	7712811	7044416	0	0
gen_not_sticky_sva.StableStDropOut_A	7712811	24	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	92	0	0
T11	824	4	0	0
T12	784	2	0	0
T24	705	0	0	0
T25	654	0	0	0
T32	504	0	0	0
T35	0	2	0	0
T40	0	2	0	0
T41	8348	0	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T78	0	1	0	0
T81	0	2	0	0
T82	0	1	0	0
T154	0	2	0	0
T156	0	4	0	0
T196	0	4	0	0
T212	403	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	34546	0	0
T11	824	88	0	0
T12	784	59	0	0
T24	705	0	0	0
T25	654	0	0	0
T32	504	0	0	0
T35	0	64	0	0
T40	0	100	0	0
T41	8348	0	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T78	0	19	0	0
T81	0	29	0	0
T82	0	54	0	0
T154	0	46	0	0
T156	0	44	0	0
T196	0	106	0	0
T212	403	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7041912	0	0
T1	1212	811	0	0
T2	516	115	0	0
T3	499	98	0	0
T4	1063	662	0	0
T5	502	101	0	0
T6	422	21	0	0
T13	494	93	0	0
T14	498	97	0	0
T15	764	363	0	0
T16	507	106	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	1	0	0
T85	29484	0	0	0
T158	23441	1	0	0
T219	9205	0	0	0
T226	510	0	0	0
T227	489	0	0	0
T228	405	0	0	0
T229	405	0	0	0
T230	204719	0	0	0
T231	426	0	0	0
T232	23788	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	54537	0	0
T11	824	142	0	0
T12	784	45	0	0
T24	705	0	0	0
T25	654	0	0	0
T32	504	0	0	0
T35	0	37	0	0
T40	0	41	0	0
T41	8348	0	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T81	0	73	0	0
T154	0	95	0	0
T156	0	127	0	0
T157	0	83	0	0
T158	0	10	0	0
T196	0	70	0	0
T212	403	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	44	0	0
T11	824	2	0	0
T12	784	1	0	0
T24	705	0	0	0
T25	654	0	0	0
T32	504	0	0	0
T35	0	1	0	0
T40	0	1	0	0
T41	8348	0	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T81	0	1	0	0
T154	0	1	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	2	0	0
T196	0	2	0	0
T212	403	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	6658482	0	0
T1	1212	811	0	0
T2	516	115	0	0
T3	499	4	0	0
T4	1063	662	0	0
T5	502	101	0	0
T6	422	21	0	0
T13	494	93	0	0
T14	498	97	0	0
T15	764	363	0	0
T16	507	106	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	6660830	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	4	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	47	0	0
T11	824	2	0	0
T12	784	1	0	0
T24	705	0	0	0
T25	654	0	0	0
T32	504	0	0	0
T35	0	1	0	0
T40	0	1	0	0
T41	8348	0	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T78	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T154	0	1	0	0
T156	0	2	0	0
T196	0	2	0	0
T212	403	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	45	0	0
T11	824	2	0	0
T12	784	1	0	0
T24	705	0	0	0
T25	654	0	0	0
T32	504	0	0	0
T35	0	1	0	0
T40	0	1	0	0
T41	8348	0	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T81	0	1	0	0
T154	0	1	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	3	0	0
T196	0	2	0	0
T212	403	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	44	0	0
T11	824	2	0	0
T12	784	1	0	0
T24	705	0	0	0
T25	654	0	0	0
T32	504	0	0	0
T35	0	1	0	0
T40	0	1	0	0
T41	8348	0	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T81	0	1	0	0
T154	0	1	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	2	0	0
T196	0	2	0	0
T212	403	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	44	0	0
T11	824	2	0	0
T12	784	1	0	0
T24	705	0	0	0
T25	654	0	0	0
T32	504	0	0	0
T35	0	1	0	0
T40	0	1	0	0
T41	8348	0	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T81	0	1	0	0
T154	0	1	0	0
T156	0	2	0	0
T157	0	2	0	0
T158	0	2	0	0
T196	0	2	0	0
T212	403	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	54474	0	0
T11	824	139	0	0
T12	784	43	0	0
T24	705	0	0	0
T25	654	0	0	0
T32	504	0	0	0
T35	0	35	0	0
T40	0	39	0	0
T41	8348	0	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T81	0	72	0	0
T154	0	94	0	0
T156	0	124	0	0
T157	0	80	0	0
T158	0	8	0	0
T196	0	67	0	0
T212	403	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	6308	0	0
T2	516	0	0	0
T3	499	0	0	0
T4	1063	2	0	0
T5	502	5	0	0
T6	422	3	0	0
T13	494	10	0	0
T14	498	5	0	0
T15	764	0	0	0
T16	507	2	0	0
T23	0	13	0	0
T49	404	0	0	0
T50	0	5	0	0
T51	0	2	0	0
T52	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7044416	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	24	0	0
T11	824	1	0	0
T12	784	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T32	504	0	0	0
T41	8348	0	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T81	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	2	0	0
T174	0	1	0	0
T196	0	1	0	0
T212	403	0	0	0
T233	0	1	0	0