Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T8,T26,T27
1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T8,T10,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T8,T10,T26

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T8,T10,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T26,T27
1	0	Covered	T8,T27,T34
1	1	Covered	T8,T10,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T10,T26
0	1	Covered	T26,T94,T96
1	0	Covered	T36,T69,T94

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T10,T27
0	1	Covered	T8,T27,T34
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T10,T27
1	-	Covered	T8,T27,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T10,T26
DetectSt	168	Covered	T8,T10,T26
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T8,T10,T27

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T10,T26
DebounceSt->IdleSt	163	Covered	T78,T269,T270
DetectSt->IdleSt	186	Covered	T26,T36,T69
DetectSt->StableSt	191	Covered	T8,T10,T27
IdleSt->DebounceSt	148	Covered	T8,T10,T26
StableSt->IdleSt	206	Covered	T8,T27,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T8,T10,T26
0	1	Covered	T8,T10,T26
0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T10,T26
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T8,T10,T26
IdleSt	0	-	-	-	-	-	-	Covered	T8,T26,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T10,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T78,T269,T270
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T10,T26
DetectSt	-	-	-	-	1	-	-	Covered	T26,T36,T69
DetectSt	-	-	-	-	0	1	-	Covered	T8,T10,T27
DetectSt	-	-	-	-	0	0	-	Covered	T8,T10,T26
StableSt	-	-	-	-	-	-	1	Covered	T8,T27,T34
StableSt	-	-	-	-	-	-	0	Covered	T8,T10,T27
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7712811	2906	0	0
CntIncr_A	7712811	94747	0	0
CntNoWrap_A	7712811	7039098	0	0
DetectStDropOut_A	7712811	401	0	0
DetectedOut_A	7712811	62868	0	0
DetectedPulseOut_A	7712811	768	0	0
DisabledIdleSt_A	7712811	6598605	0	0
DisabledNoDetection_A	7712811	6600823	0	0
EnterDebounceSt_A	7712811	1460	0	0
EnterDetectSt_A	7712811	1447	0	0
EnterStableSt_A	7712811	768	0	0
PulseIsPulse_A	7712811	768	0	0
StayInStableSt	7712811	61998	0	0
gen_high_event_sva.HighLevelEvent_A	7712811	7044416	0	0
gen_high_level_sva.HighLevelEvent_A	7712811	7044416	0	0
gen_not_sticky_sva.StableStDropOut_A	7712811	666	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	2906	0	0
T8	15968	8	0	0
T9	15697	0	0	0
T10	528	2	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	28	0	0
T27	0	28	0	0
T34	0	44	0	0
T36	0	52	0	0
T46	0	56	0	0
T47	0	2	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T69	0	22	0	0
T70	0	64	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	94747	0	0
T8	15968	220	0	0
T9	15697	0	0	0
T10	528	21	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	720	0	0
T27	0	798	0	0
T34	0	1496	0	0
T36	0	1872	0	0
T46	0	1876	0	0
T47	0	21	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T69	0	901	0	0
T70	0	1504	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7039098	0	0
T1	1212	811	0	0
T2	516	115	0	0
T3	499	98	0	0
T4	1063	662	0	0
T5	502	101	0	0
T6	422	21	0	0
T13	494	93	0	0
T14	498	97	0	0
T15	764	363	0	0
T16	507	106	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	401	0	0
T11	824	0	0	0
T12	784	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	14	0	0
T32	504	0	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T80	0	14	0	0
T84	0	16	0	0
T94	0	21	0	0
T96	0	12	0	0
T98	0	6	0	0
T99	0	18	0	0
T104	0	5	0	0
T106	0	22	0	0
T107	0	9	0	0
T212	403	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	62868	0	0
T8	15968	205	0	0
T9	15697	0	0	0
T10	528	103	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T27	0	318	0	0
T34	0	1771	0	0
T46	0	2096	0	0
T47	0	88	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T70	0	3239	0	0
T71	0	1204	0	0
T72	0	154	0	0
T271	0	953	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	768	0	0
T8	15968	4	0	0
T9	15697	0	0	0
T10	528	1	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T27	0	14	0	0
T34	0	22	0	0
T46	0	28	0	0
T47	0	1	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T70	0	32	0	0
T71	0	26	0	0
T72	0	7	0	0
T271	0	15	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	6598605	0	0
T1	1212	811	0	0
T2	516	115	0	0
T3	499	98	0	0
T4	1063	662	0	0
T5	502	101	0	0
T6	422	21	0	0
T13	494	93	0	0
T14	498	97	0	0
T15	764	363	0	0
T16	507	106	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	6600823	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	1460	0	0
T8	15968	4	0	0
T9	15697	0	0	0
T10	528	1	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	14	0	0
T27	0	14	0	0
T34	0	22	0	0
T36	0	26	0	0
T46	0	28	0	0
T47	0	1	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T69	0	11	0	0
T70	0	32	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	1447	0	0
T8	15968	4	0	0
T9	15697	0	0	0
T10	528	1	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	14	0	0
T27	0	14	0	0
T34	0	22	0	0
T36	0	26	0	0
T46	0	28	0	0
T47	0	1	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T69	0	11	0	0
T70	0	32	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	768	0	0
T8	15968	4	0	0
T9	15697	0	0	0
T10	528	1	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T27	0	14	0	0
T34	0	22	0	0
T46	0	28	0	0
T47	0	1	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T70	0	32	0	0
T71	0	26	0	0
T72	0	7	0	0
T271	0	15	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	768	0	0
T8	15968	4	0	0
T9	15697	0	0	0
T10	528	1	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T27	0	14	0	0
T34	0	22	0	0
T46	0	28	0	0
T47	0	1	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T70	0	32	0	0
T71	0	26	0	0
T72	0	7	0	0
T271	0	15	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	61998	0	0
T8	15968	201	0	0
T9	15697	0	0	0
T10	528	101	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T27	0	304	0	0
T34	0	1743	0	0
T46	0	2068	0	0
T47	0	86	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T70	0	3200	0	0
T71	0	1178	0	0
T72	0	147	0	0
T271	0	938	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7044416	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7044416	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	666	0	0
T8	15968	4	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T27	0	14	0	0
T34	0	16	0	0
T46	0	28	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T70	0	25	0	0
T71	0	26	0	0
T72	0	7	0	0
T78	0	5	0	0
T269	0	7	0	0
T271	0	15	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T8,T9,T10
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T9,T10,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T9,T10,T34

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T9,T10,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T23,T22,T7
1	1	Covered	T9,T10,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T10,T34
0	1	Covered	T90,T92,T39
1	0	Covered	T78,T58

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T10,T34
0	1	Covered	T9,T10,T34
1	0	Covered	T78,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T10,T34
1	-	Covered	T9,T10,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T10,T34
DetectSt	168	Covered	T9,T10,T34
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T9,T10,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T10,T34
DebounceSt->IdleSt	163	Covered	T9,T37,T44
DetectSt->IdleSt	186	Covered	T90,T92,T39
DetectSt->StableSt	191	Covered	T9,T10,T34
IdleSt->DebounceSt	148	Covered	T9,T10,T34
StableSt->IdleSt	206	Covered	T9,T10,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T10,T34
0	1	Covered	T9,T10,T34
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T34
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T10,T34
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T10,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T37,T44
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T10,T34
DetectSt	-	-	-	-	1	-	-	Covered	T90,T92,T39
DetectSt	-	-	-	-	0	1	-	Covered	T9,T10,T34
DetectSt	-	-	-	-	0	0	-	Covered	T9,T10,T34
StableSt	-	-	-	-	-	-	1	Covered	T9,T10,T34
StableSt	-	-	-	-	-	-	0	Covered	T9,T10,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7712811	1056	0	0
CntIncr_A	7712811	53983	0	0
CntNoWrap_A	7712811	7040948	0	0
DetectStDropOut_A	7712811	60	0	0
DetectedOut_A	7712811	16970	0	0
DetectedPulseOut_A	7712811	428	0	0
DisabledIdleSt_A	7712811	6680725	0	0
DisabledNoDetection_A	7712811	6682412	0	0
EnterDebounceSt_A	7712811	565	0	0
EnterDetectSt_A	7712811	492	0	0
EnterStableSt_A	7712811	428	0	0
PulseIsPulse_A	7712811	428	0	0
StayInStableSt	7712811	16516	0	0
gen_high_level_sva.HighLevelEvent_A	7712811	7044416	0	0
gen_not_sticky_sva.StableStDropOut_A	7712811	398	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	1056	0	0
T9	15697	11	0	0
T10	528	2	0	0
T11	824	0	0	0
T12	784	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T34	0	8	0	0
T35	0	4	0	0
T37	0	3	0	0
T44	0	7	0	0
T47	0	2	0	0
T48	0	2	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T64	0	2	0	0
T90	0	17	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	53983	0	0
T9	15697	357	0	0
T10	528	25	0	0
T11	824	0	0	0
T12	784	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T34	0	240	0	0
T35	0	97	0	0
T37	0	160	0	0
T44	0	186	0	0
T47	0	25	0	0
T48	0	25	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T64	0	25	0	0
T90	0	714	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7040948	0	0
T1	1212	811	0	0
T2	516	115	0	0
T3	499	98	0	0
T4	1063	662	0	0
T5	502	101	0	0
T6	422	21	0	0
T13	494	93	0	0
T14	498	97	0	0
T15	764	363	0	0
T16	507	106	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	60	0	0
T38	133052	0	0	0
T39	0	1	0	0
T48	2332	0	0	0
T64	24840	0	0	0
T90	25273	8	0	0
T91	782	0	0	0
T92	0	3	0	0
T93	0	2	0	0
T95	0	11	0	0
T97	0	3	0	0
T100	0	4	0	0
T101	0	9	0	0
T102	0	8	0	0
T105	0	2	0	0
T108	430	0	0	0
T109	504	0	0	0
T110	646	0	0	0
T111	2846	0	0	0
T112	507	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	16970	0	0
T9	15697	45	0	0
T10	528	3	0	0
T11	824	0	0	0
T12	784	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T34	0	210	0	0
T35	0	66	0	0
T37	0	17	0	0
T44	0	148	0	0
T47	0	3	0	0
T48	0	3	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T64	0	3	0	0
T122	0	94	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	428	0	0
T9	15697	5	0	0
T10	528	1	0	0
T11	824	0	0	0
T12	784	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T34	0	4	0	0
T35	0	2	0	0
T37	0	1	0	0
T44	0	3	0	0
T47	0	1	0	0
T48	0	1	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T64	0	1	0	0
T122	0	18	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	6680725	0	0
T1	1212	811	0	0
T2	516	115	0	0
T3	499	98	0	0
T4	1063	662	0	0
T5	502	101	0	0
T6	422	21	0	0
T13	494	93	0	0
T14	498	97	0	0
T15	764	363	0	0
T16	507	106	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	6682412	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	565	0	0
T9	15697	6	0	0
T10	528	1	0	0
T11	824	0	0	0
T12	784	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T34	0	4	0	0
T35	0	2	0	0
T37	0	3	0	0
T44	0	4	0	0
T47	0	1	0	0
T48	0	1	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T64	0	1	0	0
T90	0	9	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	492	0	0
T9	15697	5	0	0
T10	528	1	0	0
T11	824	0	0	0
T12	784	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T34	0	4	0	0
T35	0	2	0	0
T37	0	1	0	0
T44	0	3	0	0
T47	0	1	0	0
T48	0	1	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T64	0	1	0	0
T90	0	8	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	428	0	0
T9	15697	5	0	0
T10	528	1	0	0
T11	824	0	0	0
T12	784	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T34	0	4	0	0
T35	0	2	0	0
T37	0	1	0	0
T44	0	3	0	0
T47	0	1	0	0
T48	0	1	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T64	0	1	0	0
T122	0	18	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	428	0	0
T9	15697	5	0	0
T10	528	1	0	0
T11	824	0	0	0
T12	784	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T34	0	4	0	0
T35	0	2	0	0
T37	0	1	0	0
T44	0	3	0	0
T47	0	1	0	0
T48	0	1	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T64	0	1	0	0
T122	0	18	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	16516	0	0
T9	15697	40	0	0
T10	528	2	0	0
T11	824	0	0	0
T12	784	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T34	0	206	0	0
T35	0	64	0	0
T37	0	16	0	0
T44	0	145	0	0
T47	0	2	0	0
T48	0	2	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T64	0	2	0	0
T122	0	75	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7044416	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	398	0	0
T9	15697	5	0	0
T10	528	1	0	0
T11	824	0	0	0
T12	784	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T34	0	4	0	0
T35	0	2	0	0
T37	0	1	0	0
T44	0	3	0	0
T47	0	1	0	0
T48	0	1	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T64	0	1	0	0
T122	0	17	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T8,T26,T27
1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T8,T26,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T8,T26,T27

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T8,T26,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T26,T27
1	0	Covered	T8,T27,T34
1	1	Covered	T8,T26,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T26,T27
0	1	Covered	T26,T71,T94
1	0	Covered	T71,T94,T272

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T27,T34
0	1	Covered	T8,T27,T34
1	0	Covered	T78,T83,T273

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T27,T34
1	-	Covered	T8,T27,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T26,T27
DetectSt	168	Covered	T8,T26,T27
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T8,T27,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T26,T27
DebounceSt->IdleSt	163	Covered	T78,T269,T270
DetectSt->IdleSt	186	Covered	T26,T71,T94
DetectSt->StableSt	191	Covered	T8,T27,T34
IdleSt->DebounceSt	148	Covered	T8,T26,T27
StableSt->IdleSt	206	Covered	T8,T27,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T8,T26,T27
0	1	Covered	T8,T26,T27
0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T26,T27
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T8,T26,T27
IdleSt	0	-	-	-	-	-	-	Covered	T8,T26,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T26,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T78,T269,T270
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T26,T27
DetectSt	-	-	-	-	1	-	-	Covered	T26,T71,T94
DetectSt	-	-	-	-	0	1	-	Covered	T8,T27,T34
DetectSt	-	-	-	-	0	0	-	Covered	T8,T26,T27
StableSt	-	-	-	-	-	-	1	Covered	T8,T27,T34
StableSt	-	-	-	-	-	-	0	Covered	T8,T27,T34
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7712811	2918	0	0
CntIncr_A	7712811	92156	0	0
CntNoWrap_A	7712811	7039086	0	0
DetectStDropOut_A	7712811	368	0	0
DetectedOut_A	7712811	80887	0	0
DetectedPulseOut_A	7712811	934	0	0
DisabledIdleSt_A	7712811	6587255	0	0
DisabledNoDetection_A	7712811	6589472	0	0
EnterDebounceSt_A	7712811	1477	0	0
EnterDetectSt_A	7712811	1441	0	0
EnterStableSt_A	7712811	934	0	0
PulseIsPulse_A	7712811	934	0	0
StayInStableSt	7712811	79851	0	0
gen_high_event_sva.HighLevelEvent_A	7712811	7044416	0	0
gen_high_level_sva.HighLevelEvent_A	7712811	7044416	0	0
gen_not_sticky_sva.StableStDropOut_A	7712811	817	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	2918	0	0
T8	15968	8	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	20	0	0
T27	0	56	0	0
T34	0	10	0	0
T36	0	52	0	0
T46	0	12	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T69	0	50	0	0
T70	0	32	0	0
T71	0	64	0	0
T72	0	22	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	92156	0	0
T8	15968	332	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	514	0	0
T27	0	1316	0	0
T34	0	250	0	0
T36	0	1170	0	0
T46	0	528	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T69	0	1700	0	0
T70	0	1104	0	0
T71	0	2031	0	0
T72	0	506	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7039086	0	0
T1	1212	811	0	0
T2	516	115	0	0
T3	499	98	0	0
T4	1063	662	0	0
T5	502	101	0	0
T6	422	21	0	0
T13	494	93	0	0
T14	498	97	0	0
T15	764	363	0	0
T16	507	106	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	368	0	0
T11	824	0	0	0
T12	784	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	10	0	0
T32	504	0	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T71	0	18	0	0
T78	0	1	0	0
T84	0	4	0	0
T94	0	18	0	0
T99	0	20	0	0
T104	0	26	0	0
T106	0	7	0	0
T107	0	12	0	0
T212	403	0	0	0
T274	0	8	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	80887	0	0
T8	15968	252	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T27	0	1550	0	0
T34	0	492	0	0
T36	0	2231	0	0
T46	0	81	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T69	0	2800	0	0
T70	0	1867	0	0
T72	0	329	0	0
T96	0	1922	0	0
T271	0	1202	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	934	0	0
T8	15968	4	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T27	0	28	0	0
T34	0	5	0	0
T36	0	26	0	0
T46	0	6	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T69	0	25	0	0
T70	0	16	0	0
T72	0	11	0	0
T96	0	15	0	0
T271	0	25	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	6587255	0	0
T1	1212	811	0	0
T2	516	115	0	0
T3	499	98	0	0
T4	1063	662	0	0
T5	502	101	0	0
T6	422	21	0	0
T13	494	93	0	0
T14	498	97	0	0
T15	764	363	0	0
T16	507	106	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	6589472	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	1477	0	0
T8	15968	4	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	10	0	0
T27	0	28	0	0
T34	0	5	0	0
T36	0	26	0	0
T46	0	6	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T69	0	25	0	0
T70	0	16	0	0
T71	0	32	0	0
T72	0	11	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	1441	0	0
T8	15968	4	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	10	0	0
T27	0	28	0	0
T34	0	5	0	0
T36	0	26	0	0
T46	0	6	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T69	0	25	0	0
T70	0	16	0	0
T71	0	32	0	0
T72	0	11	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	934	0	0
T8	15968	4	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T27	0	28	0	0
T34	0	5	0	0
T36	0	26	0	0
T46	0	6	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T69	0	25	0	0
T70	0	16	0	0
T72	0	11	0	0
T96	0	15	0	0
T271	0	25	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	934	0	0
T8	15968	4	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T27	0	28	0	0
T34	0	5	0	0
T36	0	26	0	0
T46	0	6	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T69	0	25	0	0
T70	0	16	0	0
T72	0	11	0	0
T96	0	15	0	0
T271	0	25	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	79851	0	0
T8	15968	247	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T27	0	1520	0	0
T34	0	487	0	0
T36	0	2202	0	0
T46	0	75	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T69	0	2769	0	0
T70	0	1848	0	0
T72	0	317	0	0
T96	0	1905	0	0
T271	0	1177	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7044416	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7044416	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	817	0	0
T8	15968	3	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T27	0	26	0	0
T34	0	5	0	0
T36	0	23	0	0
T46	0	6	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T69	0	19	0	0
T70	0	13	0	0
T72	0	10	0	0
T96	0	13	0	0
T271	0	25	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T8,T9,T26
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T26
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T8,T9,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T8,T9,T41

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T8,T9,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T41
1	0	Covered	T23,T22,T7
1	1	Covered	T8,T9,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T41
0	1	Covered	T9,T41,T92
1	0	Covered	T78,T58

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T27,T34
0	1	Covered	T8,T27,T34
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T27,T34
1	-	Covered	T8,T27,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T9,T41
DetectSt	168	Covered	T8,T9,T41
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T8,T27,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T9,T41
DebounceSt->IdleSt	163	Covered	T9,T41,T201
DetectSt->IdleSt	186	Covered	T9,T41,T92
DetectSt->StableSt	191	Covered	T8,T27,T34
IdleSt->DebounceSt	148	Covered	T8,T9,T41
StableSt->IdleSt	206	Covered	T8,T27,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T9,T41
0	1	Covered	T8,T9,T41
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T41
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T9,T41
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T9,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T41,T201
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T9,T41
DetectSt	-	-	-	-	1	-	-	Covered	T9,T41,T92
DetectSt	-	-	-	-	0	1	-	Covered	T8,T27,T34
DetectSt	-	-	-	-	0	0	-	Covered	T8,T9,T41
StableSt	-	-	-	-	-	-	1	Covered	T8,T27,T34
StableSt	-	-	-	-	-	-	0	Covered	T8,T27,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7712811	947	0	0
CntIncr_A	7712811	50428	0	0
CntNoWrap_A	7712811	7041057	0	0
DetectStDropOut_A	7712811	95	0	0
DetectedOut_A	7712811	16004	0	0
DetectedPulseOut_A	7712811	351	0	0
DisabledIdleSt_A	7712811	6667545	0	0
DisabledNoDetection_A	7712811	6669293	0	0
EnterDebounceSt_A	7712811	498	0	0
EnterDetectSt_A	7712811	450	0	0
EnterStableSt_A	7712811	351	0	0
PulseIsPulse_A	7712811	351	0	0
StayInStableSt	7712811	15615	0	0
gen_high_level_sva.HighLevelEvent_A	7712811	7044416	0	0
gen_not_sticky_sva.StableStDropOut_A	7712811	310	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	947	0	0
T8	15968	2	0	0
T9	15697	5	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T27	0	4	0	0
T34	0	2	0	0
T35	0	6	0	0
T37	0	2	0	0
T41	0	18	0	0
T44	0	12	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T92	0	2	0	0
T122	0	10	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	50428	0	0
T8	15968	69	0	0
T9	15697	190	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T27	0	80	0	0
T34	0	69	0	0
T35	0	267	0	0
T37	0	66	0	0
T41	0	708	0	0
T44	0	564	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T92	0	163	0	0
T122	0	1339	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7041057	0	0
T1	1212	811	0	0
T2	516	115	0	0
T3	499	98	0	0
T4	1063	662	0	0
T5	502	101	0	0
T6	422	21	0	0
T13	494	93	0	0
T14	498	97	0	0
T15	764	363	0	0
T16	507	106	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	95	0	0
T9	15697	2	0	0
T10	528	0	0	0
T11	824	0	0	0
T12	784	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T41	0	7	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T85	0	2	0	0
T87	0	2	0	0
T92	0	1	0	0
T122	0	5	0	0
T201	0	2	0	0
T206	0	5	0	0
T275	0	6	0	0
T276	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	16004	0	0
T8	15968	79	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T27	0	90	0	0
T34	0	44	0	0
T35	0	140	0	0
T36	0	176	0	0
T37	0	40	0	0
T39	0	44	0	0
T44	0	41	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T69	0	337	0	0
T93	0	88	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	351	0	0
T8	15968	1	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T27	0	2	0	0
T34	0	1	0	0
T35	0	3	0	0
T36	0	3	0	0
T37	0	1	0	0
T39	0	1	0	0
T44	0	6	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T69	0	6	0	0
T93	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	6667545	0	0
T1	1212	811	0	0
T2	516	115	0	0
T3	499	98	0	0
T4	1063	662	0	0
T5	502	101	0	0
T6	422	21	0	0
T13	494	93	0	0
T14	498	97	0	0
T15	764	363	0	0
T16	507	106	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	6669293	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	498	0	0
T8	15968	1	0	0
T9	15697	3	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T27	0	2	0	0
T34	0	1	0	0
T35	0	3	0	0
T37	0	1	0	0
T41	0	11	0	0
T44	0	6	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T92	0	1	0	0
T122	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	450	0	0
T8	15968	1	0	0
T9	15697	2	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T27	0	2	0	0
T34	0	1	0	0
T35	0	3	0	0
T37	0	1	0	0
T41	0	8	0	0
T44	0	6	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T92	0	1	0	0
T122	0	5	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	351	0	0
T8	15968	1	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T27	0	2	0	0
T34	0	1	0	0
T35	0	3	0	0
T36	0	3	0	0
T37	0	1	0	0
T39	0	1	0	0
T44	0	6	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T69	0	6	0	0
T93	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	351	0	0
T8	15968	1	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T27	0	2	0	0
T34	0	1	0	0
T35	0	3	0	0
T36	0	3	0	0
T37	0	1	0	0
T39	0	1	0	0
T44	0	6	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T69	0	6	0	0
T93	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	15615	0	0
T8	15968	78	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T27	0	87	0	0
T34	0	43	0	0
T35	0	137	0	0
T36	0	173	0	0
T37	0	39	0	0
T39	0	43	0	0
T44	0	35	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T69	0	327	0	0
T93	0	85	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7044416	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	310	0	0
T8	15968	1	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T27	0	1	0	0
T34	0	1	0	0
T35	0	3	0	0
T36	0	3	0	0
T37	0	1	0	0
T39	0	1	0	0
T44	0	6	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T69	0	2	0	0
T93	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T8,T26,T27
1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T8,T26,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T8,T26,T27

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T8,T26,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T26,T27
1	0	Covered	T8,T27,T34
1	1	Covered	T8,T26,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T26,T27
0	1	Covered	T26,T71,T94
1	0	Covered	T71,T94,T272

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T27,T34
0	1	Covered	T8,T27,T34
1	0	Covered	T277,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T27,T34
1	-	Covered	T8,T27,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T26,T27
DetectSt	168	Covered	T8,T26,T27
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T8,T27,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T26,T27
DebounceSt->IdleSt	163	Covered	T78,T269,T270
DetectSt->IdleSt	186	Covered	T26,T71,T94
DetectSt->StableSt	191	Covered	T8,T27,T34
IdleSt->DebounceSt	148	Covered	T8,T26,T27
StableSt->IdleSt	206	Covered	T8,T27,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T8,T26,T27
0	1	Covered	T8,T26,T27
0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T26,T27
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T8,T26,T27
IdleSt	0	-	-	-	-	-	-	Covered	T8,T26,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T26,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T78,T269,T270
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T26,T27
DetectSt	-	-	-	-	1	-	-	Covered	T26,T71,T94
DetectSt	-	-	-	-	0	1	-	Covered	T8,T27,T34
DetectSt	-	-	-	-	0	0	-	Covered	T8,T26,T27
StableSt	-	-	-	-	-	-	1	Covered	T8,T27,T34
StableSt	-	-	-	-	-	-	0	Covered	T8,T27,T34
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7712811	3380	0	0
CntIncr_A	7712811	113298	0	0
CntNoWrap_A	7712811	7038624	0	0
DetectStDropOut_A	7712811	508	0	0
DetectedOut_A	7712811	77838	0	0
DetectedPulseOut_A	7712811	907	0	0
DisabledIdleSt_A	7712811	6586429	0	0
DisabledNoDetection_A	7712811	6588638	0	0
EnterDebounceSt_A	7712811	1708	0	0
EnterDetectSt_A	7712811	1672	0	0
EnterStableSt_A	7712811	907	0	0
PulseIsPulse_A	7712811	907	0	0
StayInStableSt	7712811	76820	0	0
gen_high_event_sva.HighLevelEvent_A	7712811	7044416	0	0
gen_high_level_sva.HighLevelEvent_A	7712811	7044416	0	0
gen_not_sticky_sva.StableStDropOut_A	7712811	788	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	3380	0	0
T8	15968	44	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	12	0	0
T27	0	52	0	0
T34	0	24	0	0
T36	0	34	0	0
T46	0	54	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T69	0	16	0	0
T70	0	64	0	0
T71	0	30	0	0
T72	0	48	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	113298	0	0
T8	15968	2068	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	307	0	0
T27	0	1534	0	0
T34	0	612	0	0
T36	0	952	0	0
T46	0	2376	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T69	0	432	0	0
T70	0	1440	0	0
T71	0	946	0	0
T72	0	1320	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7038624	0	0
T1	1212	811	0	0
T2	516	115	0	0
T3	499	98	0	0
T4	1063	662	0	0
T5	502	101	0	0
T6	422	21	0	0
T13	494	93	0	0
T14	498	97	0	0
T15	764	363	0	0
T16	507	106	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	508	0	0
T11	824	0	0	0
T12	784	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	6	0	0
T32	504	0	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T71	0	9	0	0
T78	0	1	0	0
T94	0	21	0	0
T98	0	3	0	0
T99	0	8	0	0
T104	0	24	0	0
T212	403	0	0	0
T272	0	10	0	0
T274	0	6	0	0
T278	0	7	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	77838	0	0
T8	15968	2285	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T27	0	989	0	0
T34	0	1164	0	0
T36	0	1663	0	0
T46	0	378	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T69	0	387	0	0
T70	0	3303	0	0
T72	0	1732	0	0
T96	0	1774	0	0
T271	0	444	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	907	0	0
T8	15968	22	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T27	0	26	0	0
T34	0	12	0	0
T36	0	17	0	0
T46	0	27	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T69	0	8	0	0
T70	0	32	0	0
T72	0	24	0	0
T96	0	25	0	0
T271	0	13	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	6586429	0	0
T1	1212	811	0	0
T2	516	115	0	0
T3	499	98	0	0
T4	1063	662	0	0
T5	502	101	0	0
T6	422	21	0	0
T13	494	93	0	0
T14	498	97	0	0
T15	764	363	0	0
T16	507	106	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	6588638	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	1708	0	0
T8	15968	22	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	6	0	0
T27	0	26	0	0
T34	0	12	0	0
T36	0	17	0	0
T46	0	27	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T69	0	8	0	0
T70	0	32	0	0
T71	0	15	0	0
T72	0	24	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	1672	0	0
T8	15968	22	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	6	0	0
T27	0	26	0	0
T34	0	12	0	0
T36	0	17	0	0
T46	0	27	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T69	0	8	0	0
T70	0	32	0	0
T71	0	15	0	0
T72	0	24	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	907	0	0
T8	15968	22	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T27	0	26	0	0
T34	0	12	0	0
T36	0	17	0	0
T46	0	27	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T69	0	8	0	0
T70	0	32	0	0
T72	0	24	0	0
T96	0	25	0	0
T271	0	13	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	907	0	0
T8	15968	22	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T27	0	26	0	0
T34	0	12	0	0
T36	0	17	0	0
T46	0	27	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T69	0	8	0	0
T70	0	32	0	0
T72	0	24	0	0
T96	0	25	0	0
T271	0	13	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	76820	0	0
T8	15968	2260	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T27	0	963	0	0
T34	0	1148	0	0
T36	0	1643	0	0
T46	0	351	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T69	0	379	0	0
T70	0	3264	0	0
T72	0	1708	0	0
T96	0	1747	0	0
T271	0	431	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7044416	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7044416	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	788	0	0
T8	15968	19	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T27	0	26	0	0
T34	0	8	0	0
T36	0	14	0	0
T46	0	27	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T69	0	8	0	0
T70	0	25	0	0
T72	0	24	0	0
T96	0	23	0	0
T271	0	13	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T8,T9,T26
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T26
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T8,T9,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T8,T9,T41

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T8,T9,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T41
1	0	Covered	T23,T22,T7
1	1	Covered	T8,T9,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T34
0	1	Covered	T9,T44,T90
1	0	Covered	T78,T58

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T34,T35
0	1	Covered	T8,T34,T35
1	0	Covered	T78,T79,T80

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T34,T35
1	-	Covered	T8,T34,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T9,T41
DetectSt	168	Covered	T8,T9,T34
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T8,T34,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T9,T34
DebounceSt->IdleSt	163	Covered	T9,T41,T44
DetectSt->IdleSt	186	Covered	T9,T44,T90
DetectSt->StableSt	191	Covered	T8,T34,T35
IdleSt->DebounceSt	148	Covered	T8,T9,T41
StableSt->IdleSt	206	Covered	T8,T34,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T9,T41
0	1	Covered	T8,T9,T41
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T34
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T9,T41
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T9,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T41,T44
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T9,T41
DetectSt	-	-	-	-	1	-	-	Covered	T9,T44,T90
DetectSt	-	-	-	-	0	1	-	Covered	T8,T34,T35
DetectSt	-	-	-	-	0	0	-	Covered	T8,T9,T34
StableSt	-	-	-	-	-	-	1	Covered	T8,T34,T35
StableSt	-	-	-	-	-	-	0	Covered	T8,T34,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7712811	844	0	0
CntIncr_A	7712811	45606	0	0
CntNoWrap_A	7712811	7041160	0	0
DetectStDropOut_A	7712811	89	0	0
DetectedOut_A	7712811	12316	0	0
DetectedPulseOut_A	7712811	303	0	0
DisabledIdleSt_A	7712811	6664915	0	0
DisabledNoDetection_A	7712811	6666642	0	0
EnterDebounceSt_A	7712811	449	0	0
EnterDetectSt_A	7712811	395	0	0
EnterStableSt_A	7712811	303	0	0
PulseIsPulse_A	7712811	303	0	0
StayInStableSt	7712811	11997	0	0
gen_high_level_sva.HighLevelEvent_A	7712811	7044416	0	0
gen_not_sticky_sva.StableStDropOut_A	7712811	280	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	844	0	0
T8	15968	6	0	0
T9	15697	9	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T34	0	8	0	0
T35	0	2	0	0
T36	0	6	0	0
T41	0	1	0	0
T44	0	9	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T90	0	19	0	0
T93	0	6	0	0
T122	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	45606	0	0
T8	15968	186	0	0
T9	15697	332	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T34	0	172	0	0
T35	0	130	0	0
T36	0	222	0	0
T41	0	52	0	0
T44	0	433	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T90	0	796	0	0
T93	0	300	0	0
T122	0	268	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7041160	0	0
T1	1212	811	0	0
T2	516	115	0	0
T3	499	98	0	0
T4	1063	662	0	0
T5	502	101	0	0
T6	422	21	0	0
T13	494	93	0	0
T14	498	97	0	0
T15	764	363	0	0
T16	507	106	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	89	0	0
T9	15697	4	0	0
T10	528	0	0	0
T11	824	0	0	0
T12	784	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T44	0	4	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T90	0	9	0	0
T95	0	8	0	0
T100	0	12	0	0
T122	0	1	0	0
T238	0	10	0	0
T279	0	6	0	0
T280	0	8	0	0
T281	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	12316	0	0
T8	15968	258	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T34	0	282	0	0
T35	0	5	0	0
T36	0	108	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T70	0	285	0	0
T93	0	25	0	0
T196	0	72	0	0
T201	0	9	0	0
T206	0	70	0	0
T275	0	36	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	303	0	0
T8	15968	3	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T34	0	4	0	0
T35	0	1	0	0
T36	0	3	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T70	0	4	0	0
T93	0	3	0	0
T196	0	3	0	0
T201	0	2	0	0
T206	0	10	0	0
T275	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	6664915	0	0
T1	1212	811	0	0
T2	516	115	0	0
T3	499	98	0	0
T4	1063	662	0	0
T5	502	101	0	0
T6	422	21	0	0
T13	494	93	0	0
T14	498	97	0	0
T15	764	363	0	0
T16	507	106	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	6666642	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	449	0	0
T8	15968	3	0	0
T9	15697	5	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T34	0	4	0	0
T35	0	1	0	0
T36	0	3	0	0
T41	0	1	0	0
T44	0	5	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T90	0	10	0	0
T93	0	3	0	0
T122	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	395	0	0
T8	15968	3	0	0
T9	15697	4	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T34	0	4	0	0
T35	0	1	0	0
T36	0	3	0	0
T44	0	4	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T70	0	4	0	0
T90	0	9	0	0
T93	0	3	0	0
T122	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	303	0	0
T8	15968	3	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T34	0	4	0	0
T35	0	1	0	0
T36	0	3	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T70	0	4	0	0
T93	0	3	0	0
T196	0	3	0	0
T201	0	2	0	0
T206	0	10	0	0
T275	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	303	0	0
T8	15968	3	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T34	0	4	0	0
T35	0	1	0	0
T36	0	3	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T70	0	4	0	0
T93	0	3	0	0
T196	0	3	0	0
T201	0	2	0	0
T206	0	10	0	0
T275	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	11997	0	0
T8	15968	255	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T34	0	278	0	0
T35	0	4	0	0
T36	0	105	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T70	0	281	0	0
T93	0	22	0	0
T196	0	69	0	0
T201	0	7	0	0
T206	0	60	0	0
T275	0	34	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7044416	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	280	0	0
T8	15968	3	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T34	0	4	0	0
T35	0	1	0	0
T36	0	3	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T70	0	4	0	0
T93	0	3	0	0
T196	0	3	0	0
T201	0	2	0	0
T206	0	10	0	0
T275	0	2	0	0