Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T8,T26,T27
1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T8,T26,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T8,T26,T27

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T8,T26,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T26,T27
1	0	Covered	T8,T27,T34
1	1	Covered	T8,T26,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T26,T27
0	1	Covered	T26,T36,T71
1	0	Covered	T36,T71,T271

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T27,T34
0	1	Covered	T8,T27,T34
1	0	Covered	T84

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T27,T34
1	-	Covered	T8,T27,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T26,T27
DetectSt	168	Covered	T8,T26,T27
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T8,T27,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T26,T27
DebounceSt->IdleSt	163	Covered	T78,T269,T270
DetectSt->IdleSt	186	Covered	T26,T36,T71
DetectSt->StableSt	191	Covered	T8,T27,T34
IdleSt->DebounceSt	148	Covered	T8,T26,T27
StableSt->IdleSt	206	Covered	T8,T27,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T8,T26,T27
0	1	Covered	T8,T26,T27
0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T26,T27
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T8,T26,T27
IdleSt	0	-	-	-	-	-	-	Covered	T8,T26,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T26,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T78,T269,T270
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T26,T27
DetectSt	-	-	-	-	1	-	-	Covered	T26,T36,T71
DetectSt	-	-	-	-	0	1	-	Covered	T8,T27,T34
DetectSt	-	-	-	-	0	0	-	Covered	T8,T26,T27
StableSt	-	-	-	-	-	-	1	Covered	T8,T27,T34
StableSt	-	-	-	-	-	-	0	Covered	T8,T27,T34
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7712811	3048	0	0
CntIncr_A	7712811	100168	0	0
CntNoWrap_A	7712811	7038956	0	0
DetectStDropOut_A	7712811	411	0	0
DetectedOut_A	7712811	80528	0	0
DetectedPulseOut_A	7712811	862	0	0
DisabledIdleSt_A	7712811	6582180	0	0
DisabledNoDetection_A	7712811	6584363	0	0
EnterDebounceSt_A	7712811	1537	0	0
EnterDetectSt_A	7712811	1512	0	0
EnterStableSt_A	7712811	862	0	0
PulseIsPulse_A	7712811	862	0	0
StayInStableSt	7712811	79529	0	0
gen_high_event_sva.HighLevelEvent_A	7712811	7044416	0	0
gen_high_level_sva.HighLevelEvent_A	7712811	7044416	0	0
gen_not_sticky_sva.StableStDropOut_A	7712811	722	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	3048	0	0
T8	15968	20	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	28	0	0
T27	0	24	0	0
T34	0	16	0	0
T36	0	56	0	0
T46	0	12	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T69	0	22	0	0
T70	0	64	0	0
T71	0	16	0	0
T72	0	32	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	100168	0	0
T8	15968	670	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	725	0	0
T27	0	732	0	0
T34	0	552	0	0
T36	0	2004	0	0
T46	0	336	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T69	0	638	0	0
T70	0	1984	0	0
T71	0	502	0	0
T72	0	880	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7038956	0	0
T1	1212	811	0	0
T2	516	115	0	0
T3	499	98	0	0
T4	1063	662	0	0
T5	502	101	0	0
T6	422	21	0	0
T13	494	93	0	0
T14	498	97	0	0
T15	764	363	0	0
T16	507	106	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	411	0	0
T11	824	0	0	0
T12	784	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	14	0	0
T32	504	0	0	0
T36	0	13	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T71	0	4	0	0
T78	0	1	0	0
T84	0	16	0	0
T99	0	36	0	0
T104	0	24	0	0
T106	0	11	0	0
T212	403	0	0	0
T282	0	6	0	0
T283	0	14	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	80528	0	0
T8	15968	870	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T27	0	491	0	0
T34	0	782	0	0
T46	0	393	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T69	0	1339	0	0
T70	0	2759	0	0
T72	0	1660	0	0
T94	0	1815	0	0
T96	0	135	0	0
T272	0	1969	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	862	0	0
T8	15968	10	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T27	0	12	0	0
T34	0	8	0	0
T46	0	6	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T69	0	11	0	0
T70	0	32	0	0
T72	0	16	0	0
T94	0	16	0	0
T96	0	13	0	0
T272	0	20	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	6582180	0	0
T1	1212	811	0	0
T2	516	115	0	0
T3	499	98	0	0
T4	1063	662	0	0
T5	502	101	0	0
T6	422	21	0	0
T13	494	93	0	0
T14	498	97	0	0
T15	764	363	0	0
T16	507	106	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	6584363	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	1537	0	0
T8	15968	10	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	14	0	0
T27	0	12	0	0
T34	0	8	0	0
T36	0	28	0	0
T46	0	6	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T69	0	11	0	0
T70	0	32	0	0
T71	0	8	0	0
T72	0	16	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	1512	0	0
T8	15968	10	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	14	0	0
T27	0	12	0	0
T34	0	8	0	0
T36	0	28	0	0
T46	0	6	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T69	0	11	0	0
T70	0	32	0	0
T71	0	8	0	0
T72	0	16	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	862	0	0
T8	15968	10	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T27	0	12	0	0
T34	0	8	0	0
T46	0	6	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T69	0	11	0	0
T70	0	32	0	0
T72	0	16	0	0
T94	0	16	0	0
T96	0	13	0	0
T272	0	20	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	862	0	0
T8	15968	10	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T27	0	12	0	0
T34	0	8	0	0
T46	0	6	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T69	0	11	0	0
T70	0	32	0	0
T72	0	16	0	0
T94	0	16	0	0
T96	0	13	0	0
T272	0	20	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	79529	0	0
T8	15968	858	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T27	0	478	0	0
T34	0	771	0	0
T46	0	386	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T69	0	1325	0	0
T70	0	2720	0	0
T72	0	1644	0	0
T94	0	1795	0	0
T96	0	122	0	0
T272	0	1947	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7044416	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7044416	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	722	0	0
T8	15968	8	0	0
T9	15697	0	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T27	0	11	0	0
T34	0	5	0	0
T46	0	5	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T69	0	8	0	0
T70	0	25	0	0
T72	0	16	0	0
T94	0	12	0	0
T96	0	13	0	0
T272	0	18	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T8,T9,T26
1	Covered	T1,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T26
1	0	Covered	T1,T5,T6
1	1	Covered	T1,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T8,T9,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T5,T6	VC_COV_UNR
1	Covered	T8,T9,T41

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T8,T9,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T41
1	0	Covered	T23,T22,T7
1	1	Covered	T8,T9,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T41
0	1	Covered	T206,T284,T78
1	0	Covered	T78,T58

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T41
0	1	Covered	T8,T9,T41
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T9,T41
1	-	Covered	T8,T9,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T9,T41
DetectSt	168	Covered	T8,T9,T41
IdleSt	163	Covered	T1,T5,T6
StableSt	191	Covered	T8,T9,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T9,T41
DebounceSt->IdleSt	163	Covered	T9,T92,T196
DetectSt->IdleSt	186	Covered	T206,T284,T78
DetectSt->StableSt	191	Covered	T8,T9,T41
IdleSt->DebounceSt	148	Covered	T8,T9,T41
StableSt->IdleSt	206	Covered	T8,T9,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T9,T41
0	1	Covered	T8,T9,T41
0	0	Excluded	T1,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T41
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T9,T41
IdleSt	0	-	-	-	-	-	-	Covered	T1,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T9,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T92,T196
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T9,T41
DetectSt	-	-	-	-	1	-	-	Covered	T206,T284,T78
DetectSt	-	-	-	-	0	1	-	Covered	T8,T9,T41
DetectSt	-	-	-	-	0	0	-	Covered	T8,T9,T41
StableSt	-	-	-	-	-	-	1	Covered	T8,T9,T41
StableSt	-	-	-	-	-	-	0	Covered	T8,T9,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7712811	841	0	0
CntIncr_A	7712811	42886	0	0
CntNoWrap_A	7712811	7041163	0	0
DetectStDropOut_A	7712811	61	0	0
DetectedOut_A	7712811	18827	0	0
DetectedPulseOut_A	7712811	334	0	0
DisabledIdleSt_A	7712811	6675179	0	0
DisabledNoDetection_A	7712811	6676912	0	0
EnterDebounceSt_A	7712811	443	0	0
EnterDetectSt_A	7712811	398	0	0
EnterStableSt_A	7712811	334	0	0
PulseIsPulse_A	7712811	334	0	0
StayInStableSt	7712811	18434	0	0
gen_high_level_sva.HighLevelEvent_A	7712811	7044416	0	0
gen_not_sticky_sva.StableStDropOut_A	7712811	272	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	841	0	0
T8	15968	4	0	0
T9	15697	7	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T27	0	2	0	0
T34	0	6	0	0
T35	0	6	0	0
T37	0	2	0	0
T41	0	4	0	0
T46	0	2	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T90	0	20	0	0
T92	0	7	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	42886	0	0
T8	15968	186	0	0
T9	15697	221	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T27	0	63	0	0
T34	0	132	0	0
T35	0	213	0	0
T37	0	102	0	0
T41	0	124	0	0
T46	0	75	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T90	0	650	0	0
T92	0	520	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7041163	0	0
T1	1212	811	0	0
T2	516	115	0	0
T3	499	98	0	0
T4	1063	662	0	0
T5	502	101	0	0
T6	422	21	0	0
T13	494	93	0	0
T14	498	97	0	0
T15	764	363	0	0
T16	507	106	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	61	0	0
T75	1395	0	0	0
T78	0	1	0	0
T97	0	1	0	0
T125	0	1	0	0
T155	876	0	0	0
T178	645	0	0	0
T206	30715	10	0	0
T207	489	0	0	0
T208	676	0	0	0
T271	7568	0	0	0
T276	0	5	0	0
T284	0	2	0	0
T285	0	3	0	0
T286	0	11	0	0
T287	0	4	0	0
T288	0	2	0	0
T289	532	0	0	0
T290	418	0	0	0
T291	837	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	18827	0	0
T8	15968	110	0	0
T9	15697	41	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T27	0	23	0	0
T34	0	208	0	0
T35	0	192	0	0
T37	0	4	0	0
T41	0	13	0	0
T46	0	33	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T90	0	182	0	0
T92	0	72	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	334	0	0
T8	15968	2	0	0
T9	15697	3	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T27	0	1	0	0
T34	0	3	0	0
T35	0	3	0	0
T37	0	1	0	0
T41	0	2	0	0
T46	0	1	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T90	0	10	0	0
T92	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	6675179	0	0
T1	1212	811	0	0
T2	516	115	0	0
T3	499	98	0	0
T4	1063	662	0	0
T5	502	101	0	0
T6	422	21	0	0
T13	494	93	0	0
T14	498	97	0	0
T15	764	363	0	0
T16	507	106	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	6676912	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	443	0	0
T8	15968	2	0	0
T9	15697	4	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T27	0	1	0	0
T34	0	3	0	0
T35	0	3	0	0
T37	0	1	0	0
T41	0	2	0	0
T46	0	1	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T90	0	10	0	0
T92	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	398	0	0
T8	15968	2	0	0
T9	15697	3	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T27	0	1	0	0
T34	0	3	0	0
T35	0	3	0	0
T37	0	1	0	0
T41	0	2	0	0
T46	0	1	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T90	0	10	0	0
T92	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	334	0	0
T8	15968	2	0	0
T9	15697	3	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T27	0	1	0	0
T34	0	3	0	0
T35	0	3	0	0
T37	0	1	0	0
T41	0	2	0	0
T46	0	1	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T90	0	10	0	0
T92	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	334	0	0
T8	15968	2	0	0
T9	15697	3	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T27	0	1	0	0
T34	0	3	0	0
T35	0	3	0	0
T37	0	1	0	0
T41	0	2	0	0
T46	0	1	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T90	0	10	0	0
T92	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	18434	0	0
T8	15968	108	0	0
T9	15697	38	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T27	0	22	0	0
T34	0	205	0	0
T35	0	189	0	0
T37	0	3	0	0
T41	0	11	0	0
T46	0	32	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T90	0	172	0	0
T92	0	69	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	7044416	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7712811	272	0	0
T8	15968	2	0	0
T9	15697	3	0	0
T10	528	0	0	0
T11	824	0	0	0
T24	705	0	0	0
T25	654	0	0	0
T26	5223	0	0	0
T27	0	1	0	0
T34	0	3	0	0
T35	0	3	0	0
T37	0	1	0	0
T41	0	1	0	0
T46	0	1	0	0
T55	799	0	0	0
T56	501	0	0	0
T57	441	0	0	0
T90	0	10	0	0
T92	0	3	0	0