Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1171091306	11268	0	0
auto_block_debounce_ctl_rd_A	1171091306	2072	0	0
auto_block_out_ctl_rd_A	1171091306	2652	0	0
com_det_ctl_0_rd_A	1171091306	4860	0	0
com_det_ctl_1_rd_A	1171091306	4956	0	0
com_det_ctl_2_rd_A	1171091306	4686	0	0
com_det_ctl_3_rd_A	1171091306	4901	0	0
com_out_ctl_0_rd_A	1171091306	5143	0	0
com_out_ctl_1_rd_A	1171091306	5631	0	0
com_out_ctl_2_rd_A	1171091306	5165	0	0
com_out_ctl_3_rd_A	1171091306	5141	0	0
com_pre_det_ctl_0_rd_A	1171091306	1746	0	0
com_pre_det_ctl_1_rd_A	1171091306	1554	0	0
com_pre_det_ctl_2_rd_A	1171091306	1577	0	0
com_pre_det_ctl_3_rd_A	1171091306	1706	0	0
com_pre_sel_ctl_0_rd_A	1171091306	5394	0	0
com_pre_sel_ctl_1_rd_A	1171091306	5455	0	0
com_pre_sel_ctl_2_rd_A	1171091306	5276	0	0
com_pre_sel_ctl_3_rd_A	1171091306	5605	0	0
com_sel_ctl_0_rd_A	1171091306	5784	0	0
com_sel_ctl_1_rd_A	1171091306	5453	0	0
com_sel_ctl_2_rd_A	1171091306	5504	0	0
com_sel_ctl_3_rd_A	1171091306	5409	0	0
ec_rst_ctl_rd_A	1171091306	2833	0	0
intr_enable_rd_A	1171091306	2308	0	0
key_intr_ctl_rd_A	1171091306	3859	0	0
key_intr_debounce_ctl_rd_A	1171091306	1692	0	0
key_invert_ctl_rd_A	1171091306	5382	0	0
pin_allowed_ctl_rd_A	1171091306	6436	0	0
pin_out_ctl_rd_A	1171091306	4426	0	0
pin_out_value_rd_A	1171091306	4604	0	0
regwen_rd_A	1171091306	1945	0	0
ulp_ac_debounce_ctl_rd_A	1171091306	1776	0	0
ulp_ctl_rd_A	1171091306	1710	0	0
ulp_lid_debounce_ctl_rd_A	1171091306	2070	0	0
ulp_pwrb_debounce_ctl_rd_A	1171091306	1831	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	11268	0	0
T35	855190	6	0	0
T37	280351	15	0	0
T39	0	15	0	0
T40	341384	0	0	0
T44	761951	0	0	0
T61	0	4	0	0
T64	0	11	0	0
T82	0	4	0	0
T111	0	5	0	0
T158	0	14	0	0
T196	0	6	0	0
T201	0	7	0	0
T220	243583	0	0	0
T221	55916	0	0	0
T222	49311	0	0	0
T223	105694	0	0	0
T224	46889	0	0	0
T225	99288	0	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	2072	0	0
T27	292967	0	0	0
T33	215435	7	0	0
T34	108728	0	0	0
T37	0	35	0	0
T42	374648	0	0	0
T43	112788	0	0	0
T59	246566	0	0	0
T65	27602	0	0	0
T66	59288	0	0	0
T67	18032	0	0	0
T68	27854	0	0	0
T91	0	5	0	0
T111	0	28	0	0
T175	0	53	0	0
T203	0	8	0	0
T245	0	9	0	0
T284	0	3	0	0
T312	0	8	0	0
T313	0	13	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	2652	0	0
T27	292967	0	0	0
T33	215435	8	0	0
T34	108728	0	0	0
T37	0	35	0	0
T42	374648	0	0	0
T43	112788	0	0	0
T59	246566	0	0	0
T61	0	7	0	0
T65	27602	0	0	0
T66	59288	0	0	0
T67	18032	0	0	0
T68	27854	0	0	0
T91	0	1	0	0
T111	0	13	0	0
T203	0	8	0	0
T245	0	13	0	0
T284	0	10	0	0
T312	0	7	0	0
T313	0	17	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	4860	0	0
T9	753446	75	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T12	54349	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	0	0	0
T34	0	28	0	0
T37	0	41	0	0
T46	0	57	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0
T61	0	4	0	0
T69	0	53	0	0
T70	0	53	0	0
T111	0	18	0	0
T122	0	65	0	0
T275	0	89	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	4956	0	0
T9	753446	90	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T12	54349	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	0	0	0
T34	0	33	0	0
T37	0	40	0	0
T46	0	43	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0
T61	0	11	0	0
T69	0	61	0	0
T70	0	41	0	0
T111	0	18	0	0
T122	0	65	0	0
T275	0	67	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	4686	0	0
T9	753446	79	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T12	54349	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	0	0	0
T34	0	48	0	0
T37	0	28	0	0
T46	0	52	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0
T61	0	12	0	0
T69	0	95	0	0
T70	0	48	0	0
T111	0	18	0	0
T122	0	89	0	0
T275	0	68	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	4901	0	0
T9	753446	54	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T12	54349	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	0	0	0
T34	0	67	0	0
T37	0	40	0	0
T46	0	53	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0
T61	0	1	0	0
T69	0	68	0	0
T70	0	40	0	0
T111	0	26	0	0
T122	0	88	0	0
T275	0	61	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	5143	0	0
T9	753446	52	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T12	54349	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	0	0	0
T34	0	35	0	0
T37	0	41	0	0
T46	0	24	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0
T61	0	8	0	0
T69	0	64	0	0
T70	0	43	0	0
T111	0	30	0	0
T122	0	64	0	0
T275	0	59	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	5631	0	0
T9	753446	72	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T12	54349	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	0	0	0
T34	0	52	0	0
T37	0	27	0	0
T46	0	55	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0
T69	0	69	0	0
T70	0	56	0	0
T72	0	24	0	0
T111	0	27	0	0
T122	0	67	0	0
T275	0	73	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	5165	0	0
T9	753446	92	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T12	54349	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	0	0	0
T34	0	34	0	0
T37	0	15	0	0
T46	0	56	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0
T69	0	85	0	0
T70	0	66	0	0
T72	0	24	0	0
T111	0	17	0	0
T122	0	64	0	0
T275	0	49	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	5141	0	0
T9	753446	56	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T12	54349	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	0	0	0
T34	0	53	0	0
T37	0	38	0	0
T46	0	55	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0
T61	0	1	0	0
T69	0	50	0	0
T70	0	43	0	0
T111	0	4	0	0
T122	0	38	0	0
T275	0	42	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1746	0	0
T20	65070	0	0	0
T37	280351	16	0	0
T40	341384	0	0	0
T44	761951	0	0	0
T61	0	14	0	0
T111	0	18	0	0
T175	0	28	0	0
T190	0	19	0	0
T220	243583	0	0	0
T221	55916	0	0	0
T222	49311	0	0	0
T223	105694	0	0	0
T224	46889	0	0	0
T225	99288	0	0	0
T235	0	19	0	0
T236	0	20	0	0
T288	0	20	0	0
T314	0	23	0	0
T315	0	3	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1554	0	0
T20	65070	0	0	0
T37	280351	31	0	0
T40	341384	0	0	0
T44	761951	0	0	0
T61	0	3	0	0
T111	0	23	0	0
T175	0	40	0	0
T190	0	10	0	0
T220	243583	0	0	0
T221	55916	0	0	0
T222	49311	0	0	0
T223	105694	0	0	0
T224	46889	0	0	0
T225	99288	0	0	0
T235	0	19	0	0
T236	0	10	0	0
T288	0	24	0	0
T314	0	19	0	0
T315	0	8	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1577	0	0
T20	65070	0	0	0
T37	280351	34	0	0
T40	341384	0	0	0
T44	761951	0	0	0
T61	0	2	0	0
T111	0	15	0	0
T175	0	17	0	0
T190	0	25	0	0
T220	243583	0	0	0
T221	55916	0	0	0
T222	49311	0	0	0
T223	105694	0	0	0
T224	46889	0	0	0
T225	99288	0	0	0
T235	0	3	0	0
T236	0	7	0	0
T288	0	16	0	0
T314	0	4	0	0
T315	0	5	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1706	0	0
T20	65070	0	0	0
T37	280351	22	0	0
T40	341384	0	0	0
T44	761951	0	0	0
T61	0	11	0	0
T111	0	20	0	0
T175	0	37	0	0
T190	0	21	0	0
T220	243583	0	0	0
T221	55916	0	0	0
T222	49311	0	0	0
T223	105694	0	0	0
T224	46889	0	0	0
T225	99288	0	0	0
T235	0	6	0	0
T236	0	2	0	0
T288	0	34	0	0
T314	0	30	0	0
T315	0	13	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	5394	0	0
T9	753446	88	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T12	54349	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	0	0	0
T34	0	39	0	0
T37	0	28	0	0
T46	0	41	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0
T61	0	8	0	0
T69	0	62	0	0
T70	0	29	0	0
T111	0	15	0	0
T122	0	82	0	0
T275	0	71	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	5455	0	0
T9	753446	66	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T12	54349	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	0	0	0
T34	0	43	0	0
T37	0	24	0	0
T46	0	37	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0
T61	0	7	0	0
T69	0	68	0	0
T70	0	58	0	0
T111	0	13	0	0
T122	0	60	0	0
T275	0	66	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	5276	0	0
T9	753446	47	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T12	54349	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	0	0	0
T34	0	42	0	0
T37	0	29	0	0
T46	0	42	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0
T61	0	5	0	0
T69	0	77	0	0
T70	0	32	0	0
T111	0	23	0	0
T122	0	83	0	0
T275	0	68	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	5605	0	0
T9	753446	60	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T12	54349	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	0	0	0
T34	0	49	0	0
T37	0	42	0	0
T46	0	52	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0
T61	0	10	0	0
T69	0	80	0	0
T70	0	44	0	0
T111	0	20	0	0
T122	0	76	0	0
T275	0	65	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	5784	0	0
T9	753446	68	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T12	54349	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	0	0	0
T34	0	66	0	0
T37	0	30	0	0
T46	0	47	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0
T61	0	11	0	0
T69	0	77	0	0
T70	0	67	0	0
T111	0	21	0	0
T122	0	74	0	0
T275	0	80	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	5453	0	0
T9	753446	68	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T12	54349	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	0	0	0
T34	0	50	0	0
T37	0	32	0	0
T46	0	33	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0
T61	0	3	0	0
T69	0	83	0	0
T70	0	31	0	0
T111	0	21	0	0
T122	0	67	0	0
T275	0	97	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	5504	0	0
T9	753446	59	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T12	54349	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	0	0	0
T34	0	46	0	0
T37	0	26	0	0
T46	0	42	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0
T61	0	13	0	0
T69	0	69	0	0
T70	0	46	0	0
T111	0	27	0	0
T122	0	61	0	0
T275	0	54	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	5409	0	0
T9	753446	78	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T12	54349	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	0	0	0
T34	0	59	0	0
T37	0	33	0	0
T46	0	30	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0
T61	0	5	0	0
T69	0	53	0	0
T70	0	55	0	0
T111	0	21	0	0
T122	0	68	0	0
T275	0	69	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	2833	0	0
T9	753446	19	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T12	54349	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	0	0	0
T34	0	9	0	0
T37	0	70	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0
T61	0	3	0	0
T69	0	22	0	0
T70	0	20	0	0
T111	0	28	0	0
T122	0	52	0	0
T214	0	1	0	0
T275	0	11	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	2308	0	0
T9	753446	9	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T12	54349	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	0	0	0
T37	0	62	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0
T61	0	15	0	0
T111	0	39	0	0
T175	0	65	0	0
T209	0	11	0	0
T245	0	11	0	0
T313	0	19	0	0
T314	0	15	0	0
T315	0	5	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	3859	0	0
T7	634977	2	0	0
T8	191620	0	0	0
T9	753446	0	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T24	84683	0	0	0
T26	574577	0	0	0
T33	0	6	0	0
T37	0	42	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0
T61	0	3	0	0
T111	0	26	0	0
T153	0	2	0	0
T155	0	5	0	0
T175	0	27	0	0
T245	0	3	0	0
T247	0	5	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1692	0	0
T20	65070	0	0	0
T37	280351	36	0	0
T40	341384	0	0	0
T44	761951	0	0	0
T61	0	5	0	0
T111	0	7	0	0
T175	0	34	0	0
T190	0	22	0	0
T220	243583	0	0	0
T221	55916	0	0	0
T222	49311	0	0	0
T223	105694	0	0	0
T224	46889	0	0	0
T225	99288	0	0	0
T235	0	24	0	0
T236	0	8	0	0
T288	0	19	0	0
T314	0	22	0	0
T315	0	14	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	5382	0	0
T4	185552	0	0	0
T7	0	63	0	0
T14	124531	60	0	0
T15	91825	0	0	0
T16	63407	0	0	0
T23	226182	0	0	0
T37	0	287	0	0
T49	95153	0	0	0
T50	13947	0	0	0
T51	53135	0	0	0
T52	149776	0	0	0
T53	129275	0	0	0
T61	0	11	0	0
T68	0	68	0	0
T111	0	15	0	0
T153	0	38	0	0
T197	0	87	0	0
T202	0	31	0	0
T284	0	39	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	6436	0	0
T16	63407	68	0	0
T22	107961	0	0	0
T23	226182	0	0	0
T37	0	82	0	0
T49	95153	0	0	0
T50	13947	0	0	0
T51	53135	0	0	0
T52	149776	0	0	0
T53	129275	0	0	0
T54	34194	0	0	0
T60	105226	0	0	0
T61	0	115	0	0
T111	0	77	0	0
T112	0	56	0	0
T217	0	96	0	0
T245	0	62	0	0
T316	0	43	0	0
T317	0	82	0	0
T318	0	33	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	4426	0	0
T16	63407	53	0	0
T22	107961	0	0	0
T23	226182	0	0	0
T37	0	100	0	0
T49	95153	0	0	0
T50	13947	0	0	0
T51	53135	0	0	0
T52	149776	0	0	0
T53	129275	0	0	0
T54	34194	0	0	0
T60	105226	0	0	0
T61	0	66	0	0
T111	0	134	0	0
T112	0	42	0	0
T217	0	67	0	0
T245	0	60	0	0
T316	0	40	0	0
T317	0	49	0	0
T318	0	56	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	4604	0	0
T16	63407	79	0	0
T22	107961	0	0	0
T23	226182	0	0	0
T37	0	99	0	0
T49	95153	0	0	0
T50	13947	0	0	0
T51	53135	0	0	0
T52	149776	0	0	0
T53	129275	0	0	0
T54	34194	0	0	0
T60	105226	0	0	0
T61	0	106	0	0
T111	0	76	0	0
T112	0	52	0	0
T217	0	78	0	0
T245	0	58	0	0
T316	0	33	0	0
T317	0	82	0	0
T318	0	62	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1945	0	0
T20	65070	0	0	0
T37	280351	27	0	0
T40	341384	0	0	0
T44	761951	0	0	0
T61	0	10	0	0
T111	0	17	0	0
T175	0	32	0	0
T190	0	18	0	0
T220	243583	0	0	0
T221	55916	0	0	0
T222	49311	0	0	0
T223	105694	0	0	0
T224	46889	0	0	0
T225	99288	0	0	0
T235	0	14	0	0
T236	0	2	0	0
T288	0	32	0	0
T314	0	27	0	0
T315	0	13	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1776	0	0
T27	292967	0	0	0
T33	215435	7	0	0
T34	108728	0	0	0
T37	0	51	0	0
T42	374648	0	0	0
T43	112788	0	0	0
T59	246566	0	0	0
T61	0	6	0	0
T63	0	5	0	0
T65	27602	0	0	0
T66	59288	0	0	0
T67	18032	0	0	0
T68	27854	0	0	0
T111	0	31	0	0
T148	0	2	0	0
T175	0	29	0	0
T216	0	1	0	0
T314	0	13	0	0
T319	0	3	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1710	0	0
T27	292967	0	0	0
T33	215435	3	0	0
T34	108728	0	0	0
T37	0	38	0	0
T42	374648	0	0	0
T43	112788	0	0	0
T59	246566	0	0	0
T61	0	9	0	0
T63	0	7	0	0
T65	27602	0	0	0
T66	59288	0	0	0
T67	18032	0	0	0
T68	27854	0	0	0
T88	0	1	0	0
T111	0	15	0	0
T175	0	39	0	0
T314	0	15	0	0
T315	0	1	0	0
T319	0	3	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	2070	0	0
T27	292967	0	0	0
T33	215435	8	0	0
T34	108728	0	0	0
T37	0	33	0	0
T42	374648	0	0	0
T43	112788	0	0	0
T59	246566	0	0	0
T61	0	10	0	0
T63	0	2	0	0
T65	27602	0	0	0
T66	59288	0	0	0
T67	18032	0	0	0
T68	27854	0	0	0
T75	0	1	0	0
T111	0	25	0	0
T148	0	1	0	0
T175	0	28	0	0
T216	0	3	0	0
T319	0	5	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1831	0	0
T27	292967	0	0	0
T33	215435	4	0	0
T34	108728	0	0	0
T37	0	26	0	0
T42	374648	0	0	0
T43	112788	0	0	0
T59	246566	0	0	0
T61	0	3	0	0
T63	0	8	0	0
T65	27602	0	0	0
T66	59288	0	0	0
T67	18032	0	0	0
T68	27854	0	0	0
T75	0	8	0	0
T111	0	12	0	0
T148	0	1	0	0
T175	0	50	0	0
T216	0	7	0	0
T319	0	2	0	0