Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.30	100.00	89.20			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_wkup_status_cdc	96.88	100.00	87.50			100.00	100.00
tb.dut.u_reg.u_ec_rst_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_invert_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_out_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_out_value_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_intr_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_ctl_cdc	98.08	100.00	92.31			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wkup_status_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.79	96.99	84.93			93.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	92.06	95.92	81.63			90.70	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_value_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=16,ResetVal,BitMask=65535,DstWrReq=0,TxnWidth=3 + DataWidth=12,ResetVal=0,BitMask=4095,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal,BitMask=255,DstWrReq=0,TxnWidth=3 + DataWidth=14,ResetVal=0,BitMask=16383,DstWrReq=0,TxnWidth=3 + DataWidth=17,ResetVal=2000,BitMask=131071,DstWrReq=0,TxnWidth=3 + DataWidth=7,ResetVal=0,BitMask=119,DstWrReq=0,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=0,TxnWidth=3 + DataWidth=4,ResetVal=0,BitMask=15,DstWrReq=0,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ec_rst_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_allowed_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_invert_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_out_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_out_value_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_intr_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_auto_block_out_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T22

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T22
1	1	Covered	T1,T5,T22

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T5,T22

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T5,T22
1	1	Covered	T1,T5,T22

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=0,TxnWidth=3 + DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
98.08	92.31

tb.dut.u_reg.u_ulp_ctl_cdc

SCORE	COND
96.88	87.50

tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T8,T9

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T8,T9
1	1	Covered	T1,T8,T9

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T1,T20,T21
1	-	Covered	T1,T8,T9

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T8,T9

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T8,T9
1	1	Covered	T1,T8,T9

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T22,T8
0	0	1	Covered	T1,T22,T8
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T22,T8
0	0	1	Covered	T1,T22,T8
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	101800154	0	0
DstReqKnown_A	270640850	241394968	0	0
SrcAckBusyChk_A	2147483647	114285	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	101800154	0	0
T4	371104	0	0	0
T8	4024020	14344	0	0
T9	15822366	72831	0	0
T10	332850	226	0	0
T11	6310857	0	0	0
T15	183650	2863	0	0
T16	126814	0	0	0
T22	107961	0	0	0
T23	452364	0	0	0
T24	1693660	3940	0	0
T25	719940	1377	0	0
T26	12066117	2466	0	0
T27	0	21975	0	0
T33	0	12795	0	0
T34	0	118546	0	0
T35	0	45555	0	0
T36	0	7195	0	0
T37	0	19898	0	0
T41	0	16957	0	0
T42	0	10989	0	0
T43	0	916	0	0
T44	0	7310	0	0
T45	0	3228	0	0
T46	0	5352	0	0
T47	0	192	0	0
T48	0	12725	0	0
T49	190306	0	0	0
T50	27894	0	0	0
T51	106270	0	0	0
T52	299552	0	0	0
T53	258550	0	0	0
T54	68388	0	0	0
T55	2100063	0	0	0
T56	5275431	0	0	0
T57	530400	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	270640850	241394968	0	0
T1	41208	27608	0	0
T2	17544	3944	0	0
T3	16966	3366	0	0
T4	36142	22542	0	0
T5	17068	3468	0	0
T6	14348	748	0	0
T13	16796	3196	0	0
T14	16932	3332	0	0
T15	25976	12376	0	0
T16	17238	3638	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	114285	0	0
T4	371104	0	0	0
T8	4024020	36	0	0
T9	15822366	48	0	0
T10	332850	3	0	0
T11	6310857	0	0	0
T15	183650	7	0	0
T16	126814	0	0	0
T22	107961	0	0	0
T23	452364	0	0	0
T24	1693660	9	0	0
T25	719940	7	0	0
T26	12066117	9	0	0
T27	0	27	0	0
T33	0	7	0	0
T34	0	72	0	0
T35	0	28	0	0
T36	0	4	0	0
T37	0	48	0	0
T41	0	24	0	0
T42	0	7	0	0
T43	0	8	0	0
T44	0	72	0	0
T45	0	8	0	0
T46	0	14	0	0
T47	0	1	0	0
T48	0	7	0	0
T49	190306	0	0	0
T50	27894	0	0	0
T51	106270	0	0	0
T52	299552	0	0	0
T53	258550	0	0	0
T54	68388	0	0	0
T55	2100063	0	0	0
T56	5275431	0	0	0
T57	530400	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1215704	1213698	0	0
T2	7478912	7476056	0	0
T3	3684036	3680704	0	0
T4	6308768	6306456	0	0
T5	8188730	8185772	0	0
T6	6895064	6892854	0	0
T13	2015384	2013616	0	0
T14	4234054	4231878	0	0
T15	3122050	3119534	0	0
T16	2155838	2152676	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T8,T9

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T8,T9
1	1	Covered	T1,T8,T9

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T58,T28,T30
1	-	Covered	T1,T8,T9

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T8,T9

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T8,T9
1	1	Covered	T1,T8,T9

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T8,T9
0	0	1	Covered	T1,T8,T9
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T8,T9
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1171091306	1007268	0	0
DstReqKnown_A	7960025	7099852	0	0
SrcAckBusyChk_A	1171091306	1163	0	0
SrcBusyKnown_A	1171091306	1169282635	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1007268	0	0
T1	35756	627	0	0
T2	219968	0	0	0
T3	108354	0	0	0
T4	185552	0	0	0
T5	240845	0	0	0
T6	202796	0	0	0
T8	0	1240	0	0
T9	0	9442	0	0
T13	59276	0	0	0
T14	124531	0	0	0
T15	91825	0	0	0
T16	63407	0	0	0
T20	0	552	0	0
T27	0	747	0	0
T34	0	13745	0	0
T35	0	6418	0	0
T37	0	390	0	0
T44	0	624	0	0
T46	0	350	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7960025	7099852	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1163	0	0
T1	35756	3	0	0
T2	219968	0	0	0
T3	108354	0	0	0
T4	185552	0	0	0
T5	240845	0	0	0
T6	202796	0	0	0
T8	0	3	0	0
T9	0	6	0	0
T13	59276	0	0	0
T14	124531	0	0	0
T15	91825	0	0	0
T16	63407	0	0	0
T20	0	1	0	0
T27	0	1	0	0
T34	0	8	0	0
T35	0	4	0	0
T37	0	1	0	0
T44	0	6	0	0
T46	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1169282635	0	0
T1	35756	35697	0	0
T2	219968	219884	0	0
T3	108354	108256	0	0
T4	185552	185484	0	0
T5	240845	240758	0	0
T6	202796	202731	0	0
T13	59276	59224	0	0
T14	124531	124467	0	0
T15	91825	91751	0	0
T16	63407	63314	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T22,T8,T9

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T22,T8,T9
1	1	Covered	T22,T8,T9

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T22,T8,T9

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T22,T8,T9
1	1	Covered	T22,T8,T9

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T22,T8,T9
0	0	1	Covered	T22,T8,T9
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T22,T8,T9
0	0	1	Covered	T22,T8,T9
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1171091306	1644894	0	0
DstReqKnown_A	7960025	7099852	0	0
SrcAckBusyChk_A	1171091306	1922	0	0
SrcBusyKnown_A	1171091306	1169282635	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1644894	0	0
T7	634977	0	0	0
T8	191620	1677	0	0
T9	753446	8816	0	0
T10	15850	80	0	0
T11	300517	0	0	0
T22	107961	1918	0	0
T26	574577	331	0	0
T27	0	2381	0	0
T41	0	2017	0	0
T43	0	89	0	0
T55	100003	353	0	0
T56	251211	0	0	0
T59	0	1434	0	0
T60	105226	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7960025	7099852	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1922	0	0
T7	634977	0	0	0
T8	191620	4	0	0
T9	753446	6	0	0
T10	15850	1	0	0
T11	300517	0	0	0
T22	107961	1	0	0
T26	574577	1	0	0
T27	0	3	0	0
T41	0	3	0	0
T43	0	1	0	0
T55	100003	1	0	0
T56	251211	0	0	0
T59	0	1	0	0
T60	105226	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1169282635	0	0
T1	35756	35697	0	0
T2	219968	219884	0	0
T3	108354	108256	0	0
T4	185552	185484	0	0
T5	240845	240758	0	0
T6	202796	202731	0	0
T13	59276	59224	0	0
T14	124531	124467	0	0
T15	91825	91751	0	0
T16	63407	63314	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T32,T33

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T32,T33
1	1	Covered	T1,T32,T33

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T32,T33

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T32,T33
1	1	Covered	T1,T32,T33

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T32,T33
0	0	1	Covered	T1,T32,T33
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T32,T33
0	0	1	Covered	T1,T32,T33
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1171091306	885993	0	0
DstReqKnown_A	7960025	7099852	0	0
SrcAckBusyChk_A	1171091306	928	0	0
SrcBusyKnown_A	1171091306	1169282635	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	885993	0	0
T1	35756	639	0	0
T2	219968	0	0	0
T3	108354	0	0	0
T4	185552	0	0	0
T5	240845	0	0	0
T6	202796	0	0	0
T13	59276	0	0	0
T14	124531	0	0	0
T15	91825	0	0	0
T16	63407	0	0	0
T20	0	978	0	0
T21	0	1441	0	0
T32	0	749	0	0
T33	0	1974	0	0
T37	0	391	0	0
T61	0	1055	0	0
T62	0	2849	0	0
T63	0	804	0	0
T64	0	3555	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7960025	7099852	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	928	0	0
T1	35756	3	0	0
T2	219968	0	0	0
T3	108354	0	0	0
T4	185552	0	0	0
T5	240845	0	0	0
T6	202796	0	0	0
T13	59276	0	0	0
T14	124531	0	0	0
T15	91825	0	0	0
T16	63407	0	0	0
T20	0	2	0	0
T21	0	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T37	0	1	0	0
T61	0	1	0	0
T62	0	2	0	0
T63	0	2	0	0
T64	0	4	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1169282635	0	0
T1	35756	35697	0	0
T2	219968	219884	0	0
T3	108354	108256	0	0
T4	185552	185484	0	0
T5	240845	240758	0	0
T6	202796	202731	0	0
T13	59276	59224	0	0
T14	124531	124467	0	0
T15	91825	91751	0	0
T16	63407	63314	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T32,T33

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T32,T33
1	1	Covered	T1,T32,T33

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T32,T33

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T32,T33
1	1	Covered	T1,T32,T33

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T32,T33
0	0	1	Covered	T1,T32,T33
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T32,T33
0	0	1	Covered	T1,T32,T33
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1171091306	913307	0	0
DstReqKnown_A	7960025	7099852	0	0
SrcAckBusyChk_A	1171091306	961	0	0
SrcBusyKnown_A	1171091306	1169282635	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	913307	0	0
T1	35756	633	0	0
T2	219968	0	0	0
T3	108354	0	0	0
T4	185552	0	0	0
T5	240845	0	0	0
T6	202796	0	0	0
T13	59276	0	0	0
T14	124531	0	0	0
T15	91825	0	0	0
T16	63407	0	0	0
T20	0	974	0	0
T21	0	1427	0	0
T32	0	747	0	0
T33	0	1962	0	0
T37	0	378	0	0
T61	0	1043	0	0
T62	0	2845	0	0
T63	0	795	0	0
T64	0	3524	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7960025	7099852	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	961	0	0
T1	35756	3	0	0
T2	219968	0	0	0
T3	108354	0	0	0
T4	185552	0	0	0
T5	240845	0	0	0
T6	202796	0	0	0
T13	59276	0	0	0
T14	124531	0	0	0
T15	91825	0	0	0
T16	63407	0	0	0
T20	0	2	0	0
T21	0	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T37	0	1	0	0
T61	0	1	0	0
T62	0	2	0	0
T63	0	2	0	0
T64	0	4	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1169282635	0	0
T1	35756	35697	0	0
T2	219968	219884	0	0
T3	108354	108256	0	0
T4	185552	185484	0	0
T5	240845	240758	0	0
T6	202796	202731	0	0
T13	59276	59224	0	0
T14	124531	124467	0	0
T15	91825	91751	0	0
T16	63407	63314	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T32,T33

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T32,T33
1	1	Covered	T1,T32,T33

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T32,T33

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T32,T33
1	1	Covered	T1,T32,T33

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T32,T33
0	0	1	Covered	T1,T32,T33
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T32,T33
0	0	1	Covered	T1,T32,T33
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1171091306	883751	0	0
DstReqKnown_A	7960025	7099852	0	0
SrcAckBusyChk_A	1171091306	946	0	0
SrcBusyKnown_A	1171091306	1169282635	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	883751	0	0
T1	35756	627	0	0
T2	219968	0	0	0
T3	108354	0	0	0
T4	185552	0	0	0
T5	240845	0	0	0
T6	202796	0	0	0
T13	59276	0	0	0
T14	124531	0	0	0
T15	91825	0	0	0
T16	63407	0	0	0
T20	0	970	0	0
T21	0	1411	0	0
T32	0	745	0	0
T33	0	1954	0	0
T37	0	376	0	0
T61	0	1024	0	0
T62	0	2841	0	0
T63	0	775	0	0
T64	0	3505	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7960025	7099852	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	946	0	0
T1	35756	3	0	0
T2	219968	0	0	0
T3	108354	0	0	0
T4	185552	0	0	0
T5	240845	0	0	0
T6	202796	0	0	0
T13	59276	0	0	0
T14	124531	0	0	0
T15	91825	0	0	0
T16	63407	0	0	0
T20	0	2	0	0
T21	0	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T37	0	1	0	0
T61	0	1	0	0
T62	0	2	0	0
T63	0	2	0	0
T64	0	4	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1169282635	0	0
T1	35756	35697	0	0
T2	219968	219884	0	0
T3	108354	108256	0	0
T4	185552	185484	0	0
T5	240845	240758	0	0
T6	202796	202731	0	0
T13	59276	59224	0	0
T14	124531	124467	0	0
T15	91825	91751	0	0
T16	63407	63314	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T13,T14,T22

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T13,T14,T22
1	1	Covered	T13,T14,T22

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T13,T14,T22

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T13,T14,T22
1	1	Covered	T13,T14,T22

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T13,T14,T22
0	0	1	Covered	T13,T14,T22
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T13,T14,T22
0	0	1	Covered	T13,T14,T22
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1171091306	2650563	0	0
DstReqKnown_A	7960025	7099852	0	0
SrcAckBusyChk_A	1171091306	2936	0	0
SrcBusyKnown_A	1171091306	1169282635	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	2650563	0	0
T2	219968	0	0	0
T3	108354	0	0	0
T4	185552	0	0	0
T7	0	17136	0	0
T13	59276	8173	0	0
T14	124531	18414	0	0
T15	91825	0	0	0
T16	63407	0	0	0
T22	0	34563	0	0
T23	226182	0	0	0
T35	0	32883	0	0
T43	0	2380	0	0
T49	95153	0	0	0
T50	13947	0	0	0
T65	0	3858	0	0
T66	0	8142	0	0
T67	0	2560	0	0
T68	0	3871	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7960025	7099852	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	2936	0	0
T2	219968	0	0	0
T3	108354	0	0	0
T4	185552	0	0	0
T7	0	20	0	0
T13	59276	20	0	0
T14	124531	20	0	0
T15	91825	0	0	0
T16	63407	0	0	0
T22	0	20	0	0
T23	226182	0	0	0
T35	0	20	0	0
T43	0	20	0	0
T49	95153	0	0	0
T50	13947	0	0	0
T65	0	20	0	0
T66	0	20	0	0
T67	0	20	0	0
T68	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1169282635	0	0
T1	35756	35697	0	0
T2	219968	219884	0	0
T3	108354	108256	0	0
T4	185552	185484	0	0
T5	240845	240758	0	0
T6	202796	202731	0	0
T13	59276	59224	0	0
T14	124531	124467	0	0
T15	91825	91751	0	0
T16	63407	63314	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T5,T13,T14

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T5,T13,T14
1	1	Covered	T5,T13,T14

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T5,T13,T14

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T13,T14
1	1	Covered	T5,T13,T14

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T5,T13,T14
0	0	1	Covered	T5,T13,T14
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T5,T13,T14
0	0	1	Covered	T5,T13,T14
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1171091306	5846161	0	0
DstReqKnown_A	7960025	7099852	0	0
SrcAckBusyChk_A	1171091306	6460	0	0
SrcBusyKnown_A	1171091306	1169282635	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	5846161	0	0
T2	219968	0	0	0
T3	108354	0	0	0
T4	185552	0	0	0
T5	240845	31768	0	0
T6	202796	0	0	0
T7	0	33683	0	0
T13	59276	464	0	0
T14	124531	979	0	0
T15	91825	0	0	0
T16	63407	8347	0	0
T22	0	35924	0	0
T23	0	15328	0	0
T33	0	68759	0	0
T49	95153	0	0	0
T56	0	35931	0	0
T65	0	159	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7960025	7099852	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	6460	0	0
T2	219968	0	0	0
T3	108354	0	0	0
T4	185552	0	0	0
T5	240845	20	0	0
T6	202796	0	0	0
T7	0	41	0	0
T13	59276	1	0	0
T14	124531	1	0	0
T15	91825	0	0	0
T16	63407	20	0	0
T22	0	21	0	0
T23	0	40	0	0
T33	0	40	0	0
T49	95153	0	0	0
T56	0	20	0	0
T65	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1169282635	0	0
T1	35756	35697	0	0
T2	219968	219884	0	0
T3	108354	108256	0	0
T4	185552	185484	0	0
T5	240845	240758	0	0
T6	202796	202731	0	0
T13	59276	59224	0	0
T14	124531	124467	0	0
T15	91825	91751	0	0
T16	63407	63314	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T5,T13,T14

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T5,T13,T14
1	1	Covered	T5,T13,T14

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T5,T13,T14

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T13,T14
1	1	Covered	T5,T13,T14

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T5,T13,T14
0	0	1	Covered	T5,T13,T14
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T5,T13,T14
0	0	1	Covered	T5,T13,T14
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1171091306	6900864	0	0
DstReqKnown_A	7960025	7099852	0	0
SrcAckBusyChk_A	1171091306	7613	0	0
SrcBusyKnown_A	1171091306	1169282635	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	6900864	0	0
T2	219968	0	0	0
T3	108354	0	0	0
T4	185552	0	0	0
T5	240845	32058	0	0
T6	202796	0	0	0
T7	0	34556	0	0
T8	0	1766	0	0
T9	0	9498	0	0
T10	0	73	0	0
T13	59276	467	0	0
T14	124531	994	0	0
T15	91825	0	0	0
T16	63407	8771	0	0
T22	0	37445	0	0
T23	0	15896	0	0
T49	95153	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7960025	7099852	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	7613	0	0
T2	219968	0	0	0
T3	108354	0	0	0
T4	185552	0	0	0
T5	240845	20	0	0
T6	202796	0	0	0
T7	0	41	0	0
T8	0	4	0	0
T9	0	6	0	0
T10	0	1	0	0
T13	59276	1	0	0
T14	124531	1	0	0
T15	91825	0	0	0
T16	63407	20	0	0
T22	0	22	0	0
T23	0	40	0	0
T49	95153	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1169282635	0	0
T1	35756	35697	0	0
T2	219968	219884	0	0
T3	108354	108256	0	0
T4	185552	185484	0	0
T5	240845	240758	0	0
T6	202796	202731	0	0
T13	59276	59224	0	0
T14	124531	124467	0	0
T15	91825	91751	0	0
T16	63407	63314	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T5,T16,T23

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T5,T16,T23
1	1	Covered	T5,T16,T23

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T5,T16,T23

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T16,T23
1	1	Covered	T5,T16,T23

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T5,T16,T23
0	0	1	Covered	T5,T16,T23
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T5,T16,T23
0	0	1	Covered	T5,T16,T23
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1171091306	5748087	0	0
DstReqKnown_A	7960025	7099852	0	0
SrcAckBusyChk_A	1171091306	6345	0	0
SrcBusyKnown_A	1171091306	1169282635	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	5748087	0	0
T2	219968	0	0	0
T3	108354	0	0	0
T4	185552	0	0	0
T5	240845	31919	0	0
T6	202796	0	0	0
T7	0	33673	0	0
T13	59276	0	0	0
T14	124531	0	0	0
T15	91825	0	0	0
T16	63407	8574	0	0
T22	0	34530	0	0
T23	0	15612	0	0
T33	0	69182	0	0
T35	0	136058	0	0
T37	0	45244	0	0
T43	0	2265	0	0
T49	95153	0	0	0
T56	0	35971	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7960025	7099852	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	6345	0	0
T2	219968	0	0	0
T3	108354	0	0	0
T4	185552	0	0	0
T5	240845	20	0	0
T6	202796	0	0	0
T7	0	40	0	0
T13	59276	0	0	0
T14	124531	0	0	0
T15	91825	0	0	0
T16	63407	20	0	0
T22	0	20	0	0
T23	0	40	0	0
T33	0	40	0	0
T35	0	80	0	0
T37	0	100	0	0
T43	0	20	0	0
T49	95153	0	0	0
T56	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1169282635	0	0
T1	35756	35697	0	0
T2	219968	219884	0	0
T3	108354	108256	0	0
T4	185552	185484	0	0
T5	240845	240758	0	0
T6	202796	202731	0	0
T13	59276	59224	0	0
T14	124531	124467	0	0
T15	91825	91751	0	0
T16	63407	63314	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T2,T3,T4

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T2,T3,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1171091306	852237	0	0
DstReqKnown_A	7960025	7099852	0	0
SrcAckBusyChk_A	1171091306	967	0	0
SrcBusyKnown_A	1171091306	1169282635	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	852237	0	0
T2	219968	1490	0	0
T3	108354	966	0	0
T4	185552	1000	0	0
T7	0	737	0	0
T11	0	1957	0	0
T12	0	360	0	0
T14	124531	0	0	0
T15	91825	0	0	0
T16	63407	0	0	0
T23	226182	0	0	0
T33	0	1979	0	0
T35	0	3486	0	0
T37	0	387	0	0
T40	0	1499	0	0
T49	95153	0	0	0
T50	13947	0	0	0
T51	53135	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7960025	7099852	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	967	0	0
T2	219968	1	0	0
T3	108354	1	0	0
T4	185552	1	0	0
T7	0	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T14	124531	0	0	0
T15	91825	0	0	0
T16	63407	0	0	0
T23	226182	0	0	0
T33	0	1	0	0
T35	0	2	0	0
T37	0	1	0	0
T40	0	1	0	0
T49	95153	0	0	0
T50	13947	0	0	0
T51	53135	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1169282635	0	0
T1	35756	35697	0	0
T2	219968	219884	0	0
T3	108354	108256	0	0
T4	185552	185484	0	0
T5	240845	240758	0	0
T6	202796	202731	0	0
T13	59276	59224	0	0
T14	124531	124467	0	0
T15	91825	91751	0	0
T16	63407	63314	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T2,T3,T4

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T2,T3,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1171091306	1629076	0	0
DstReqKnown_A	7960025	7099852	0	0
SrcAckBusyChk_A	1171091306	1932	0	0
SrcBusyKnown_A	1171091306	1169282635	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1629076	0	0
T2	219968	1487	0	0
T3	108354	958	0	0
T4	185552	998	0	0
T7	0	732	0	0
T8	0	1650	0	0
T9	0	8751	0	0
T10	0	71	0	0
T11	0	1955	0	0
T12	0	358	0	0
T14	124531	0	0	0
T15	91825	0	0	0
T16	63407	0	0	0
T23	226182	0	0	0
T26	0	319	0	0
T49	95153	0	0	0
T50	13947	0	0	0
T51	53135	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7960025	7099852	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1932	0	0
T2	219968	1	0	0
T3	108354	1	0	0
T4	185552	1	0	0
T7	0	1	0	0
T8	0	4	0	0
T9	0	6	0	0
T10	0	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T14	124531	0	0	0
T15	91825	0	0	0
T16	63407	0	0	0
T23	226182	0	0	0
T26	0	1	0	0
T49	95153	0	0	0
T50	13947	0	0	0
T51	53135	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1169282635	0	0
T1	35756	35697	0	0
T2	219968	219884	0	0
T3	108354	108256	0	0
T4	185552	185484	0	0
T5	240845	240758	0	0
T6	202796	202731	0	0
T13	59276	59224	0	0
T14	124531	124467	0	0
T15	91825	91751	0	0
T16	63407	63314	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T15,T24,T25

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T15,T24,T25
1	1	Covered	T15,T24,T25

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T15,T24,T25

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T15,T24,T25
1	1	Covered	T15,T24,T25

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T15,T24,T25
0	0	1	Covered	T15,T24,T25
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T15,T24,T25
0	0	1	Covered	T15,T24,T25
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1171091306	1276701	0	0
DstReqKnown_A	7960025	7099852	0	0
SrcAckBusyChk_A	1171091306	1342	0	0
SrcBusyKnown_A	1171091306	1169282635	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1276701	0	0
T4	185552	0	0	0
T15	91825	1675	0	0
T16	63407	0	0	0
T23	226182	0	0	0
T24	0	2632	0	0
T25	0	805	0	0
T33	0	7404	0	0
T35	0	1983	0	0
T37	0	6013	0	0
T42	0	6498	0	0
T43	0	566	0	0
T45	0	2037	0	0
T48	0	7346	0	0
T49	95153	0	0	0
T50	13947	0	0	0
T51	53135	0	0	0
T52	149776	0	0	0
T53	129275	0	0	0
T54	34194	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7960025	7099852	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1342	0	0
T4	185552	0	0	0
T15	91825	4	0	0
T16	63407	0	0	0
T23	226182	0	0	0
T24	0	6	0	0
T25	0	4	0	0
T33	0	4	0	0
T35	0	1	0	0
T37	0	13	0	0
T42	0	4	0	0
T43	0	5	0	0
T45	0	5	0	0
T48	0	4	0	0
T49	95153	0	0	0
T50	13947	0	0	0
T51	53135	0	0	0
T52	149776	0	0	0
T53	129275	0	0	0
T54	34194	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1169282635	0	0
T1	35756	35697	0	0
T2	219968	219884	0	0
T3	108354	108256	0	0
T4	185552	185484	0	0
T5	240845	240758	0	0
T6	202796	202731	0	0
T13	59276	59224	0	0
T14	124531	124467	0	0
T15	91825	91751	0	0
T16	63407	63314	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T15,T24,T25

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T15,T24,T25
1	1	Covered	T15,T24,T25

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T15,T24,T25

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T15,T24,T25
1	1	Covered	T15,T24,T25

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T15,T24,T25
0	0	1	Covered	T15,T24,T25
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T15,T24,T25
0	0	1	Covered	T15,T24,T25
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1171091306	1102602	0	0
DstReqKnown_A	7960025	7099852	0	0
SrcAckBusyChk_A	1171091306	1164	0	0
SrcBusyKnown_A	1171091306	1169282635	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1102602	0	0
T4	185552	0	0	0
T15	91825	1188	0	0
T16	63407	0	0	0
T23	226182	0	0	0
T24	0	1308	0	0
T25	0	572	0	0
T33	0	5391	0	0
T35	0	1974	0	0
T37	0	4209	0	0
T42	0	4491	0	0
T43	0	350	0	0
T45	0	1191	0	0
T48	0	5379	0	0
T49	95153	0	0	0
T50	13947	0	0	0
T51	53135	0	0	0
T52	149776	0	0	0
T53	129275	0	0	0
T54	34194	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7960025	7099852	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1164	0	0
T4	185552	0	0	0
T15	91825	3	0	0
T16	63407	0	0	0
T23	226182	0	0	0
T24	0	3	0	0
T25	0	3	0	0
T33	0	3	0	0
T35	0	1	0	0
T37	0	9	0	0
T42	0	3	0	0
T43	0	3	0	0
T45	0	3	0	0
T48	0	3	0	0
T49	95153	0	0	0
T50	13947	0	0	0
T51	53135	0	0	0
T52	149776	0	0	0
T53	129275	0	0	0
T54	34194	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1169282635	0	0
T1	35756	35697	0	0
T2	219968	219884	0	0
T3	108354	108256	0	0
T4	185552	185484	0	0
T5	240845	240758	0	0
T6	202796	202731	0	0
T13	59276	59224	0	0
T14	124531	124467	0	0
T15	91825	91751	0	0
T16	63407	63314	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T10,T26

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T8,T10,T26
1	1	Covered	T8,T10,T26

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T10,T26

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T10,T26
1	1	Covered	T8,T10,T26

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T10,T26
0	0	1	Covered	T8,T10,T26
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T10,T26
0	0	1	Covered	T8,T10,T26
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1171091306	6720048	0	0
DstReqKnown_A	7960025	7099852	0	0
SrcAckBusyChk_A	1171091306	7271	0	0
SrcBusyKnown_A	1171091306	1169282635	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	6720048	0	0
T8	191620	29036	0	0
T9	753446	0	0	0
T10	15850	87	0	0
T11	300517	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	18684	0	0
T27	0	70287	0	0
T34	0	104048	0	0
T36	0	135146	0	0
T46	0	27095	0	0
T47	0	194	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0
T69	0	145722	0	0
T70	0	44995	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7960025	7099852	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	7271	0	0
T8	191620	72	0	0
T9	753446	0	0	0
T10	15850	1	0	0
T11	300517	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	51	0	0
T27	0	79	0	0
T34	0	62	0	0
T36	0	80	0	0
T46	0	63	0	0
T47	0	1	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0
T69	0	86	0	0
T70	0	66	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1169282635	0	0
T1	35756	35697	0	0
T2	219968	219884	0	0
T3	108354	108256	0	0
T4	185552	185484	0	0
T5	240845	240758	0	0
T6	202796	202731	0	0
T13	59276	59224	0	0
T14	124531	124467	0	0
T15	91825	91751	0	0
T16	63407	63314	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T26,T27

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T8,T26,T27
1	1	Covered	T8,T26,T27

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T26,T27

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T26,T27
1	1	Covered	T8,T26,T27

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T26,T27
0	0	1	Covered	T8,T26,T27
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T26,T27
0	0	1	Covered	T8,T26,T27
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1171091306	6254228	0	0
DstReqKnown_A	7960025	7099852	0	0
SrcAckBusyChk_A	1171091306	7094	0	0
SrcBusyKnown_A	1171091306	1169282635	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	6254228	0	0
T8	191620	27977	0	0
T9	753446	0	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	17957	0	0
T27	0	57544	0	0
T34	0	131895	0	0
T36	0	91266	0	0
T46	0	35438	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0
T69	0	101418	0	0
T70	0	54855	0	0
T71	0	17113	0	0
T72	0	62298	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7960025	7099852	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	7094	0	0
T8	191620	72	0	0
T9	753446	0	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	51	0	0
T27	0	65	0	0
T34	0	79	0	0
T36	0	54	0	0
T46	0	85	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0
T69	0	61	0	0
T70	0	82	0	0
T71	0	77	0	0
T72	0	72	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1169282635	0	0
T1	35756	35697	0	0
T2	219968	219884	0	0
T3	108354	108256	0	0
T4	185552	185484	0	0
T5	240845	240758	0	0
T6	202796	202731	0	0
T13	59276	59224	0	0
T14	124531	124467	0	0
T15	91825	91751	0	0
T16	63407	63314	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T26,T27

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T8,T26,T27
1	1	Covered	T8,T26,T27

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T26,T27

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T26,T27
1	1	Covered	T8,T26,T27

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T26,T27
0	0	1	Covered	T8,T26,T27
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T26,T27
0	0	1	Covered	T8,T26,T27
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1171091306	6308024	0	0
DstReqKnown_A	7960025	7099852	0	0
SrcAckBusyChk_A	1171091306	7096	0	0
SrcBusyKnown_A	1171091306	1169282635	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	6308024	0	0
T8	191620	20086	0	0
T9	753446	0	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	17167	0	0
T27	0	59060	0	0
T34	0	117542	0	0
T36	0	106351	0	0
T46	0	25352	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0
T69	0	128904	0	0
T70	0	42601	0	0
T71	0	16161	0	0
T72	0	49890	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7960025	7099852	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	7096	0	0
T8	191620	54	0	0
T9	753446	0	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	51	0	0
T27	0	67	0	0
T34	0	72	0	0
T36	0	63	0	0
T46	0	64	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0
T69	0	78	0	0
T70	0	66	0	0
T71	0	77	0	0
T72	0	59	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1169282635	0	0
T1	35756	35697	0	0
T2	219968	219884	0	0
T3	108354	108256	0	0
T4	185552	185484	0	0
T5	240845	240758	0	0
T6	202796	202731	0	0
T13	59276	59224	0	0
T14	124531	124467	0	0
T15	91825	91751	0	0
T16	63407	63314	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T26,T27

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T8,T26,T27
1	1	Covered	T8,T26,T27

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T26,T27

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T26,T27
1	1	Covered	T8,T26,T27

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T26,T27
0	0	1	Covered	T8,T26,T27
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T26,T27
0	0	1	Covered	T8,T26,T27
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1171091306	6255124	0	0
DstReqKnown_A	7960025	7099852	0	0
SrcAckBusyChk_A	1171091306	7165	0	0
SrcBusyKnown_A	1171091306	1169282635	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	6255124	0	0
T8	191620	24314	0	0
T9	753446	0	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	16431	0	0
T27	0	71496	0	0
T34	0	123936	0	0
T36	0	134300	0	0
T46	0	33397	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0
T69	0	122107	0	0
T70	0	41134	0	0
T71	0	15306	0	0
T72	0	56273	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7960025	7099852	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	7165	0	0
T8	191620	66	0	0
T9	753446	0	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	51	0	0
T27	0	81	0	0
T34	0	76	0	0
T36	0	80	0	0
T46	0	85	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0
T69	0	75	0	0
T70	0	66	0	0
T71	0	77	0	0
T72	0	67	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1169282635	0	0
T1	35756	35697	0	0
T2	219968	219884	0	0
T3	108354	108256	0	0
T4	185552	185484	0	0
T5	240845	240758	0	0
T6	202796	202731	0	0
T13	59276	59224	0	0
T14	124531	124467	0	0
T15	91825	91751	0	0
T16	63407	63314	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T10,T26

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T8,T10,T26
1	1	Covered	T8,T10,T26

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T10,T26

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T10,T26
1	1	Covered	T8,T10,T26

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T10,T26
0	0	1	Covered	T8,T10,T26
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T10,T26
0	0	1	Covered	T8,T10,T26
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1171091306	1063701	0	0
DstReqKnown_A	7960025	7099852	0	0
SrcAckBusyChk_A	1171091306	1192	0	0
SrcBusyKnown_A	1171091306	1169282635	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1063701	0	0
T8	191620	1749	0	0
T9	753446	0	0	0
T10	15850	77	0	0
T11	300517	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	318	0	0
T27	0	2495	0	0
T34	0	13818	0	0
T36	0	7195	0	0
T46	0	844	0	0
T47	0	192	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0
T69	0	11420	0	0
T70	0	7064	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7960025	7099852	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1192	0	0
T8	191620	4	0	0
T9	753446	0	0	0
T10	15850	1	0	0
T11	300517	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	1	0	0
T27	0	3	0	0
T34	0	8	0	0
T36	0	4	0	0
T46	0	2	0	0
T47	0	1	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0
T69	0	7	0	0
T70	0	10	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1169282635	0	0
T1	35756	35697	0	0
T2	219968	219884	0	0
T3	108354	108256	0	0
T4	185552	185484	0	0
T5	240845	240758	0	0
T6	202796	202731	0	0
T13	59276	59224	0	0
T14	124531	124467	0	0
T15	91825	91751	0	0
T16	63407	63314	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T26,T27

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T8,T26,T27
1	1	Covered	T8,T26,T27

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T26,T27

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T26,T27
1	1	Covered	T8,T26,T27

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T26,T27
0	0	1	Covered	T8,T26,T27
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T26,T27
0	0	1	Covered	T8,T26,T27
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1171091306	1067826	0	0
DstReqKnown_A	7960025	7099852	0	0
SrcAckBusyChk_A	1171091306	1189	0	0
SrcBusyKnown_A	1171091306	1169282635	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1067826	0	0
T8	191620	1610	0	0
T9	753446	0	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	294	0	0
T27	0	2465	0	0
T34	0	13444	0	0
T36	0	7155	0	0
T46	0	739	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0
T69	0	11026	0	0
T70	0	6638	0	0
T71	0	168	0	0
T72	0	1380	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7960025	7099852	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1189	0	0
T8	191620	4	0	0
T9	753446	0	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	1	0	0
T27	0	3	0	0
T34	0	8	0	0
T36	0	4	0	0
T46	0	2	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0
T69	0	7	0	0
T70	0	10	0	0
T71	0	1	0	0
T72	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1169282635	0	0
T1	35756	35697	0	0
T2	219968	219884	0	0
T3	108354	108256	0	0
T4	185552	185484	0	0
T5	240845	240758	0	0
T6	202796	202731	0	0
T13	59276	59224	0	0
T14	124531	124467	0	0
T15	91825	91751	0	0
T16	63407	63314	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T26,T27

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T8,T26,T27
1	1	Covered	T8,T26,T27

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T26,T27

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T26,T27
1	1	Covered	T8,T26,T27

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T26,T27
0	0	1	Covered	T8,T26,T27
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T26,T27
0	0	1	Covered	T8,T26,T27
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1171091306	1059785	0	0
DstReqKnown_A	7960025	7099852	0	0
SrcAckBusyChk_A	1171091306	1218	0	0
SrcBusyKnown_A	1171091306	1169282635	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1059785	0	0
T8	191620	1481	0	0
T9	753446	0	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	270	0	0
T27	0	2435	0	0
T34	0	13087	0	0
T36	0	7115	0	0
T46	0	768	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0
T69	0	10634	0	0
T70	0	6196	0	0
T71	0	200	0	0
T72	0	1289	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7960025	7099852	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1218	0	0
T8	191620	4	0	0
T9	753446	0	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	1	0	0
T27	0	3	0	0
T34	0	8	0	0
T36	0	4	0	0
T46	0	2	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0
T69	0	7	0	0
T70	0	10	0	0
T71	0	1	0	0
T72	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1169282635	0	0
T1	35756	35697	0	0
T2	219968	219884	0	0
T3	108354	108256	0	0
T4	185552	185484	0	0
T5	240845	240758	0	0
T6	202796	202731	0	0
T13	59276	59224	0	0
T14	124531	124467	0	0
T15	91825	91751	0	0
T16	63407	63314	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T26,T27

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T8,T26,T27
1	1	Covered	T8,T26,T27

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T26,T27

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T26,T27
1	1	Covered	T8,T26,T27

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T26,T27
0	0	1	Covered	T8,T26,T27
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T26,T27
0	0	1	Covered	T8,T26,T27
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1171091306	1035488	0	0
DstReqKnown_A	7960025	7099852	0	0
SrcAckBusyChk_A	1171091306	1203	0	0
SrcBusyKnown_A	1171091306	1169282635	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1035488	0	0
T8	191620	1565	0	0
T9	753446	0	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	236	0	0
T27	0	2405	0	0
T34	0	12720	0	0
T36	0	7075	0	0
T46	0	786	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0
T69	0	10257	0	0
T70	0	5731	0	0
T71	0	166	0	0
T72	0	1222	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7960025	7099852	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1203	0	0
T8	191620	4	0	0
T9	753446	0	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	1	0	0
T27	0	3	0	0
T34	0	8	0	0
T36	0	4	0	0
T46	0	2	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0
T69	0	7	0	0
T70	0	10	0	0
T71	0	1	0	0
T72	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1169282635	0	0
T1	35756	35697	0	0
T2	219968	219884	0	0
T3	108354	108256	0	0
T4	185552	185484	0	0
T5	240845	240758	0	0
T6	202796	202731	0	0
T13	59276	59224	0	0
T14	124531	124467	0	0
T15	91825	91751	0	0
T16	63407	63314	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T9,T10

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T8,T9,T10
1	1	Covered	T8,T9,T10

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T9,T10

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T9,T10
1	1	Covered	T8,T9,T10

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T9,T10
0	0	1	Covered	T8,T9,T10
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T9,T10
0	0	1	Covered	T8,T9,T10
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1171091306	7312950	0	0
DstReqKnown_A	7960025	7099852	0	0
SrcAckBusyChk_A	1171091306	7910	0	0
SrcBusyKnown_A	1171091306	1169282635	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	7312950	0	0
T8	191620	29443	0	0
T9	753446	9582	0	0
T10	15850	70	0	0
T11	300517	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	19016	0	0
T27	0	70427	0	0
T34	0	104401	0	0
T35	0	6467	0	0
T37	0	1728	0	0
T41	0	2289	0	0
T44	0	1014	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7960025	7099852	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	7910	0	0
T8	191620	72	0	0
T9	753446	6	0	0
T10	15850	1	0	0
T11	300517	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	51	0	0
T27	0	79	0	0
T34	0	62	0	0
T35	0	4	0	0
T37	0	4	0	0
T41	0	3	0	0
T44	0	9	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1169282635	0	0
T1	35756	35697	0	0
T2	219968	219884	0	0
T3	108354	108256	0	0
T4	185552	185484	0	0
T5	240845	240758	0	0
T6	202796	202731	0	0
T13	59276	59224	0	0
T14	124531	124467	0	0
T15	91825	91751	0	0
T16	63407	63314	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T9,T26

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T8,T9,T26
1	1	Covered	T8,T9,T26

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T9,T26

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T9,T26
1	1	Covered	T8,T9,T26

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T9,T26
0	0	1	Covered	T8,T9,T26
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T9,T26
0	0	1	Covered	T8,T9,T26
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1171091306	6757751	0	0
DstReqKnown_A	7960025	7099852	0	0
SrcAckBusyChk_A	1171091306	7671	0	0
SrcBusyKnown_A	1171091306	1169282635	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	6757751	0	0
T8	191620	28444	0	0
T9	753446	9517	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	18306	0	0
T27	0	57656	0	0
T34	0	132394	0	0
T35	0	4964	0	0
T37	0	1304	0	0
T41	0	2275	0	0
T44	0	960	0	0
T46	0	36291	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7960025	7099852	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	7671	0	0
T8	191620	72	0	0
T9	753446	6	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	51	0	0
T27	0	65	0	0
T34	0	79	0	0
T35	0	3	0	0
T37	0	3	0	0
T41	0	3	0	0
T44	0	9	0	0
T46	0	85	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1169282635	0	0
T1	35756	35697	0	0
T2	219968	219884	0	0
T3	108354	108256	0	0
T4	185552	185484	0	0
T5	240845	240758	0	0
T6	202796	202731	0	0
T13	59276	59224	0	0
T14	124531	124467	0	0
T15	91825	91751	0	0
T16	63407	63314	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T9,T26

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T8,T9,T26
1	1	Covered	T8,T9,T26

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T9,T26

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T9,T26
1	1	Covered	T8,T9,T26

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T9,T26
0	0	1	Covered	T8,T9,T26
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T9,T26
0	0	1	Covered	T8,T9,T26
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1171091306	6830268	0	0
DstReqKnown_A	7960025	7099852	0	0
SrcAckBusyChk_A	1171091306	7675	0	0
SrcBusyKnown_A	1171091306	1169282635	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	6830268	0	0
T8	191620	20406	0	0
T9	753446	9471	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	17526	0	0
T27	0	59176	0	0
T34	0	117952	0	0
T35	0	4941	0	0
T37	0	1268	0	0
T41	0	2260	0	0
T44	0	906	0	0
T46	0	26043	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7960025	7099852	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	7675	0	0
T8	191620	54	0	0
T9	753446	6	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	51	0	0
T27	0	67	0	0
T34	0	72	0	0
T35	0	3	0	0
T37	0	3	0	0
T41	0	3	0	0
T44	0	9	0	0
T46	0	64	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1169282635	0	0
T1	35756	35697	0	0
T2	219968	219884	0	0
T3	108354	108256	0	0
T4	185552	185484	0	0
T5	240845	240758	0	0
T6	202796	202731	0	0
T13	59276	59224	0	0
T14	124531	124467	0	0
T15	91825	91751	0	0
T16	63407	63314	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T9,T26

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T8,T9,T26
1	1	Covered	T8,T9,T26

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T9,T26

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T9,T26
1	1	Covered	T8,T9,T26

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T9,T26
0	0	1	Covered	T8,T9,T26
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T9,T26
0	0	1	Covered	T8,T9,T26
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1171091306	6708304	0	0
DstReqKnown_A	7960025	7099852	0	0
SrcAckBusyChk_A	1171091306	7694	0	0
SrcBusyKnown_A	1171091306	1169282635	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	6708304	0	0
T8	191620	24703	0	0
T9	753446	9406	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	16801	0	0
T27	0	71640	0	0
T34	0	124421	0	0
T35	0	4920	0	0
T37	0	1236	0	0
T41	0	2233	0	0
T44	0	836	0	0
T46	0	34197	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7960025	7099852	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	7694	0	0
T8	191620	66	0	0
T9	753446	6	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	51	0	0
T27	0	81	0	0
T34	0	76	0	0
T35	0	3	0	0
T37	0	3	0	0
T41	0	3	0	0
T44	0	9	0	0
T46	0	85	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1169282635	0	0
T1	35756	35697	0	0
T2	219968	219884	0	0
T3	108354	108256	0	0
T4	185552	185484	0	0
T5	240845	240758	0	0
T6	202796	202731	0	0
T13	59276	59224	0	0
T14	124531	124467	0	0
T15	91825	91751	0	0
T16	63407	63314	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T9,T10

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T8,T9,T10
1	1	Covered	T8,T9,T10

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T9,T10

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T9,T10
1	1	Covered	T8,T9,T10

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T9,T10
0	0	1	Covered	T8,T9,T10
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T9,T10
0	0	1	Covered	T8,T9,T10
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1171091306	1583867	0	0
DstReqKnown_A	7960025	7099852	0	0
SrcAckBusyChk_A	1171091306	1815	0	0
SrcBusyKnown_A	1171091306	1169282635	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1583867	0	0
T8	191620	1695	0	0
T9	753446	9325	0	0
T10	15850	63	0	0
T11	300517	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	313	0	0
T27	0	2483	0	0
T34	0	13662	0	0
T35	0	6371	0	0
T37	0	1587	0	0
T41	0	2205	0	0
T44	0	868	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7960025	7099852	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1815	0	0
T8	191620	4	0	0
T9	753446	6	0	0
T10	15850	1	0	0
T11	300517	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	1	0	0
T27	0	3	0	0
T34	0	8	0	0
T35	0	4	0	0
T37	0	4	0	0
T41	0	3	0	0
T44	0	9	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1169282635	0	0
T1	35756	35697	0	0
T2	219968	219884	0	0
T3	108354	108256	0	0
T4	185552	185484	0	0
T5	240845	240758	0	0
T6	202796	202731	0	0
T13	59276	59224	0	0
T14	124531	124467	0	0
T15	91825	91751	0	0
T16	63407	63314	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T9,T26

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T8,T9,T26
1	1	Covered	T8,T9,T26

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T9,T26

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T9,T26
1	1	Covered	T8,T9,T26

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T9,T26
0	0	1	Covered	T8,T9,T26
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T9,T26
0	0	1	Covered	T8,T9,T26
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1171091306	1533744	0	0
DstReqKnown_A	7960025	7099852	0	0
SrcAckBusyChk_A	1171091306	1787	0	0
SrcBusyKnown_A	1171091306	1169282635	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1533744	0	0
T8	191620	1552	0	0
T9	753446	9264	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	288	0	0
T27	0	2453	0	0
T34	0	13293	0	0
T35	0	4881	0	0
T37	0	1181	0	0
T41	0	2186	0	0
T44	0	980	0	0
T46	0	697	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7960025	7099852	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1787	0	0
T8	191620	4	0	0
T9	753446	6	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	1	0	0
T27	0	3	0	0
T34	0	8	0	0
T35	0	3	0	0
T37	0	3	0	0
T41	0	3	0	0
T44	0	9	0	0
T46	0	2	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1169282635	0	0
T1	35756	35697	0	0
T2	219968	219884	0	0
T3	108354	108256	0	0
T4	185552	185484	0	0
T5	240845	240758	0	0
T6	202796	202731	0	0
T13	59276	59224	0	0
T14	124531	124467	0	0
T15	91825	91751	0	0
T16	63407	63314	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T9,T26

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T8,T9,T26
1	1	Covered	T8,T9,T26

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T9,T26

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T9,T26
1	1	Covered	T8,T9,T26

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T9,T26
0	0	1	Covered	T8,T9,T26
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T9,T26
0	0	1	Covered	T8,T9,T26
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1171091306	1506771	0	0
DstReqKnown_A	7960025	7099852	0	0
SrcAckBusyChk_A	1171091306	1770	0	0
SrcBusyKnown_A	1171091306	1169282635	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1506771	0	0
T8	191620	1431	0	0
T9	753446	9218	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	255	0	0
T27	0	2423	0	0
T34	0	12950	0	0
T35	0	4860	0	0
T37	0	1152	0	0
T41	0	2155	0	0
T44	0	910	0	0
T46	0	841	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7960025	7099852	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1770	0	0
T8	191620	4	0	0
T9	753446	6	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	1	0	0
T27	0	3	0	0
T34	0	8	0	0
T35	0	3	0	0
T37	0	3	0	0
T41	0	3	0	0
T44	0	9	0	0
T46	0	2	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1169282635	0	0
T1	35756	35697	0	0
T2	219968	219884	0	0
T3	108354	108256	0	0
T4	185552	185484	0	0
T5	240845	240758	0	0
T6	202796	202731	0	0
T13	59276	59224	0	0
T14	124531	124467	0	0
T15	91825	91751	0	0
T16	63407	63314	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T9,T26

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T8,T9,T26
1	1	Covered	T8,T9,T26

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T9,T26

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T9,T26
1	1	Covered	T8,T9,T26

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T9,T26
0	0	1	Covered	T8,T9,T26
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T9,T26
0	0	1	Covered	T8,T9,T26
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1171091306	1524759	0	0
DstReqKnown_A	7960025	7099852	0	0
SrcAckBusyChk_A	1171091306	1805	0	0
SrcBusyKnown_A	1171091306	1169282635	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1524759	0	0
T8	191620	1617	0	0
T9	753446	9139	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	231	0	0
T27	0	2393	0	0
T34	0	12588	0	0
T35	0	4844	0	0
T37	0	1122	0	0
T41	0	2135	0	0
T44	0	900	0	0
T46	0	748	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7960025	7099852	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1805	0	0
T8	191620	4	0	0
T9	753446	6	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	1	0	0
T27	0	3	0	0
T34	0	8	0	0
T35	0	3	0	0
T37	0	3	0	0
T41	0	3	0	0
T44	0	9	0	0
T46	0	2	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1169282635	0	0
T1	35756	35697	0	0
T2	219968	219884	0	0
T3	108354	108256	0	0
T4	185552	185484	0	0
T5	240845	240758	0	0
T6	202796	202731	0	0
T13	59276	59224	0	0
T14	124531	124467	0	0
T15	91825	91751	0	0
T16	63407	63314	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T9,T10

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T8,T9,T10
1	1	Covered	T8,T9,T10

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T9,T10

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T9,T10
1	1	Covered	T8,T9,T10

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T9,T10
0	0	1	Covered	T8,T9,T10
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T9,T10
0	0	1	Covered	T8,T9,T10
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1171091306	1568902	0	0
DstReqKnown_A	7960025	7099852	0	0
SrcAckBusyChk_A	1171091306	1814	0	0
SrcBusyKnown_A	1171091306	1169282635	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1568902	0	0
T8	191620	1664	0	0
T9	753446	9074	0	0
T10	15850	86	0	0
T11	300517	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	307	0	0
T27	0	2477	0	0
T34	0	13603	0	0
T35	0	6299	0	0
T37	0	1470	0	0
T41	0	2112	0	0
T44	0	833	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7960025	7099852	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1814	0	0
T8	191620	4	0	0
T9	753446	6	0	0
T10	15850	1	0	0
T11	300517	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	1	0	0
T27	0	3	0	0
T34	0	8	0	0
T35	0	4	0	0
T37	0	4	0	0
T41	0	3	0	0
T44	0	9	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1169282635	0	0
T1	35756	35697	0	0
T2	219968	219884	0	0
T3	108354	108256	0	0
T4	185552	185484	0	0
T5	240845	240758	0	0
T6	202796	202731	0	0
T13	59276	59224	0	0
T14	124531	124467	0	0
T15	91825	91751	0	0
T16	63407	63314	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T9,T26

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T8,T9,T26
1	1	Covered	T8,T9,T26

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T9,T26

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T9,T26
1	1	Covered	T8,T9,T26

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T9,T26
0	0	1	Covered	T8,T9,T26
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T9,T26
0	0	1	Covered	T8,T9,T26
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1171091306	1481513	0	0
DstReqKnown_A	7960025	7099852	0	0
SrcAckBusyChk_A	1171091306	1753	0	0
SrcBusyKnown_A	1171091306	1169282635	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1481513	0	0
T8	191620	1522	0	0
T9	753446	9006	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	279	0	0
T27	0	2447	0	0
T34	0	13225	0	0
T35	0	4802	0	0
T37	0	1048	0	0
T41	0	2078	0	0
T44	0	899	0	0
T46	0	677	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7960025	7099852	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1753	0	0
T8	191620	4	0	0
T9	753446	6	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	1	0	0
T27	0	3	0	0
T34	0	8	0	0
T35	0	3	0	0
T37	0	3	0	0
T41	0	3	0	0
T44	0	9	0	0
T46	0	2	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1169282635	0	0
T1	35756	35697	0	0
T2	219968	219884	0	0
T3	108354	108256	0	0
T4	185552	185484	0	0
T5	240845	240758	0	0
T6	202796	202731	0	0
T13	59276	59224	0	0
T14	124531	124467	0	0
T15	91825	91751	0	0
T16	63407	63314	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T9,T26

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T8,T9,T26
1	1	Covered	T8,T9,T26

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T9,T26

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T9,T26
1	1	Covered	T8,T9,T26

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T9,T26
0	0	1	Covered	T8,T9,T26
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T9,T26
0	0	1	Covered	T8,T9,T26
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1171091306	1477363	0	0
DstReqKnown_A	7960025	7099852	0	0
SrcAckBusyChk_A	1171091306	1741	0	0
SrcBusyKnown_A	1171091306	1169282635	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1477363	0	0
T8	191620	1403	0	0
T9	753446	8929	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	252	0	0
T27	0	2417	0	0
T34	0	12878	0	0
T35	0	4781	0	0
T37	0	1009	0	0
T41	0	2056	0	0
T44	0	964	0	0
T46	0	825	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7960025	7099852	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1741	0	0
T8	191620	4	0	0
T9	753446	6	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	1	0	0
T27	0	3	0	0
T34	0	8	0	0
T35	0	3	0	0
T37	0	3	0	0
T41	0	3	0	0
T44	0	9	0	0
T46	0	2	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1169282635	0	0
T1	35756	35697	0	0
T2	219968	219884	0	0
T3	108354	108256	0	0
T4	185552	185484	0	0
T5	240845	240758	0	0
T6	202796	202731	0	0
T13	59276	59224	0	0
T14	124531	124467	0	0
T15	91825	91751	0	0
T16	63407	63314	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T9,T26

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T8,T9,T26
1	1	Covered	T8,T9,T26

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T8,T9,T26

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T9,T26
1	1	Covered	T8,T9,T26

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T9,T26
0	0	1	Covered	T8,T9,T26
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T8,T9,T26
0	0	1	Covered	T8,T9,T26
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1171091306	1494559	0	0
DstReqKnown_A	7960025	7099852	0	0
SrcAckBusyChk_A	1171091306	1780	0	0
SrcBusyKnown_A	1171091306	1169282635	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1494559	0	0
T8	191620	1711	0	0
T9	753446	8876	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	223	0	0
T27	0	2387	0	0
T34	0	12529	0	0
T35	0	4760	0	0
T37	0	1107	0	0
T41	0	2030	0	0
T44	0	956	0	0
T46	0	720	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7960025	7099852	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1780	0	0
T8	191620	4	0	0
T9	753446	6	0	0
T10	15850	0	0	0
T11	300517	0	0	0
T24	84683	0	0	0
T25	35997	0	0	0
T26	574577	1	0	0
T27	0	3	0	0
T34	0	8	0	0
T35	0	3	0	0
T37	0	3	0	0
T41	0	3	0	0
T44	0	9	0	0
T46	0	2	0	0
T55	100003	0	0	0
T56	251211	0	0	0
T57	26520	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1169282635	0	0
T1	35756	35697	0	0
T2	219968	219884	0	0
T3	108354	108256	0	0
T4	185552	185484	0	0
T5	240845	240758	0	0
T6	202796	202731	0	0
T13	59276	59224	0	0
T14	124531	124467	0	0
T15	91825	91751	0	0
T16	63407	63314	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T20,T21

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T20,T21
1	1	Covered	T1,T20,T21

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T1,T20,T21
1	-	Covered	T1,T20,T21

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Unreachable
1	0	Covered	T1,T20,T21

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T20,T21
1	1	Covered	T1,T20,T21

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T20,T21
0	0	1	Covered	T1,T20,T21
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T5,T6
0	1	-	Covered	T1,T20,T21
0	0	1	Covered	T1,T20,T21
0	0	0	Covered	T1,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1171091306	913675	0	0
DstReqKnown_A	7960025	7099852	0	0
SrcAckBusyChk_A	1171091306	963	0	0
SrcBusyKnown_A	1171091306	1169282635	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	913675	0	0
T1	35756	1344	0	0
T2	219968	0	0	0
T3	108354	0	0	0
T4	185552	0	0	0
T5	240845	0	0	0
T6	202796	0	0	0
T13	59276	0	0	0
T14	124531	0	0	0
T15	91825	0	0	0
T16	63407	0	0	0
T20	0	974	0	0
T21	0	1431	0	0
T63	0	480	0	0
T64	0	3512	0	0
T73	0	3923	0	0
T74	0	3494	0	0
T75	0	3963	0	0
T76	0	2873	0	0
T77	0	3886	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7960025	7099852	0	0
T1	1212	812	0	0
T2	516	116	0	0
T3	499	99	0	0
T4	1063	663	0	0
T5	502	102	0	0
T6	422	22	0	0
T13	494	94	0	0
T14	498	98	0	0
T15	764	364	0	0
T16	507	107	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	963	0	0
T1	35756	6	0	0
T2	219968	0	0	0
T3	108354	0	0	0
T4	185552	0	0	0
T5	240845	0	0	0
T6	202796	0	0	0
T13	59276	0	0	0
T14	124531	0	0	0
T15	91825	0	0	0
T16	63407	0	0	0
T20	0	2	0	0
T21	0	2	0	0
T63	0	1	0	0
T64	0	4	0	0
T73	0	2	0	0
T74	0	2	0	0
T75	0	2	0	0
T76	0	2	0	0
T77	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171091306	1169282635	0	0
T1	35756	35697	0	0
T2	219968	219884	0	0
T3	108354	108256	0	0
T4	185552	185484	0	0
T5	240845	240758	0	0
T6	202796	202731	0	0
T13	59276	59224	0	0
T14	124531	124467	0	0
T15	91825	91751	0	0
T16	63407	63314	0	0