Group : tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_key_intr_status_cg
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Group : tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_key_intr_status_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_cov_0/sysrst_ctrl_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
sysrst_ctrl_key_intr_status_cg 100.00 1 100 1 64 64




Group Instance : sysrst_ctrl_key_intr_status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sysrst_ctrl_key_intr_status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 28 0 28 100.00


Variables for Group Instance sysrst_ctrl_key_intr_status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_ac_present_h2l 2 0 2 100.00 100 1 1 2
cp_ac_present_l2h 2 0 2 100.00 100 1 1 2
cp_ec_rst_l_h2l 2 0 2 100.00 100 1 1 2
cp_ec_rst_l_l2h 2 0 2 100.00 100 1 1 2
cp_flash_wp_l_h2l 2 0 2 100.00 100 1 1 2
cp_flash_wp_l_l2h 2 0 2 100.00 100 1 1 2
cp_key0_in_h2l 2 0 2 100.00 100 1 1 2
cp_key0_in_l2h 2 0 2 100.00 100 1 1 2
cp_key1_in_h2l 2 0 2 100.00 100 1 1 2
cp_key1_in_l2h 2 0 2 100.00 100 1 1 2
cp_key2_in_h2l 2 0 2 100.00 100 1 1 2
cp_key2_in_l2h 2 0 2 100.00 100 1 1 2
cp_pwrb_h2l 2 0 2 100.00 100 1 1 2
cp_pwrb_l2h 2 0 2 100.00 100 1 1 2


Summary for Variable cp_ac_present_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ac_present_h2l

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 993 1 T3 8 T7 6 T10 17
auto[1] 122 1 T3 1 T7 2 T36 2



Summary for Variable cp_ac_present_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ac_present_l2h

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 970 1 T3 6 T7 5 T10 14
auto[1] 145 1 T3 3 T7 3 T10 3



Summary for Variable cp_ec_rst_l_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ec_rst_l_h2l

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 965 1 T3 7 T7 5 T10 17
auto[1] 150 1 T3 2 T7 3 T36 2



Summary for Variable cp_ec_rst_l_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ec_rst_l_l2h

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 998 1 T3 9 T7 6 T10 15
auto[1] 117 1 T7 2 T10 2 T37 3



Summary for Variable cp_flash_wp_l_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_flash_wp_l_h2l

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 960 1 T3 9 T7 3 T10 14
auto[1] 155 1 T7 5 T10 3 T36 3



Summary for Variable cp_flash_wp_l_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_flash_wp_l_l2h

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 998 1 T3 9 T7 5 T10 17
auto[1] 117 1 T7 3 T36 2 T37 4



Summary for Variable cp_key0_in_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_in_h2l

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 991 1 T3 5 T7 8 T10 13
auto[1] 124 1 T3 4 T10 4 T39 2



Summary for Variable cp_key0_in_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_in_l2h

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 958 1 T3 6 T7 5 T10 13
auto[1] 157 1 T3 3 T7 3 T10 4



Summary for Variable cp_key1_in_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_in_h2l

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 966 1 T3 8 T7 8 T10 17
auto[1] 149 1 T3 1 T36 2 T37 2



Summary for Variable cp_key1_in_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_in_l2h

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 968 1 T3 5 T7 8 T10 17
auto[1] 147 1 T3 4 T36 2 T38 3



Summary for Variable cp_key2_in_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_in_h2l

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 998 1 T3 5 T7 5 T10 17
auto[1] 117 1 T3 4 T7 3 T36 2



Summary for Variable cp_key2_in_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_in_l2h

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 977 1 T3 9 T7 5 T10 13
auto[1] 138 1 T7 3 T10 4 T36 2



Summary for Variable cp_pwrb_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_pwrb_h2l

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 983 1 T3 9 T7 8 T10 16
auto[1] 132 1 T10 1 T36 2 T37 2



Summary for Variable cp_pwrb_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_pwrb_l2h

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 949 1 T3 4 T7 8 T10 17
auto[1] 166 1 T3 5 T36 3 T39 2

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