Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
92.68	92.68	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	92.68	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.68	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	6	56	90.32

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	6	25	80.65	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2172

1

T1

9

T2

46

T8

12

auto[1]

685

1

T1

1

T2

22

T8

9

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2231

1

T1

9

T2

28

T8

19

auto[1]

626

1

T1

1

T2

40

T8

2

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2334

1

T1

9

T2

68

T8

16

auto[1]

523

1

T1

1

T8

5

T13

1

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2138

1

T1

10

T2

52

T8

21

auto[1]

719

1

T2

16

T11

6

T13

1

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2625

1

T1

10

T2

68

T8

21

auto[1]

232

1

T13

2

T34

3

T69

6

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2631

1

T1

10

T2

62

T8

21

auto[1]

226

1

T2

6

T34

14

T42

13

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2551

1

T1

10

T2

28

T8

21

auto[1]

306

1

T2

40

T9

5

T13

5

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2579

1

T1

10

T2

62

T8

21

auto[1]

278

1

T2

6

T9

5

T13

6

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2635

1

T1

10

T2

60

T8

21

auto[1]

222

1

T2

8

T13

2

T34

2

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2168

1

T1

1

T2

46

T8

9

auto[1]

689

1

T1

9

T2

22

T8

12

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	6	25	80.65	6
Automatically Generated Cross Bins	31	6	25	80.65	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	*	[auto[0]]	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

904

1

T1

10

T8

10

T11

6

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

101

1

T69

6

T35

1

T150

8

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

59

1

T208

3

T211

5

T311

7

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

24

1

T13

1

T208

3

T213

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

64

1

T211

2

T214

2

T312

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

5

1

T212

3

T207

1

T313

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

41

1

T211

1

T79

2

T220

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

13

1

T13

1

T222

1

T314

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

141

1

T2

32

T68

3

T208

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

20

1

T210

8

T204

1

T308

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

28

1

T2

8

T220

1

T222

7

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

3

1

T315

1

T316

1

T317

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

28

1

T9

5

T13

5

T34

6

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

8

1

T34

3

T318

4

T319

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1

1

T212

1

-

-

-

-

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

47

1

T34

12

T298

3

T203

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

17

1

T320

4

T306

2

T305

8

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

28

1

T42

6

T321

3

T164

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

4

1

T301

1

T322

3

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

44

1

T2

6

T150

4

T210

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

12

1

T208

1

T213

2

T298

6

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

4

1

T34

2

T321

2

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

26

1

T42

7

T68

2

T213

7

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

3

1

T323

2

T324

1

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

6

1

T318

4

T325

2

-

-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

133

1

T34

2

T68

3

T211

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

148

1

T1

9

T8

7

T34

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

86

1

T2

6

T13

5

T215

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

180

1

T42

7

T39

13

T211

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

87

1

T34

12

T42

6

T115

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

80

1

T11

6

T84

7

T210

8

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

24

1

T211

3

T212

7

T326

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

82

1

T69

6

T213

2

T131

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

37

1

T150

4

T210

2

T217

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

52

1

T8

3

T86

3

T312

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

17

1

T84

2

T80

1

T90

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

75

1

T13

1

T115

2

T208

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

18

1

T302

2

T311

7

T202

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

25

1

T86

2

T170

4

T225

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

8

1

T228

2

T219

2

T327

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

113

1

T2

8

T9

5

T13

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

97

1

T2

16

T88

5

T202

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

53

1

T34

6

T69

1

T150

8

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

26

1

T82

1

T73

1

T80

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

46

1

T73

3

T80

3

T147

5

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

22

1

T208

3

T147

2

T217

8

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

52

1

T2

16

T80

1

T302

5

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

9

1

T39

2

T328

2

T304

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

57

1

T35

1

T115

7

T211

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

26

1

T1

1

T82

2

T79

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

33

1

T82

1

T226

3

T80

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

5

1

T96

2

T229

3

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

15

1

T329

3

T330

4

T331

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

15

1

T96

3

T230

2

T99

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

8

1

T86

2

T294

2

T99

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

2

1

T219

2

-

-

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded