Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

980

1

T19

12

T10

9

T60

11

auto[1]

977

1

T19

8

T10

11

T60

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

453

1

T19

6

T10

3

T60

6

from_0to1

457

1

T19

7

T10

4

T60

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

981

1

T19

10

T10

14

T60

13

auto[1]

976

1

T19

10

T10

6

T60

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

996

1

T19

11

T10

10

T60

7

auto[1]

961

1

T19

9

T10

10

T60

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

57

1

T19

1

T10

1

T60

1

auto[0]

from_1to0

auto[0]

auto[1]

59

1

T19

3

T60

3

T38

4

auto[0]

from_1to0

auto[1]

auto[0]

50

1

T38

1

T355

1

T161

1

auto[0]

from_1to0

auto[1]

auto[1]

56

1

T105

2

T355

1

T161

1

auto[0]

from_0to1

auto[0]

auto[0]

58

1

T10

1

T60

2

T38

1

auto[0]

from_0to1

auto[0]

auto[1]

55

1

T19

1

T10

1

T60

1

auto[0]

from_0to1

auto[1]

auto[0]

61

1

T19

3

T10

1

T60

1

auto[0]

from_0to1

auto[1]

auto[1]

53

1

T60

1

T127

1

T38

1

auto[1]

from_1to0

auto[0]

auto[0]

52

1

T10

1

T127

1

T38

1

auto[1]

from_1to0

auto[0]

auto[1]

42

1

T60

1

T127

1

T38

1

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T19

1

T38

1

T250

1

auto[1]

from_1to0

auto[1]

auto[1]

74

1

T19

1

T10

1

T60

1

auto[1]

from_0to1

auto[0]

auto[0]

59

1

T38

1

T105

1

T356

2

auto[1]

from_0to1

auto[0]

auto[1]

53

1

T19

1

T10

1

T60

1

auto[1]

from_0to1

auto[1]

auto[0]

58

1

T19

1

T60

1

T127

1

auto[1]

from_0to1

auto[1]

auto[1]

60

1

T19

1

T127

2

T38

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

941

1

T19

16

T10

12

T60

14

auto[1]

1016

1

T19

4

T10

8

T60

6

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

477

1

T19

3

T10

6

T60

5

from_0to1

474

1

T19

3

T10

6

T60

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

985

1

T19

9

T10

9

T60

8

auto[1]

972

1

T19

11

T10

11

T60

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

965

1

T19

8

T10

12

T60

10

auto[1]

992

1

T19

12

T10

8

T60

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

58

1

T10

1

T60

2

T38

2

auto[0]

from_1to0

auto[0]

auto[1]

59

1

T19

1

T10

2

T60

1

auto[0]

from_1to0

auto[1]

auto[0]

49

1

T19

1

T10

2

T38

3

auto[0]

from_1to0

auto[1]

auto[1]

54

1

T60

2

T38

1

T250

2

auto[0]

from_0to1

auto[0]

auto[0]

54

1

T127

1

T38

1

T102

1

auto[0]

from_0to1

auto[0]

auto[1]

57

1

T19

1

T10

1

T38

3

auto[0]

from_0to1

auto[1]

auto[0]

70

1

T60

2

T38

1

T356

2

auto[0]

from_0to1

auto[1]

auto[1]

62

1

T19

2

T10

1

T38

1

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T102

1

T357

5

T358

3

auto[1]

from_1to0

auto[0]

auto[1]

74

1

T10

1

T127

1

T250

2

auto[1]

from_1to0

auto[1]

auto[0]

61

1

T19

1

T38

2

T250

1

auto[1]

from_1to0

auto[1]

auto[1]

59

1

T127

1

T38

1

T102

2

auto[1]

from_0to1

auto[0]

auto[0]

64

1

T10

1

T60

1

T38

2

auto[1]

from_0to1

auto[0]

auto[1]

61

1

T10

1

T127

1

T250

2

auto[1]

from_0to1

auto[1]

auto[0]

58

1

T10

2

T38

2

T250

1

auto[1]

from_0to1

auto[1]

auto[1]

48

1

T60

1

T102

1

T105

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

994

1

T19

12

T10

9

T60

11

auto[1]

963

1

T19

8

T10

11

T60

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

476

1

T19

6

T10

3

T60

5

from_0to1

480

1

T19

6

T10

3

T60

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

947

1

T19

7

T10

12

T60

11

auto[1]

1010

1

T19

13

T10

8

T60

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

947

1

T19

11

T10

10

T60

7

auto[1]

1010

1

T19

9

T10

10

T60

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

64

1

T19

2

T10

1

T38

1

auto[0]

from_1to0

auto[0]

auto[1]

70

1

T60

3

T127

1

T38

2

auto[0]

from_1to0

auto[1]

auto[0]

63

1

T19

1

T60

1

T127

2

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T19

1

T10

1

T38

1

auto[0]

from_0to1

auto[0]

auto[0]

48

1

T38

3

T80

3

T148

1

auto[0]

from_0to1

auto[0]

auto[1]

68

1

T19

1

T60

1

T250

1

auto[0]

from_0to1

auto[1]

auto[0]

55

1

T38

1

T250

1

T102

2

auto[0]

from_0to1

auto[1]

auto[1]

72

1

T19

3

T60

1

T127

3

auto[1]

from_1to0

auto[0]

auto[0]

50

1

T10

1

T60

1

T127

1

auto[1]

from_1to0

auto[0]

auto[1]

50

1

T19

1

T38

1

T250

1

auto[1]

from_1to0

auto[1]

auto[0]

52

1

T127

1

T38

4

T102

1

auto[1]

from_1to0

auto[1]

auto[1]

63

1

T19

1

T38

1

T250

1

auto[1]

from_0to1

auto[0]

auto[0]

51

1

T19

1

T127

2

T38

1

auto[1]

from_0to1

auto[0]

auto[1]

51

1

T10

3

T60

1

T127

1

auto[1]

from_0to1

auto[1]

auto[0]

80

1

T19

1

T38

2

T250

1

auto[1]

from_0to1

auto[1]

auto[1]

55

1

T60

2

T250

1

T105

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

990

1

T19

9

T10

10

T60

5

auto[1]

967

1

T19

11

T10

10

T60

15

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

466

1

T19

6

T10

5

T60

6

from_0to1

458

1

T19

6

T10

5

T60

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

967

1

T19

11

T10

11

T60

11

auto[1]

990

1

T19

9

T10

9

T60

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

994

1

T19

14

T10

12

T60

10

auto[1]

963

1

T19

6

T10

8

T60

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T19

2

T60

1

T38

2

auto[0]

from_1to0

auto[0]

auto[1]

55

1

T19

1

T10

1

T127

2

auto[0]

from_1to0

auto[1]

auto[0]

56

1

T10

1

T60

1

T127

1

auto[0]

from_1to0

auto[1]

auto[1]

61

1

T60

2

T250

1

T102

1

auto[0]

from_0to1

auto[0]

auto[0]

55

1

T10

1

T38

2

T102

2

auto[0]

from_0to1

auto[0]

auto[1]

48

1

T19

1

T10

1

T38

1

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T19

1

T10

1

T38

3

auto[0]

from_0to1

auto[1]

auto[1]

69

1

T19

1

T127

1

T356

2

auto[1]

from_1to0

auto[0]

auto[0]

72

1

T19

2

T10

2

T60

1

auto[1]

from_1to0

auto[0]

auto[1]

57

1

T19

1

T10

1

T38

4

auto[1]

from_1to0

auto[1]

auto[0]

52

1

T356

2

T355

2

T259

1

auto[1]

from_1to0

auto[1]

auto[1]

50

1

T60

1

T38

1

T250

1

auto[1]

from_0to1

auto[0]

auto[0]

70

1

T19

1

T10

1

T60

2

auto[1]

from_0to1

auto[0]

auto[1]

51

1

T60

1

T127

1

T38

1

auto[1]

from_0to1

auto[1]

auto[0]

49

1

T19

1

T10

1

T38

1

auto[1]

from_0to1

auto[1]

auto[1]

50

1

T19

1

T60

2

T38

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

985

1

T19

8

T10

13

T60

11

auto[1]

972

1

T19

12

T10

7

T60

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

463

1

T19

5

T10

6

T60

4

from_0to1

460

1

T19

5

T10

5

T60

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

984

1

T19

14

T10

13

T60

10

auto[1]

973

1

T19

6

T10

7

T60

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

957

1

T19

9

T10

13

T60

12

auto[1]

1000

1

T19

11

T10

7

T60

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

52

1

T19

1

T10

1

T60

1

auto[0]

from_1to0

auto[0]

auto[1]

69

1

T19

1

T10

1

T127

2

auto[0]

from_1to0

auto[1]

auto[0]

63

1

T19

1

T127

2

T250

1

auto[0]

from_1to0

auto[1]

auto[1]

51

1

T19

1

T10

2

T250

1

auto[0]

from_0to1

auto[0]

auto[0]

57

1

T10

3

T38

2

T105

1

auto[0]

from_0to1

auto[0]

auto[1]

63

1

T19

1

T10

1

T127

1

auto[0]

from_0to1

auto[1]

auto[0]

56

1

T19

1

T60

1

T127

2

auto[0]

from_0to1

auto[1]

auto[1]

65

1

T60

1

T38

3

T259

2

auto[1]

from_1to0

auto[0]

auto[0]

52

1

T19

1

T10

1

T60

1

auto[1]

from_1to0

auto[0]

auto[1]

64

1

T10

1

T60

2

T38

3

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T38

2

T250

1

T102

1

auto[1]

from_1to0

auto[1]

auto[1]

49

1

T127

1

T38

1

T250

1

auto[1]

from_0to1

auto[0]

auto[0]

51

1

T19

2

T10

1

T60

1

auto[1]

from_0to1

auto[0]

auto[1]

49

1

T19

1

T127

1

T38

2

auto[1]

from_0to1

auto[1]

auto[0]

64

1

T127

1

T38

1

T102

1

auto[1]

from_0to1

auto[1]

auto[1]

55

1

T38

2

T250

2

T102

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

987

1

T19

12

T10

10

T60

11

auto[1]

970

1

T19

8

T10

10

T60

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

471

1

T19

4

T10

5

T60

5

from_0to1

462

1

T19

5

T10

4

T60

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

986

1

T19

12

T10

10

T60

9

auto[1]

971

1

T19

8

T10

10

T60

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

995

1

T19

11

T10

8

T60

6

auto[1]

962

1

T19

9

T10

12

T60

14

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

61

1

T38

2

T250

1

T102

2

auto[0]

from_1to0

auto[0]

auto[1]

66

1

T19

2

T10

1

T60

1

auto[0]

from_1to0

auto[1]

auto[0]

57

1

T60

2

T127

1

T250

1

auto[0]

from_1to0

auto[1]

auto[1]

50

1

T10

2

T60

1

T38

1

auto[0]

from_0to1

auto[0]

auto[0]

64

1

T19

2

T10

1

T60

2

auto[0]

from_0to1

auto[0]

auto[1]

58

1

T19

1

T60

1

T38

1

auto[0]

from_0to1

auto[1]

auto[0]

61

1

T19

1

T10

1

T250

1

auto[0]

from_0to1

auto[1]

auto[1]

68

1

T38

2

T105

1

T356

1

auto[1]

from_1to0

auto[0]

auto[0]

70

1

T127

1

T38

1

T250

1

auto[1]

from_1to0

auto[0]

auto[1]

46

1

T19

2

T10

1

T259

1

auto[1]

from_1to0

auto[1]

auto[0]

65

1

T38

2

T105

1

T355

1

auto[1]

from_1to0

auto[1]

auto[1]

56

1

T10

1

T60

1

T127

1

auto[1]

from_0to1

auto[0]

auto[0]

57

1

T10

1

T127

1

T38

2

auto[1]

from_0to1

auto[0]

auto[1]

55

1

T19

1

T10

1

T60

1

auto[1]

from_0to1

auto[1]

auto[0]

50

1

T127

2

T38

2

T259

1

auto[1]

from_0to1

auto[1]

auto[1]

49

1

T127

1

T250

2

T102

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

985

1

T19

12

T10

10

T60

10

auto[1]

972

1

T19

8

T10

10

T60

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

456

1

T19

5

T10

4

T60

3

from_0to1

452

1

T19

5

T10

4

T60

2

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1006

1

T19

8

T10

11

T60

13

auto[1]

951

1

T19

12

T10

9

T60

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

971

1

T19

11

T10

7

T60

8

auto[1]

986

1

T19

9

T10

13

T60

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

55

1

T19

1

T10

1

T38

1

auto[0]

from_1to0

auto[0]

auto[1]

48

1

T60

1

T127

1

T250

2

auto[0]

from_1to0

auto[1]

auto[0]

54

1

T19

2

T127

1

T38

3

auto[0]

from_1to0

auto[1]

auto[1]

65

1

T38

1

T356

1

T355

3

auto[0]

from_0to1

auto[0]

auto[0]

61

1

T19

1

T38

2

T250

2

auto[0]

from_0to1

auto[0]

auto[1]

76

1

T19

2

T10

1

T60

1

auto[0]

from_0to1

auto[1]

auto[0]

63

1

T19

1

T10

1

T127

1

auto[0]

from_0to1

auto[1]

auto[1]

34

1

T19

1

T60

1

T38

1

auto[1]

from_1to0

auto[0]

auto[0]

52

1

T60

1

T38

2

T250

1

auto[1]

from_1to0

auto[0]

auto[1]

64

1

T10

1

T127

1

T102

1

auto[1]

from_1to0

auto[1]

auto[0]

68

1

T19

2

T60

1

T38

4

auto[1]

from_1to0

auto[1]

auto[1]

50

1

T10

2

T38

2

T250

1

auto[1]

from_0to1

auto[0]

auto[0]

52

1

T38

2

T356

1

T355

1

auto[1]

from_0to1

auto[0]

auto[1]

62

1

T10

2

T250

1

T105

2

auto[1]

from_0to1

auto[1]

auto[0]

36

1

T127

1

T161

1

T358

1

auto[1]

from_0to1

auto[1]

auto[1]

68

1

T127

1

T38

1

T105

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

985

1

T19

12

T10

13

T60

12

auto[1]

972

1

T19

8

T10

7

T60

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

459

1

T19

3

T10

6

T60

6

from_0to1

468

1

T19

2

T10

5

T60

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

991

1

T19

13

T10

9

T60

15

auto[1]

966

1

T19

7

T10

11

T60

5

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

977

1

T19

6

T10

15

T60

11

auto[1]

980

1

T19

14

T10

5

T60

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T10

1

T60

2

T127

2

auto[0]

from_1to0

auto[0]

auto[1]

64

1

T19

1

T60

1

T38

1

auto[0]

from_1to0

auto[1]

auto[0]

56

1

T10

1

T38

3

T250

2

auto[0]

from_1to0

auto[1]

auto[1]

61

1

T10

1

T60

1

T102

1

auto[0]

from_0to1

auto[0]

auto[0]

65

1

T10

2

T60

1

T250

2

auto[0]

from_0to1

auto[0]

auto[1]

61

1

T60

2

T250

2

T105

1

auto[0]

from_0to1

auto[1]

auto[0]

52

1

T10

1

T127

1

T38

1

auto[0]

from_0to1

auto[1]

auto[1]

60

1

T10

1

T127

1

T38

1

auto[1]

from_1to0

auto[0]

auto[0]

59

1

T10

1

T60

1

T127

2

auto[1]

from_1to0

auto[0]

auto[1]

50

1

T19

1

T38

1

T102

1

auto[1]

from_1to0

auto[1]

auto[0]

52

1

T10

1

T105

1

T357

1

auto[1]

from_1to0

auto[1]

auto[1]

54

1

T19

1

T10

1

T60

1

auto[1]

from_0to1

auto[0]

auto[0]

47

1

T60

2

T127

1

T38

2

auto[1]

from_0to1

auto[0]

auto[1]

59

1

T19

1

T127

2

T38

2

auto[1]

from_0to1

auto[1]

auto[0]

71

1

T10

1

T38

3

T356

1

auto[1]

from_0to1

auto[1]

auto[1]

53

1

T19

1

T60

1

T38

1