Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	152556	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

116403

1

T4

12

T5

8

T6

66

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	136680	1			T4	8		T5	8		T6	107
values[0x0]	65589	1			T4	4		T5	6		T6	15
values[0x1]	66690	1			T4	4		T5	1		T6	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	124115	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

144844

1

T4

13

T5

8

T6

72

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1195	1			T6	3		T21	1		T1	1
valid_sources[0x01]	1016	1			T6	1		T21	1		T1	4
valid_sources[0x02]	825	1			T21	2		T1	1		T2	4
valid_sources[0x03]	1820	1			T6	3		T21	1		T1	3
valid_sources[0x04]	800	1			T6	1		T21	5		T2	3
valid_sources[0x05]	726	1			T6	2		T21	3		T2	5
valid_sources[0x06]	932	1			T21	1		T1	1		T2	8
valid_sources[0x07]	1839	1			T21	2		T1	2		T2	3
valid_sources[0x08]	1246	1			T6	3		T2	7		T8	3
valid_sources[0x09]	961	1			T21	1		T1	1		T2	6
valid_sources[0x0a]	1565	1			T21	2		T1	5		T2	5
valid_sources[0x0b]	957	1			T21	1		T1	4		T2	10
valid_sources[0x0c]	918	1			T21	3		T1	1		T2	6
valid_sources[0x0d]	887	1			T4	1		T21	2		T2	2
valid_sources[0x0e]	982	1			T6	1		T22	1		T2	6
valid_sources[0x0f]	1973	1			T6	1		T1	2		T2	5
valid_sources[0x10]	1534	1			T21	3		T2	10		T8	2
valid_sources[0x11]	1400	1			T2	6		T8	6		T34	3
valid_sources[0x12]	964	1			T21	2		T1	3		T2	5
valid_sources[0x13]	885	1			T4	2		T20	45		T21	3
valid_sources[0x14]	877	1			T6	1		T21	3		T1	1
valid_sources[0x15]	1122	1			T21	1		T1	3		T2	7
valid_sources[0x16]	915	1			T21	1		T1	1		T2	7
valid_sources[0x17]	1188	1			T6	2		T21	4		T1	1
valid_sources[0x18]	754	1			T6	1		T21	1		T1	5
valid_sources[0x19]	842	1			T21	1		T2	4		T8	3
valid_sources[0x1a]	946	1			T2	9		T8	2		T10	3
valid_sources[0x1b]	999	1			T21	1		T1	3		T2	11
valid_sources[0x1c]	1614	1			T6	4		T21	1		T1	2
valid_sources[0x1d]	838	1			T6	1		T21	1		T2	10
valid_sources[0x1e]	810	1			T6	2		T21	2		T1	4
valid_sources[0x1f]	832	1			T21	1		T1	2		T2	6
valid_sources[0x20]	800	1			T21	1		T1	3		T2	5
valid_sources[0x21]	1769	1			T21	1		T2	8		T29	1
valid_sources[0x22]	833	1			T6	1		T21	2		T1	1
valid_sources[0x23]	977	1			T6	2		T21	2		T1	7
valid_sources[0x24]	966	1			T6	3		T1	3		T2	8
valid_sources[0x25]	1342	1			T21	2		T1	3		T2	3
valid_sources[0x26]	858	1			T6	3		T21	1		T1	1
valid_sources[0x27]	938	1			T6	1		T21	1		T1	3
valid_sources[0x28]	730	1			T21	2		T1	5		T2	2
valid_sources[0x29]	901	1			T21	2		T1	2		T2	8
valid_sources[0x2a]	895	1			T4	1		T6	2		T21	4
valid_sources[0x2b]	736	1			T6	2		T21	2		T2	9
valid_sources[0x2c]	1998	1			T21	1		T1	5		T2	1
valid_sources[0x2d]	832	1			T21	1		T2	2		T8	4
valid_sources[0x2e]	1196	1			T22	1		T1	5		T2	7
valid_sources[0x2f]	871	1			T6	1		T21	1		T1	2
valid_sources[0x30]	755	1			T21	2		T22	1		T1	1
valid_sources[0x31]	1059	1			T21	2		T1	4		T2	6
valid_sources[0x32]	904	1			T1	1		T2	6		T52	1
valid_sources[0x33]	860	1			T21	1		T1	2		T2	4
valid_sources[0x34]	982	1			T21	1		T2	6		T10	1
valid_sources[0x35]	1014	1			T21	1		T2	7		T18	1
valid_sources[0x36]	815	1			T1	1		T2	7		T8	3
valid_sources[0x37]	837	1			T6	1		T21	1		T1	3
valid_sources[0x38]	2097	1			T4	2		T6	1		T21	1
valid_sources[0x39]	797	1			T6	2		T21	2		T1	5
valid_sources[0x3a]	983	1			T21	5		T1	2		T2	10
valid_sources[0x3b]	804	1			T1	3		T2	4		T3	1
valid_sources[0x3c]	750	1			T21	1		T1	4		T2	4
valid_sources[0x3d]	984	1			T21	1		T1	2		T2	3
valid_sources[0x3e]	666	1			T21	2		T1	7		T2	3
valid_sources[0x3f]	1030	1			T6	2		T21	2		T1	2
valid_sources[0x40]	1424	1			T21	1		T1	1		T2	10
valid_sources[0x41]	743	1			T6	2		T21	4		T1	5
valid_sources[0x42]	874	1			T21	2		T1	2		T2	3
valid_sources[0x43]	1317	1			T1	1		T2	2		T16	1
valid_sources[0x44]	1445	1			T21	1		T2	4		T10	10
valid_sources[0x45]	978	1			T21	4		T1	3		T2	3
valid_sources[0x46]	797	1			T1	2		T2	4		T8	4
valid_sources[0x47]	987	1			T21	2		T1	4		T2	3
valid_sources[0x48]	772	1			T6	2		T1	4		T2	2
valid_sources[0x49]	670	1			T6	5		T2	8		T8	2
valid_sources[0x4a]	879	1			T21	2		T1	3		T2	5
valid_sources[0x4b]	1161	1			T21	3		T1	2		T2	7
valid_sources[0x4c]	923	1			T2	3		T8	2		T13	1
valid_sources[0x4d]	2173	1			T1	2		T2	6		T7	2
valid_sources[0x4e]	834	1			T21	2		T1	4		T2	7
valid_sources[0x4f]	860	1			T21	1		T1	1		T2	9
valid_sources[0x50]	812	1			T6	1		T2	2		T8	3
valid_sources[0x51]	1325	1			T6	3		T21	1		T1	1
valid_sources[0x52]	973	1			T6	2		T21	5		T2	8
valid_sources[0x53]	679	1			T6	1		T21	3		T2	5
valid_sources[0x54]	2031	1			T21	2		T1	1		T2	2
valid_sources[0x55]	862	1			T6	1		T21	2		T1	3
valid_sources[0x56]	793	1			T22	1		T1	5		T2	4
valid_sources[0x57]	1008	1			T6	1		T21	5		T1	4
valid_sources[0x58]	982	1			T1	3		T2	7		T8	1
valid_sources[0x59]	2362	1			T6	1		T21	2		T1	7
valid_sources[0x5a]	1515	1			T6	1		T21	2		T1	3
valid_sources[0x5b]	1321	1			T21	9		T2	8		T8	1
valid_sources[0x5c]	1096	1			T21	2		T2	4		T8	1
valid_sources[0x5d]	901	1			T1	1		T2	3		T8	6
valid_sources[0x5e]	986	1			T21	2		T1	2		T2	3
valid_sources[0x5f]	912	1			T6	1		T21	1		T1	7
valid_sources[0x60]	949	1			T1	4		T2	4		T10	8
valid_sources[0x61]	910	1			T4	1		T21	2		T2	6
valid_sources[0x62]	963	1			T21	1		T23	2		T1	3
valid_sources[0x63]	908	1			T5	10		T21	3		T1	2
valid_sources[0x64]	1079	1			T6	1		T21	1		T1	6
valid_sources[0x65]	830	1			T6	2		T21	4		T1	1
valid_sources[0x66]	2000	1			T6	1		T21	2		T2	4
valid_sources[0x67]	1057	1			T21	3		T2	5		T8	2
valid_sources[0x68]	772	1			T6	1		T21	1		T1	6
valid_sources[0x69]	919	1			T21	4		T1	3		T2	4
valid_sources[0x6a]	1876	1			T21	3		T1	6		T2	2
valid_sources[0x6b]	1707	1			T21	4		T1	1		T2	4
valid_sources[0x6c]	787	1			T21	3		T1	1		T2	3
valid_sources[0x6d]	1154	1			T4	1		T21	2		T1	1
valid_sources[0x6e]	927	1			T21	6		T2	1		T10	5
valid_sources[0x6f]	1922	1			T21	1		T1	1		T2	3
valid_sources[0x70]	2008	1			T21	2		T1	3		T2	7
valid_sources[0x71]	667	1			T21	4		T1	2		T2	3
valid_sources[0x72]	838	1			T21	2		T2	5		T8	2
valid_sources[0x73]	794	1			T21	2		T2	6		T8	1
valid_sources[0x74]	2008	1			T21	2		T1	5		T2	9
valid_sources[0x75]	1345	1			T21	1		T1	2		T2	2
valid_sources[0x76]	744	1			T21	2		T1	2		T2	6
valid_sources[0x77]	2121	1			T21	2		T1	4		T2	3
valid_sources[0x78]	938	1			T21	3		T22	1		T2	11
valid_sources[0x79]	773	1			T21	3		T1	12		T2	4
valid_sources[0x7a]	996	1			T21	3		T2	9		T16	1
valid_sources[0x7b]	908	1			T21	1		T2	5		T16	3
valid_sources[0x7c]	798	1			T21	2		T1	6		T2	5
valid_sources[0x7d]	880	1			T21	1		T1	1		T2	4
valid_sources[0x7e]	1300	1			T1	4		T2	4		T7	3
valid_sources[0x7f]	697	1			T21	1		T1	3		T2	3
valid_sources[0x80]	1592	1			T21	2		T1	4		T2	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

62119

1

T4

7

T5

3

T6

54

values[0x0]

all_enables

biggest_size

31730

1

T4

4

T5

4

T6

7

values[0x1]

all_enables

biggest_size

22554

1

T4

1

T5

1

T6

5