Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T14

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T4,T5,T14

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T15

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T14
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T14

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T15
0	1	Covered	T67,T100,T101
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T15
0	1	Covered	T4,T5,T15
1	0	Covered	T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T5,T15
1	-	Covered	T4,T5,T15

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T5,T14
DetectSt	168	Covered	T4,T5,T15
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T4,T5,T15

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T5,T15
DebounceSt->IdleSt	163	Covered	T14,T41,T46
DetectSt->IdleSt	186	Covered	T67,T100,T101
DetectSt->StableSt	191	Covered	T4,T5,T15
IdleSt->DebounceSt	148	Covered	T4,T5,T14
StableSt->IdleSt	206	Covered	T4,T5,T15

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T5,T14
0	1	Covered	T4,T5,T14
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T15
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T5,T14
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T5,T15
DebounceSt	-	0	1	0	-	-	-	Covered	T14,T41,T46
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T5,T14
DetectSt	-	-	-	-	1	-	-	Covered	T67,T100,T101
DetectSt	-	-	-	-	0	1	-	Covered	T4,T5,T15
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T5,T15
StableSt	-	-	-	-	-	-	0	Covered	T4,T5,T15
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10142749	236	0	0
CntIncr_A	10142749	234802	0	0
CntNoWrap_A	10142749	9506939	0	0
DetectStDropOut_A	10142749	3	0	0
DetectedOut_A	10142749	682	0	0
DetectedPulseOut_A	10142749	101	0	0
DisabledIdleSt_A	10142749	9266932	0	0
DisabledNoDetection_A	10142749	9269230	0	0
EnterDebounceSt_A	10142749	136	0	0
EnterDetectSt_A	10142749	104	0	0
EnterStableSt_A	10142749	101	0	0
PulseIsPulse_A	10142749	101	0	0
StayInStableSt	10142749	581	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	10142749	7002	0	0
gen_low_level_sva.LowLevelEvent_A	10142749	9509518	0	0
gen_not_sticky_sva.StableStDropOut_A	10142749	100	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	236	0	0
T1	24783	0	0	0
T2	30367	0	0	0
T4	727	4	0	0
T5	703	2	0	0
T6	2902	0	0	0
T14	8024	1	0	0
T15	0	2	0	0
T20	492	0	0	0
T21	4666	0	0	0
T22	406	0	0	0
T23	535	0	0	0
T41	0	3	0	0
T43	0	4	0	0
T45	0	2	0	0
T46	0	5	0	0
T47	0	4	0	0
T83	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	234802	0	0
T1	24783	0	0	0
T2	30367	0	0	0
T4	727	93	0	0
T5	703	33	0	0
T6	2902	0	0	0
T14	8024	7425	0	0
T15	0	39	0	0
T20	492	0	0	0
T21	4666	0	0	0
T22	406	0	0	0
T23	535	0	0	0
T41	0	43	0	0
T43	0	52	0	0
T45	0	100	0	0
T46	0	190	0	0
T47	0	79	0	0
T83	0	47843	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9506939	0	0
T1	24783	24321	0	0
T2	30367	29895	0	0
T4	727	322	0	0
T5	703	300	0	0
T6	2902	497	0	0
T14	8024	7622	0	0
T20	492	91	0	0
T21	4666	4265	0	0
T22	406	5	0	0
T23	535	134	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	3	0	0
T35	6737	0	0	0
T67	160371	1	0	0
T85	20284	0	0	0
T100	0	1	0	0
T101	0	1	0	0
T107	724	0	0	0
T108	524	0	0	0
T109	561	0	0	0
T110	687	0	0	0
T111	578	0	0	0
T112	971	0	0	0
T113	429	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	682	0	0
T1	24783	0	0	0
T2	30367	0	0	0
T4	727	13	0	0
T5	703	10	0	0
T6	2902	0	0	0
T14	8024	0	0	0
T15	0	10	0	0
T20	492	0	0	0
T21	4666	0	0	0
T22	406	0	0	0
T23	535	0	0	0
T38	0	22	0	0
T41	0	10	0	0
T43	0	10	0	0
T45	0	10	0	0
T46	0	13	0	0
T47	0	24	0	0
T83	0	9	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	101	0	0
T1	24783	0	0	0
T2	30367	0	0	0
T4	727	2	0	0
T5	703	1	0	0
T6	2902	0	0	0
T14	8024	0	0	0
T15	0	1	0	0
T20	492	0	0	0
T21	4666	0	0	0
T22	406	0	0	0
T23	535	0	0	0
T38	0	3	0	0
T41	0	1	0	0
T43	0	2	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	2	0	0
T83	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9266932	0	0
T1	24783	24321	0	0
T2	30367	29895	0	0
T4	727	129	0	0
T5	703	205	0	0
T6	2902	497	0	0
T14	8024	174	0	0
T20	492	91	0	0
T21	4666	4265	0	0
T22	406	5	0	0
T23	535	134	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9269230	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	129	0	0
T5	703	205	0	0
T6	2902	502	0	0
T14	8024	174	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	136	0	0
T1	24783	0	0	0
T2	30367	0	0	0
T4	727	2	0	0
T5	703	1	0	0
T6	2902	0	0	0
T14	8024	1	0	0
T15	0	1	0	0
T20	492	0	0	0
T21	4666	0	0	0
T22	406	0	0	0
T23	535	0	0	0
T41	0	2	0	0
T43	0	2	0	0
T45	0	1	0	0
T46	0	3	0	0
T47	0	2	0	0
T83	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	104	0	0
T1	24783	0	0	0
T2	30367	0	0	0
T4	727	2	0	0
T5	703	1	0	0
T6	2902	0	0	0
T14	8024	0	0	0
T15	0	1	0	0
T20	492	0	0	0
T21	4666	0	0	0
T22	406	0	0	0
T23	535	0	0	0
T38	0	3	0	0
T41	0	1	0	0
T43	0	2	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	2	0	0
T83	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	101	0	0
T1	24783	0	0	0
T2	30367	0	0	0
T4	727	2	0	0
T5	703	1	0	0
T6	2902	0	0	0
T14	8024	0	0	0
T15	0	1	0	0
T20	492	0	0	0
T21	4666	0	0	0
T22	406	0	0	0
T23	535	0	0	0
T38	0	3	0	0
T41	0	1	0	0
T43	0	2	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	2	0	0
T83	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	101	0	0
T1	24783	0	0	0
T2	30367	0	0	0
T4	727	2	0	0
T5	703	1	0	0
T6	2902	0	0	0
T14	8024	0	0	0
T15	0	1	0	0
T20	492	0	0	0
T21	4666	0	0	0
T22	406	0	0	0
T23	535	0	0	0
T38	0	3	0	0
T41	0	1	0	0
T43	0	2	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	2	0	0
T83	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	581	0	0
T1	24783	0	0	0
T2	30367	0	0	0
T4	727	11	0	0
T5	703	9	0	0
T6	2902	0	0	0
T14	8024	0	0	0
T15	0	9	0	0
T20	492	0	0	0
T21	4666	0	0	0
T22	406	0	0	0
T23	535	0	0	0
T38	0	19	0	0
T41	0	9	0	0
T43	0	8	0	0
T45	0	9	0	0
T46	0	11	0	0
T47	0	22	0	0
T83	0	8	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	7002	0	0
T1	24783	12	0	0
T2	30367	34	0	0
T3	0	2	0	0
T4	727	3	0	0
T5	703	3	0	0
T6	2902	18	0	0
T14	8024	3	0	0
T15	0	3	0	0
T20	492	11	0	0
T21	4666	28	0	0
T22	406	0	0	0
T23	535	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9509518	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	100	0	0
T1	24783	0	0	0
T2	30367	0	0	0
T4	727	2	0	0
T5	703	1	0	0
T6	2902	0	0	0
T14	8024	0	0	0
T15	0	1	0	0
T20	492	0	0	0
T21	4666	0	0	0
T22	406	0	0	0
T23	535	0	0	0
T38	0	3	0	0
T41	0	1	0	0
T43	0	2	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	2	0	0
T83	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T12,T27,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T12,T27,T28

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T12,T49,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T27,T28
1	0	Covered	T4,T5,T6
1	1	Covered	T12,T27,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T37,T50
0	1	Covered	T49,T73,T81
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T37,T50
0	1	Unreachable
1	0	Covered	T12,T37,T50

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T27,T28
DetectSt	168	Covered	T12,T49,T37
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T12,T37,T50

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T49,T37
DebounceSt->IdleSt	163	Covered	T27,T28,T49
DetectSt->IdleSt	186	Covered	T49,T73,T81
DetectSt->StableSt	191	Covered	T12,T37,T50
IdleSt->DebounceSt	148	Covered	T12,T27,T28
StableSt->IdleSt	206	Covered	T12,T37,T50

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T27,T28
0	1	Covered	T12,T27,T28
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T49,T37
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T27,T28
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T49,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T27,T28,T49
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T27,T28
DetectSt	-	-	-	-	1	-	-	Covered	T49,T73,T81
DetectSt	-	-	-	-	0	1	-	Covered	T12,T37,T50
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T37,T50
StableSt	-	-	-	-	-	-	0	Covered	T12,T37,T50
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10142749	161	0	0
CntIncr_A	10142749	124869	0	0
CntNoWrap_A	10142749	9507014	0	0
DetectStDropOut_A	10142749	11	0	0
DetectedOut_A	10142749	192920	0	0
DetectedPulseOut_A	10142749	45	0	0
DisabledIdleSt_A	10142749	8569085	0	0
DisabledNoDetection_A	10142749	8571427	0	0
EnterDebounceSt_A	10142749	107	0	0
EnterDetectSt_A	10142749	56	0	0
EnterStableSt_A	10142749	45	0	0
PulseIsPulse_A	10142749	45	0	0
StayInStableSt	10142749	192875	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	10142749	7002	0	0
gen_low_level_sva.LowLevelEvent_A	10142749	9509518	0	0
gen_sticky_sva.StableStDropOut_A	10142749	6486	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	161	0	0
T12	944	2	0	0
T13	16325	0	0	0
T27	1497	2	0	0
T28	0	4	0	0
T30	527	0	0	0
T34	36282	0	0	0
T37	0	2	0	0
T42	24852	0	0	0
T49	0	5	0	0
T50	0	2	0	0
T51	0	2	0	0
T54	489	0	0	0
T59	524	0	0	0
T60	503	0	0	0
T71	0	6	0	0
T72	0	6	0	0
T73	0	6	0	0
T74	407	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	124869	0	0
T12	944	74	0	0
T13	16325	0	0	0
T27	1497	144	0	0
T28	0	320	0	0
T30	527	0	0	0
T34	36282	0	0	0
T37	0	58	0	0
T42	24852	0	0	0
T49	0	225	0	0
T50	0	62	0	0
T51	0	52	0	0
T54	489	0	0	0
T59	524	0	0	0
T60	503	0	0	0
T71	0	252	0	0
T72	0	162	0	0
T73	0	56224	0	0
T74	407	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9507014	0	0
T1	24783	24321	0	0
T2	30367	29895	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	4265	0	0
T22	406	5	0	0
T23	535	134	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	11	0	0
T37	2838	0	0	0
T39	126204	0	0	0
T49	747	2	0	0
T50	736	0	0	0
T51	1319	0	0	0
T69	29566	0	0	0
T73	0	1	0	0
T81	0	1	0	0
T101	0	2	0	0
T122	405	0	0	0
T123	344414	0	0	0
T124	0	3	0	0
T125	0	1	0	0
T126	0	1	0	0
T127	502	0	0	0
T128	615	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	192920	0	0
T12	944	360	0	0
T13	16325	0	0	0
T27	1497	0	0	0
T30	527	0	0	0
T34	36282	0	0	0
T37	0	267	0	0
T42	24852	0	0	0
T50	0	106	0	0
T51	0	393	0	0
T54	489	0	0	0
T59	524	0	0	0
T60	503	0	0	0
T71	0	815	0	0
T72	0	758	0	0
T73	0	756	0	0
T74	407	0	0	0
T78	0	657	0	0
T80	0	17	0	0
T117	0	292	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	45	0	0
T12	944	1	0	0
T13	16325	0	0	0
T27	1497	0	0	0
T30	527	0	0	0
T34	36282	0	0	0
T37	0	1	0	0
T42	24852	0	0	0
T50	0	1	0	0
T51	0	1	0	0
T54	489	0	0	0
T59	524	0	0	0
T60	503	0	0	0
T71	0	3	0	0
T72	0	3	0	0
T73	0	2	0	0
T74	407	0	0	0
T78	0	1	0	0
T80	0	1	0	0
T117	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	8569085	0	0
T1	24783	24321	0	0
T2	30367	29895	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	4265	0	0
T22	406	5	0	0
T23	535	134	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	8571427	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	107	0	0
T12	944	1	0	0
T13	16325	0	0	0
T27	1497	2	0	0
T28	0	4	0	0
T30	527	0	0	0
T34	36282	0	0	0
T37	0	1	0	0
T42	24852	0	0	0
T49	0	3	0	0
T50	0	1	0	0
T51	0	1	0	0
T54	489	0	0	0
T59	524	0	0	0
T60	503	0	0	0
T71	0	3	0	0
T72	0	3	0	0
T73	0	3	0	0
T74	407	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	56	0	0
T12	944	1	0	0
T13	16325	0	0	0
T27	1497	0	0	0
T30	527	0	0	0
T34	36282	0	0	0
T37	0	1	0	0
T42	24852	0	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	1	0	0
T54	489	0	0	0
T59	524	0	0	0
T60	503	0	0	0
T71	0	3	0	0
T72	0	3	0	0
T73	0	3	0	0
T74	407	0	0	0
T80	0	1	0	0
T117	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	45	0	0
T12	944	1	0	0
T13	16325	0	0	0
T27	1497	0	0	0
T30	527	0	0	0
T34	36282	0	0	0
T37	0	1	0	0
T42	24852	0	0	0
T50	0	1	0	0
T51	0	1	0	0
T54	489	0	0	0
T59	524	0	0	0
T60	503	0	0	0
T71	0	3	0	0
T72	0	3	0	0
T73	0	2	0	0
T74	407	0	0	0
T78	0	1	0	0
T80	0	1	0	0
T117	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	45	0	0
T12	944	1	0	0
T13	16325	0	0	0
T27	1497	0	0	0
T30	527	0	0	0
T34	36282	0	0	0
T37	0	1	0	0
T42	24852	0	0	0
T50	0	1	0	0
T51	0	1	0	0
T54	489	0	0	0
T59	524	0	0	0
T60	503	0	0	0
T71	0	3	0	0
T72	0	3	0	0
T73	0	2	0	0
T74	407	0	0	0
T78	0	1	0	0
T80	0	1	0	0
T117	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	192875	0	0
T12	944	359	0	0
T13	16325	0	0	0
T27	1497	0	0	0
T30	527	0	0	0
T34	36282	0	0	0
T37	0	266	0	0
T42	24852	0	0	0
T50	0	105	0	0
T51	0	392	0	0
T54	489	0	0	0
T59	524	0	0	0
T60	503	0	0	0
T71	0	812	0	0
T72	0	755	0	0
T73	0	754	0	0
T74	407	0	0	0
T78	0	656	0	0
T80	0	16	0	0
T117	0	291	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	7002	0	0
T1	24783	12	0	0
T2	30367	34	0	0
T3	0	2	0	0
T4	727	3	0	0
T5	703	3	0	0
T6	2902	18	0	0
T14	8024	3	0	0
T15	0	3	0	0
T20	492	11	0	0
T21	4666	28	0	0
T22	406	0	0	0
T23	535	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9509518	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	6486	0	0
T12	944	61	0	0
T13	16325	0	0	0
T27	1497	0	0	0
T30	527	0	0	0
T34	36282	0	0	0
T37	0	136	0	0
T42	24852	0	0	0
T50	0	122	0	0
T51	0	388	0	0
T54	489	0	0	0
T59	524	0	0	0
T60	503	0	0	0
T71	0	751	0	0
T72	0	593	0	0
T73	0	441	0	0
T74	407	0	0	0
T78	0	73	0	0
T80	0	57	0	0
T117	0	81	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T20,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T20,T3
1	1	Covered	T6,T20,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T12,T27,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T12,T27,T28

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T12,T28,T49

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T27,T28
1	0	Covered	T6,T20,T3
1	1	Covered	T12,T27,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T28,T49,T51
0	1	Covered	T12,T37,T81
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T49,T51
0	1	Unreachable
1	0	Covered	T28,T49,T51

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T27,T28
DetectSt	168	Covered	T12,T28,T49
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T28,T49,T51

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T28,T49
DebounceSt->IdleSt	163	Covered	T12,T27,T50
DetectSt->IdleSt	186	Covered	T12,T37,T81
DetectSt->StableSt	191	Covered	T28,T49,T51
IdleSt->DebounceSt	148	Covered	T12,T27,T28
StableSt->IdleSt	206	Covered	T28,T49,T51

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T27,T28
0	1	Covered	T12,T27,T28
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T28,T49
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T27,T28
IdleSt	0	-	-	-	-	-	-	Covered	T6,T20,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T28,T49
DebounceSt	-	0	1	0	-	-	-	Covered	T12,T27,T50
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T27,T28
DetectSt	-	-	-	-	1	-	-	Covered	T12,T37,T81
DetectSt	-	-	-	-	0	1	-	Covered	T28,T49,T51
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T28,T49,T51
StableSt	-	-	-	-	-	-	0	Covered	T28,T49,T51
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10142749	169	0	0
CntIncr_A	10142749	6607	0	0
CntNoWrap_A	10142749	9507006	0	0
DetectStDropOut_A	10142749	12	0	0
DetectedOut_A	10142749	5587	0	0
DetectedPulseOut_A	10142749	38	0	0
DisabledIdleSt_A	10142749	8569085	0	0
DisabledNoDetection_A	10142749	8571427	0	0
EnterDebounceSt_A	10142749	121	0	0
EnterDetectSt_A	10142749	50	0	0
EnterStableSt_A	10142749	38	0	0
PulseIsPulse_A	10142749	38	0	0
StayInStableSt	10142749	5549	0	0
gen_high_level_sva.HighLevelEvent_A	10142749	9509518	0	0
gen_sticky_sva.StableStDropOut_A	10142749	917396	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	169	0	0
T12	944	4	0	0
T13	16325	0	0	0
T27	1497	2	0	0
T28	0	2	0	0
T30	527	0	0	0
T34	36282	0	0	0
T37	0	6	0	0
T42	24852	0	0	0
T49	0	2	0	0
T50	0	2	0	0
T51	0	2	0	0
T54	489	0	0	0
T59	524	0	0	0
T60	503	0	0	0
T71	0	11	0	0
T72	0	11	0	0
T73	0	8	0	0
T74	407	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	6607	0	0
T12	944	63	0	0
T13	16325	0	0	0
T27	1497	110	0	0
T28	0	50	0	0
T30	527	0	0	0
T34	36282	0	0	0
T37	0	246	0	0
T42	24852	0	0	0
T49	0	27	0	0
T50	0	28	0	0
T51	0	89	0	0
T54	489	0	0	0
T59	524	0	0	0
T60	503	0	0	0
T71	0	627	0	0
T72	0	638	0	0
T73	0	397	0	0
T74	407	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9507006	0	0
T1	24783	24321	0	0
T2	30367	29895	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	4265	0	0
T22	406	5	0	0
T23	535	134	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	12	0	0
T12	944	1	0	0
T13	16325	0	0	0
T27	1497	0	0	0
T30	527	0	0	0
T34	36282	0	0	0
T37	0	3	0	0
T42	24852	0	0	0
T54	489	0	0	0
T59	524	0	0	0
T60	503	0	0	0
T74	407	0	0	0
T81	0	3	0	0
T101	0	1	0	0
T126	0	3	0	0
T129	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	5587	0	0
T28	1114	314	0	0
T37	2838	0	0	0
T39	126204	0	0	0
T45	764	0	0	0
T49	747	129	0	0
T51	0	668	0	0
T65	2124	0	0	0
T69	29566	0	0	0
T73	0	1	0	0
T78	0	124	0	0
T80	0	27	0	0
T117	0	113	0	0
T118	0	168	0	0
T119	0	120	0	0
T120	0	599	0	0
T121	432	0	0	0
T122	405	0	0	0
T123	344414	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	38	0	0
T28	1114	1	0	0
T37	2838	0	0	0
T39	126204	0	0	0
T45	764	0	0	0
T49	747	1	0	0
T51	0	1	0	0
T65	2124	0	0	0
T69	29566	0	0	0
T73	0	1	0	0
T78	0	1	0	0
T80	0	1	0	0
T117	0	1	0	0
T118	0	2	0	0
T119	0	1	0	0
T120	0	3	0	0
T121	432	0	0	0
T122	405	0	0	0
T123	344414	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	8569085	0	0
T1	24783	24321	0	0
T2	30367	29895	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	4265	0	0
T22	406	5	0	0
T23	535	134	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	8571427	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	121	0	0
T12	944	3	0	0
T13	16325	0	0	0
T27	1497	2	0	0
T28	0	1	0	0
T30	527	0	0	0
T34	36282	0	0	0
T37	0	3	0	0
T42	24852	0	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T54	489	0	0	0
T59	524	0	0	0
T60	503	0	0	0
T71	0	11	0	0
T72	0	11	0	0
T73	0	7	0	0
T74	407	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	50	0	0
T12	944	1	0	0
T13	16325	0	0	0
T27	1497	0	0	0
T28	0	1	0	0
T30	527	0	0	0
T34	36282	0	0	0
T37	0	3	0	0
T42	24852	0	0	0
T49	0	1	0	0
T51	0	1	0	0
T54	489	0	0	0
T59	524	0	0	0
T60	503	0	0	0
T73	0	1	0	0
T74	407	0	0	0
T78	0	1	0	0
T80	0	1	0	0
T117	0	1	0	0
T118	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	38	0	0
T28	1114	1	0	0
T37	2838	0	0	0
T39	126204	0	0	0
T45	764	0	0	0
T49	747	1	0	0
T51	0	1	0	0
T65	2124	0	0	0
T69	29566	0	0	0
T73	0	1	0	0
T78	0	1	0	0
T80	0	1	0	0
T117	0	1	0	0
T118	0	2	0	0
T119	0	1	0	0
T120	0	3	0	0
T121	432	0	0	0
T122	405	0	0	0
T123	344414	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	38	0	0
T28	1114	1	0	0
T37	2838	0	0	0
T39	126204	0	0	0
T45	764	0	0	0
T49	747	1	0	0
T51	0	1	0	0
T65	2124	0	0	0
T69	29566	0	0	0
T73	0	1	0	0
T78	0	1	0	0
T80	0	1	0	0
T117	0	1	0	0
T118	0	2	0	0
T119	0	1	0	0
T120	0	3	0	0
T121	432	0	0	0
T122	405	0	0	0
T123	344414	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	5549	0	0
T28	1114	313	0	0
T37	2838	0	0	0
T39	126204	0	0	0
T45	764	0	0	0
T49	747	128	0	0
T51	0	667	0	0
T65	2124	0	0	0
T69	29566	0	0	0
T78	0	123	0	0
T80	0	26	0	0
T117	0	112	0	0
T118	0	166	0	0
T119	0	119	0	0
T120	0	596	0	0
T121	432	0	0	0
T122	405	0	0	0
T123	344414	0	0	0
T130	0	296	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9509518	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	917396	0	0
T28	1114	303	0	0
T37	2838	0	0	0
T39	126204	0	0	0
T45	764	0	0	0
T49	747	148	0	0
T51	0	76	0	0
T65	2124	0	0	0
T69	29566	0	0	0
T73	0	56101	0	0
T78	0	668	0	0
T80	0	30	0	0
T117	0	312	0	0
T118	0	67	0	0
T119	0	228	0	0
T120	0	315695	0	0
T121	432	0	0	0
T122	405	0	0	0
T123	344414	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T20,T21

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T12,T27,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T12,T27,T28

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T12,T27,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T27,T28
1	0	Covered	T6,T20,T21
1	1	Covered	T12,T27,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T27,T28
0	1	Covered	T12,T49,T80
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T27,T28
0	1	Unreachable
1	0	Covered	T12,T27,T28

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T27,T28
DetectSt	168	Covered	T12,T27,T28
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T12,T27,T28

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T27,T28
DebounceSt->IdleSt	163	Covered	T12,T37,T71
DetectSt->IdleSt	186	Covered	T12,T49,T80
DetectSt->StableSt	191	Covered	T12,T27,T28
IdleSt->DebounceSt	148	Covered	T12,T27,T28
StableSt->IdleSt	206	Covered	T12,T27,T28

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T27,T28
0	1	Covered	T12,T27,T28
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T27,T28
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T27,T28
IdleSt	0	-	-	-	-	-	-	Covered	T6,T20,T21
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T27,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T12,T37,T71
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T27,T28
DetectSt	-	-	-	-	1	-	-	Covered	T12,T49,T80
DetectSt	-	-	-	-	0	1	-	Covered	T12,T27,T28
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T27,T28
StableSt	-	-	-	-	-	-	0	Covered	T12,T27,T28
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10142749	147	0	0
CntIncr_A	10142749	88612	0	0
CntNoWrap_A	10142749	9507028	0	0
DetectStDropOut_A	10142749	7	0	0
DetectedOut_A	10142749	410845	0	0
DetectedPulseOut_A	10142749	51	0	0
DisabledIdleSt_A	10142749	8569085	0	0
DisabledNoDetection_A	10142749	8571427	0	0
EnterDebounceSt_A	10142749	91	0	0
EnterDetectSt_A	10142749	58	0	0
EnterStableSt_A	10142749	51	0	0
PulseIsPulse_A	10142749	51	0	0
StayInStableSt	10142749	410794	0	0
gen_high_event_sva.HighLevelEvent_A	10142749	9509518	0	0
gen_high_level_sva.HighLevelEvent_A	10142749	9509518	0	0
gen_sticky_sva.StableStDropOut_A	10142749	435113	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	147	0	0
T12	944	5	0	0
T13	16325	0	0	0
T27	1497	2	0	0
T28	0	2	0	0
T30	527	0	0	0
T34	36282	0	0	0
T37	0	3	0	0
T42	24852	0	0	0
T49	0	6	0	0
T50	0	2	0	0
T51	0	2	0	0
T54	489	0	0	0
T59	524	0	0	0
T60	503	0	0	0
T71	0	11	0	0
T72	0	6	0	0
T73	0	5	0	0
T74	407	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	88612	0	0
T12	944	186	0	0
T13	16325	0	0	0
T27	1497	18	0	0
T28	0	30	0	0
T30	527	0	0	0
T34	36282	0	0	0
T37	0	198	0	0
T42	24852	0	0	0
T49	0	270	0	0
T50	0	69	0	0
T51	0	100	0	0
T54	489	0	0	0
T59	524	0	0	0
T60	503	0	0	0
T71	0	814	0	0
T72	0	228	0	0
T73	0	112	0	0
T74	407	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9507028	0	0
T1	24783	24321	0	0
T2	30367	29895	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	4265	0	0
T22	406	5	0	0
T23	535	134	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	7	0	0
T12	944	1	0	0
T13	16325	0	0	0
T27	1497	0	0	0
T30	527	0	0	0
T34	36282	0	0	0
T42	24852	0	0	0
T49	0	2	0	0
T54	489	0	0	0
T59	524	0	0	0
T60	503	0	0	0
T74	407	0	0	0
T80	0	1	0	0
T126	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	410845	0	0
T12	944	1	0	0
T13	16325	0	0	0
T27	1497	40	0	0
T28	0	153	0	0
T30	527	0	0	0
T34	36282	0	0	0
T42	24852	0	0	0
T49	0	1	0	0
T50	0	178	0	0
T51	0	529	0	0
T54	489	0	0	0
T59	524	0	0	0
T60	503	0	0	0
T72	0	828	0	0
T73	0	499	0	0
T74	407	0	0	0
T78	0	276	0	0
T117	0	75	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	51	0	0
T12	944	1	0	0
T13	16325	0	0	0
T27	1497	1	0	0
T28	0	1	0	0
T30	527	0	0	0
T34	36282	0	0	0
T42	24852	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T54	489	0	0	0
T59	524	0	0	0
T60	503	0	0	0
T72	0	3	0	0
T73	0	2	0	0
T74	407	0	0	0
T78	0	1	0	0
T117	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	8569085	0	0
T1	24783	24321	0	0
T2	30367	29895	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	4265	0	0
T22	406	5	0	0
T23	535	134	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	8571427	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	91	0	0
T12	944	3	0	0
T13	16325	0	0	0
T27	1497	1	0	0
T28	0	1	0	0
T30	527	0	0	0
T34	36282	0	0	0
T37	0	3	0	0
T42	24852	0	0	0
T49	0	3	0	0
T50	0	1	0	0
T51	0	1	0	0
T54	489	0	0	0
T59	524	0	0	0
T60	503	0	0	0
T71	0	11	0	0
T72	0	3	0	0
T73	0	3	0	0
T74	407	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	58	0	0
T12	944	2	0	0
T13	16325	0	0	0
T27	1497	1	0	0
T28	0	1	0	0
T30	527	0	0	0
T34	36282	0	0	0
T42	24852	0	0	0
T49	0	3	0	0
T50	0	1	0	0
T51	0	1	0	0
T54	489	0	0	0
T59	524	0	0	0
T60	503	0	0	0
T72	0	3	0	0
T73	0	2	0	0
T74	407	0	0	0
T80	0	1	0	0
T117	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	51	0	0
T12	944	1	0	0
T13	16325	0	0	0
T27	1497	1	0	0
T28	0	1	0	0
T30	527	0	0	0
T34	36282	0	0	0
T42	24852	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T54	489	0	0	0
T59	524	0	0	0
T60	503	0	0	0
T72	0	3	0	0
T73	0	2	0	0
T74	407	0	0	0
T78	0	1	0	0
T117	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	51	0	0
T12	944	1	0	0
T13	16325	0	0	0
T27	1497	1	0	0
T28	0	1	0	0
T30	527	0	0	0
T34	36282	0	0	0
T42	24852	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T54	489	0	0	0
T59	524	0	0	0
T60	503	0	0	0
T72	0	3	0	0
T73	0	2	0	0
T74	407	0	0	0
T78	0	1	0	0
T117	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	410794	0	0
T27	1497	39	0	0
T28	0	152	0	0
T36	856	0	0	0
T42	24852	0	0	0
T43	599	0	0	0
T50	0	177	0	0
T51	0	528	0	0
T55	492	0	0	0
T61	523	0	0	0
T62	1947	0	0	0
T72	0	825	0	0
T73	0	497	0	0
T78	0	275	0	0
T117	0	74	0	0
T118	0	26	0	0
T131	0	432	0	0
T132	414	0	0	0
T133	416	0	0	0
T134	630	0	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9509518	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9509518	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	435113	0	0
T12	944	113	0	0
T13	16325	0	0	0
T27	1497	185	0	0
T28	0	495	0	0
T30	527	0	0	0
T34	36282	0	0	0
T42	24852	0	0	0
T49	0	26	0	0
T50	0	55	0	0
T51	0	224	0	0
T54	489	0	0	0
T59	524	0	0	0
T60	503	0	0	0
T72	0	494	0	0
T73	0	56782	0	0
T74	407	0	0	0
T78	0	520	0	0
T117	0	369	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T36,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T7,T36,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T36,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T36,T37
1	0	Covered	T4,T5,T6
1	1	Covered	T7,T36,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T36,T37
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T36,T37
0	1	Covered	T7,T36,T37
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T36,T37
1	-	Covered	T7,T36,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T36,T37
DetectSt	168	Covered	T7,T36,T37
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T7,T36,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T36,T37
DebounceSt->IdleSt	163	Covered	T75,T135,T76
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T7,T36,T37
IdleSt->DebounceSt	148	Covered	T7,T36,T37
StableSt->IdleSt	206	Covered	T7,T36,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T36,T37
0	1	Covered	T7,T36,T37
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T36,T37
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T36,T37
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T36,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T135
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T36,T37
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T7,T36,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T36,T37
StableSt	-	-	-	-	-	-	0	Covered	T7,T36,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10142749	95	0	0
CntIncr_A	10142749	87555	0	0
CntNoWrap_A	10142749	9507080	0	0
DetectStDropOut_A	10142749	0	0	0
DetectedOut_A	10142749	247164	0	0
DetectedPulseOut_A	10142749	46	0	0
DisabledIdleSt_A	10142749	8906656	0	0
DisabledNoDetection_A	10142749	8908936	0	0
EnterDebounceSt_A	10142749	49	0	0
EnterDetectSt_A	10142749	46	0	0
EnterStableSt_A	10142749	46	0	0
PulseIsPulse_A	10142749	46	0	0
StayInStableSt	10142749	247097	0	0
gen_high_level_sva.HighLevelEvent_A	10142749	9509518	0	0
gen_not_sticky_sva.StableStDropOut_A	10142749	25	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	95	0	0
T7	624	4	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	2	0	0
T37	0	4	0	0
T38	0	2	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T67	0	2	0	0
T77	0	2	0	0
T136	0	4	0	0
T137	0	2	0	0
T138	0	2	0	0
T139	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	87555	0	0
T7	624	26	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	67	0	0
T37	0	20	0	0
T38	0	13	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T67	0	21385	0	0
T77	0	47271	0	0
T136	0	126	0	0
T137	0	50	0	0
T138	0	43	0	0
T139	0	28	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9507080	0	0
T1	24783	24321	0	0
T2	30367	29895	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	4265	0	0
T22	406	5	0	0
T23	535	134	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	247164	0	0
T7	624	96	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	47	0	0
T37	0	100	0	0
T38	0	43	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T67	0	77241	0	0
T77	0	159531	0	0
T136	0	78	0	0
T137	0	44	0	0
T138	0	44	0	0
T139	0	38	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	46	0	0
T7	624	2	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T67	0	1	0	0
T77	0	1	0	0
T136	0	2	0	0
T137	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	8906656	0	0
T1	24783	24321	0	0
T2	30367	29895	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	4265	0	0
T22	406	5	0	0
T23	535	134	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	8908936	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	49	0	0
T7	624	2	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T67	0	1	0	0
T77	0	1	0	0
T136	0	2	0	0
T137	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	46	0	0
T7	624	2	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T67	0	1	0	0
T77	0	1	0	0
T136	0	2	0	0
T137	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	46	0	0
T7	624	2	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T67	0	1	0	0
T77	0	1	0	0
T136	0	2	0	0
T137	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	46	0	0
T7	624	2	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T67	0	1	0	0
T77	0	1	0	0
T136	0	2	0	0
T137	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	247097	0	0
T7	624	94	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	46	0	0
T37	0	97	0	0
T38	0	41	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T67	0	77239	0	0
T77	0	159530	0	0
T136	0	75	0	0
T137	0	43	0	0
T138	0	42	0	0
T139	0	36	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9509518	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	25	0	0
T7	624	2	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T77	0	1	0	0
T78	0	1	0	0
T131	0	1	0	0
T136	0	1	0	0
T137	0	1	0	0
T140	0	1	0	0
T141	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T10,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T7,T10,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T10,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T10,T36
1	0	Covered	T6,T20,T1
1	1	Covered	T7,T10,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T36
0	1	Covered	T77,T78
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T36
0	1	Covered	T7,T10,T36
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T10,T36
1	-	Covered	T7,T10,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T10,T36
DetectSt	168	Covered	T7,T10,T36
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T7,T10,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T10,T36
DebounceSt->IdleSt	163	Covered	T38,T142,T75
DetectSt->IdleSt	186	Covered	T77,T78
DetectSt->StableSt	191	Covered	T7,T10,T36
IdleSt->DebounceSt	148	Covered	T7,T10,T36
StableSt->IdleSt	206	Covered	T7,T10,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T10,T36
0	1	Covered	T7,T10,T36
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T36
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T10,T36
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T10,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T38,T142,T143
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T10,T36
DetectSt	-	-	-	-	1	-	-	Covered	T77,T78
DetectSt	-	-	-	-	0	1	-	Covered	T7,T10,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T10,T36
StableSt	-	-	-	-	-	-	0	Covered	T7,T10,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10142749	161	0	0
CntIncr_A	10142749	201502	0	0
CntNoWrap_A	10142749	9507014	0	0
DetectStDropOut_A	10142749	2	0	0
DetectedOut_A	10142749	197226	0	0
DetectedPulseOut_A	10142749	75	0	0
DisabledIdleSt_A	10142749	8678334	0	0
DisabledNoDetection_A	10142749	8680617	0	0
EnterDebounceSt_A	10142749	84	0	0
EnterDetectSt_A	10142749	77	0	0
EnterStableSt_A	10142749	75	0	0
PulseIsPulse_A	10142749	75	0	0
StayInStableSt	10142749	197119	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	10142749	2678	0	0
gen_low_level_sva.LowLevelEvent_A	10142749	9509518	0	0
gen_not_sticky_sva.StableStDropOut_A	10142749	43	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	161	0	0
T7	624	6	0	0
T8	21518	0	0	0
T10	0	4	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	4	0	0
T38	0	3	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T67	0	2	0	0
T109	0	2	0	0
T136	0	4	0	0
T137	0	4	0	0
T138	0	2	0	0
T144	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	201502	0	0
T7	624	39	0	0
T8	21518	0	0	0
T10	0	70	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	134	0	0
T38	0	65	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T67	0	21385	0	0
T109	0	46	0	0
T136	0	126	0	0
T137	0	100	0	0
T138	0	43	0	0
T144	0	30	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9507014	0	0
T1	24783	24321	0	0
T2	30367	29895	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	4265	0	0
T22	406	5	0	0
T23	535	134	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	2	0	0
T73	91797	0	0	0
T77	304673	1	0	0
T78	0	1	0	0
T80	232657	0	0	0
T145	558	0	0	0
T146	502	0	0	0
T147	26596	0	0	0
T148	502	0	0	0
T149	4402	0	0	0
T150	22571	0	0	0
T151	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	197226	0	0
T7	624	50	0	0
T8	21518	0	0	0
T10	0	165	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	80	0	0
T38	0	172	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T67	0	44	0	0
T109	0	106	0	0
T136	0	294	0	0
T137	0	151	0	0
T138	0	5	0	0
T144	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	75	0	0
T7	624	3	0	0
T8	21518	0	0	0
T10	0	2	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	2	0	0
T38	0	1	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T67	0	1	0	0
T109	0	1	0	0
T136	0	2	0	0
T137	0	2	0	0
T138	0	1	0	0
T144	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	8678334	0	0
T1	24783	24321	0	0
T2	30367	29895	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	4265	0	0
T22	406	5	0	0
T23	535	134	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	8680617	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	84	0	0
T7	624	3	0	0
T8	21518	0	0	0
T10	0	2	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	2	0	0
T38	0	2	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T67	0	1	0	0
T109	0	1	0	0
T136	0	2	0	0
T137	0	2	0	0
T138	0	1	0	0
T144	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	77	0	0
T7	624	3	0	0
T8	21518	0	0	0
T10	0	2	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	2	0	0
T38	0	1	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T67	0	1	0	0
T109	0	1	0	0
T136	0	2	0	0
T137	0	2	0	0
T138	0	1	0	0
T144	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	75	0	0
T7	624	3	0	0
T8	21518	0	0	0
T10	0	2	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	2	0	0
T38	0	1	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T67	0	1	0	0
T109	0	1	0	0
T136	0	2	0	0
T137	0	2	0	0
T138	0	1	0	0
T144	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	75	0	0
T7	624	3	0	0
T8	21518	0	0	0
T10	0	2	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	2	0	0
T38	0	1	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T67	0	1	0	0
T109	0	1	0	0
T136	0	2	0	0
T137	0	2	0	0
T138	0	1	0	0
T144	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	197119	0	0
T7	624	46	0	0
T8	21518	0	0	0
T10	0	162	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	77	0	0
T38	0	171	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T67	0	43	0	0
T109	0	104	0	0
T136	0	292	0	0
T137	0	148	0	0
T138	0	4	0	0
T144	0	38	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	2678	0	0
T1	24783	0	0	0
T2	30367	0	0	0
T3	1108	2	0	0
T6	2902	16	0	0
T7	0	3	0	0
T10	0	14	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	0	4	0	0
T19	0	4	0	0
T20	492	7	0	0
T21	4666	0	0	0
T22	406	0	0	0
T23	535	0	0	0
T29	0	5	0	0
T48	0	2	0	0
T52	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9509518	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	43	0	0
T7	624	2	0	0
T8	21518	0	0	0
T10	0	1	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T67	0	1	0	0
T80	0	1	0	0
T136	0	2	0	0
T137	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0