Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T10,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T7,T10,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T10,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T10,T37
1	0	Covered	T4,T5,T6
1	1	Covered	T7,T10,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T37
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T37
0	1	Covered	T7,T10,T37
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T10,T37
1	-	Covered	T7,T10,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T10,T37
DetectSt	168	Covered	T7,T10,T37
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T7,T10,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T10,T37
DebounceSt->IdleSt	163	Covered	T38,T78,T95
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T7,T10,T37
IdleSt->DebounceSt	148	Covered	T7,T10,T37
StableSt->IdleSt	206	Covered	T7,T10,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T10,T37
0	1	Covered	T7,T10,T37
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T37
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T10,T37
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T10,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T38,T78,T95
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T10,T37
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T7,T10,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T10,T37
StableSt	-	-	-	-	-	-	0	Covered	T7,T10,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10142749	97	0	0
CntIncr_A	10142749	15784	0	0
CntNoWrap_A	10142749	9507078	0	0
DetectStDropOut_A	10142749	0	0	0
DetectedOut_A	10142749	3405	0	0
DetectedPulseOut_A	10142749	44	0	0
DisabledIdleSt_A	10142749	9152183	0	0
DisabledNoDetection_A	10142749	9154462	0	0
EnterDebounceSt_A	10142749	53	0	0
EnterDetectSt_A	10142749	44	0	0
EnterStableSt_A	10142749	44	0	0
PulseIsPulse_A	10142749	44	0	0
StayInStableSt	10142749	3338	0	0
gen_high_level_sva.HighLevelEvent_A	10142749	9509518	0	0
gen_not_sticky_sva.StableStDropOut_A	10142749	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	97	0	0
T7	624	2	0	0
T8	21518	0	0	0
T10	0	2	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T37	0	2	0	0
T38	0	6	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T77	0	2	0	0
T78	0	3	0	0
T80	0	2	0	0
T136	0	2	0	0
T140	0	2	0	0
T152	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	15784	0	0
T7	624	13	0	0
T8	21518	0	0	0
T10	0	35	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T37	0	10	0	0
T38	0	184	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T77	0	96	0	0
T78	0	182	0	0
T80	0	26	0	0
T136	0	95	0	0
T140	0	67	0	0
T152	0	17	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9507078	0	0
T1	24783	24321	0	0
T2	30367	29895	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	4265	0	0
T22	406	5	0	0
T23	535	134	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	3405	0	0
T7	624	81	0	0
T8	21518	0	0	0
T10	0	105	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T37	0	68	0	0
T38	0	125	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T77	0	67	0	0
T78	0	138	0	0
T80	0	167	0	0
T136	0	180	0	0
T140	0	41	0	0
T152	0	45	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	44	0	0
T7	624	1	0	0
T8	21518	0	0	0
T10	0	1	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T37	0	1	0	0
T38	0	2	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T77	0	1	0	0
T78	0	1	0	0
T80	0	1	0	0
T136	0	1	0	0
T140	0	1	0	0
T152	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9152183	0	0
T1	24783	24321	0	0
T2	30367	29895	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	4265	0	0
T22	406	5	0	0
T23	535	134	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9154462	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	53	0	0
T7	624	1	0	0
T8	21518	0	0	0
T10	0	1	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T37	0	1	0	0
T38	0	4	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T77	0	1	0	0
T78	0	2	0	0
T80	0	1	0	0
T136	0	1	0	0
T140	0	1	0	0
T152	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	44	0	0
T7	624	1	0	0
T8	21518	0	0	0
T10	0	1	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T37	0	1	0	0
T38	0	2	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T77	0	1	0	0
T78	0	1	0	0
T80	0	1	0	0
T136	0	1	0	0
T140	0	1	0	0
T152	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	44	0	0
T7	624	1	0	0
T8	21518	0	0	0
T10	0	1	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T37	0	1	0	0
T38	0	2	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T77	0	1	0	0
T78	0	1	0	0
T80	0	1	0	0
T136	0	1	0	0
T140	0	1	0	0
T152	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	44	0	0
T7	624	1	0	0
T8	21518	0	0	0
T10	0	1	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T37	0	1	0	0
T38	0	2	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T77	0	1	0	0
T78	0	1	0	0
T80	0	1	0	0
T136	0	1	0	0
T140	0	1	0	0
T152	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	3338	0	0
T7	624	80	0	0
T8	21518	0	0	0
T10	0	104	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T37	0	67	0	0
T38	0	121	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T77	0	65	0	0
T78	0	137	0	0
T80	0	166	0	0
T136	0	178	0	0
T140	0	39	0	0
T152	0	43	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9509518	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	21	0	0
T7	624	1	0	0
T8	21518	0	0	0
T10	0	1	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T37	0	1	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T78	0	1	0	0
T80	0	1	0	0
T153	0	1	0	0
T154	0	2	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T7,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T7,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T7,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T36
1	0	Covered	T6,T20,T23
1	1	Covered	T3,T7,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T36
0	1	Covered	T158,T159,T160
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T36
0	1	Covered	T7,T38,T67
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T7,T36
1	-	Covered	T7,T38,T67

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T7,T36
DetectSt	168	Covered	T3,T7,T36
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T7,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T7,T36
DebounceSt->IdleSt	163	Covered	T77,T142,T156
DetectSt->IdleSt	186	Covered	T158,T159,T160
DetectSt->StableSt	191	Covered	T3,T7,T36
IdleSt->DebounceSt	148	Covered	T3,T7,T36
StableSt->IdleSt	206	Covered	T7,T56,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T7,T36
0	1	Covered	T3,T7,T36
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T36
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T7,T36
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T7,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T77,T142,T156
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T7,T36
DetectSt	-	-	-	-	1	-	-	Covered	T158,T159,T160
DetectSt	-	-	-	-	0	1	-	Covered	T3,T7,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T38,T67
StableSt	-	-	-	-	-	-	0	Covered	T3,T7,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10142749	157	0	0
CntIncr_A	10142749	123377	0	0
CntNoWrap_A	10142749	9507018	0	0
DetectStDropOut_A	10142749	4	0	0
DetectedOut_A	10142749	207773	0	0
DetectedPulseOut_A	10142749	72	0	0
DisabledIdleSt_A	10142749	9025562	0	0
DisabledNoDetection_A	10142749	9027845	0	0
EnterDebounceSt_A	10142749	81	0	0
EnterDetectSt_A	10142749	76	0	0
EnterStableSt_A	10142749	72	0	0
PulseIsPulse_A	10142749	72	0	0
StayInStableSt	10142749	207667	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	10142749	3006	0	0
gen_low_level_sva.LowLevelEvent_A	10142749	9509518	0	0
gen_not_sticky_sva.StableStDropOut_A	10142749	38	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	157	0	0
T3	1108	2	0	0
T7	624	4	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	2	0	0
T38	0	2	0	0
T40	778	0	0	0
T48	423	0	0	0
T56	0	2	0	0
T67	0	6	0	0
T73	0	2	0	0
T77	0	1	0	0
T136	0	4	0	0
T161	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	123377	0	0
T3	1108	75	0	0
T7	624	26	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	67	0	0
T38	0	13	0	0
T40	778	0	0	0
T48	423	0	0	0
T56	0	83	0	0
T67	0	64155	0	0
T73	0	96	0	0
T77	0	96	0	0
T136	0	126	0	0
T161	0	92	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9507018	0	0
T1	24783	24321	0	0
T2	30367	29895	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	4265	0	0
T22	406	5	0	0
T23	535	134	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	4	0	0
T157	15004	0	0	0
T158	620	1	0	0
T159	0	1	0	0
T160	0	2	0	0
T162	522	0	0	0
T163	522	0	0	0
T164	19963	0	0	0
T165	1835	0	0	0
T166	422	0	0	0
T167	788	0	0	0
T168	1246	0	0	0
T169	5521	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	207773	0	0
T3	1108	39	0	0
T7	624	79	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	38	0	0
T38	0	40	0	0
T40	778	0	0	0
T48	423	0	0	0
T56	0	2	0	0
T67	0	38029	0	0
T73	0	31	0	0
T80	0	117	0	0
T136	0	193	0	0
T161	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	72	0	0
T3	1108	1	0	0
T7	624	2	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T40	778	0	0	0
T48	423	0	0	0
T56	0	1	0	0
T67	0	3	0	0
T73	0	1	0	0
T80	0	2	0	0
T136	0	2	0	0
T161	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9025562	0	0
T1	24783	24321	0	0
T2	30367	29895	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	4265	0	0
T22	406	5	0	0
T23	535	134	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9027845	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	81	0	0
T3	1108	1	0	0
T7	624	2	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T40	778	0	0	0
T48	423	0	0	0
T56	0	1	0	0
T67	0	3	0	0
T73	0	1	0	0
T77	0	1	0	0
T136	0	2	0	0
T161	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	76	0	0
T3	1108	1	0	0
T7	624	2	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T40	778	0	0	0
T48	423	0	0	0
T56	0	1	0	0
T67	0	3	0	0
T73	0	1	0	0
T80	0	2	0	0
T136	0	2	0	0
T161	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	72	0	0
T3	1108	1	0	0
T7	624	2	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T40	778	0	0	0
T48	423	0	0	0
T56	0	1	0	0
T67	0	3	0	0
T73	0	1	0	0
T80	0	2	0	0
T136	0	2	0	0
T161	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	72	0	0
T3	1108	1	0	0
T7	624	2	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T40	778	0	0	0
T48	423	0	0	0
T56	0	1	0	0
T67	0	3	0	0
T73	0	1	0	0
T80	0	2	0	0
T136	0	2	0	0
T161	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	207667	0	0
T3	1108	37	0	0
T7	624	76	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	36	0	0
T38	0	39	0	0
T40	778	0	0	0
T48	423	0	0	0
T67	0	38025	0	0
T73	0	30	0	0
T80	0	114	0	0
T136	0	191	0	0
T140	0	8	0	0
T161	0	39	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	3006	0	0
T1	24783	0	0	0
T2	30367	0	0	0
T3	1108	1	0	0
T6	2902	17	0	0
T7	0	2	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	0	3	0	0
T17	0	5	0	0
T18	0	2	0	0
T19	0	7	0	0
T20	492	5	0	0
T21	4666	0	0	0
T22	406	0	0	0
T23	535	3	0	0
T48	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9509518	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	38	0	0
T7	624	1	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T38	0	1	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T67	0	2	0	0
T73	0	1	0	0
T78	0	1	0	0
T80	0	1	0	0
T136	0	2	0	0
T140	0	1	0	0
T153	0	2	0	0
T170	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T20,T21

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T20,T21
1	1	Covered	T6,T20,T21

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T7,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T7,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T7,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T10
1	0	Covered	T6,T20,T21
1	1	Covered	T3,T7,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T10
0	1	Covered	T39,T77,T171
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T10
0	1	Covered	T7,T10,T36
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T7,T10
1	-	Covered	T7,T10,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T7,T10
DetectSt	168	Covered	T3,T7,T10
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T7,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T7,T10
DebounceSt->IdleSt	163	Covered	T38,T78,T75
DetectSt->IdleSt	186	Covered	T39,T77,T171
DetectSt->StableSt	191	Covered	T3,T7,T10
IdleSt->DebounceSt	148	Covered	T3,T7,T10
StableSt->IdleSt	206	Covered	T7,T10,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T7,T10
0	1	Covered	T3,T7,T10
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T10
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T7,T10
IdleSt	0	-	-	-	-	-	-	Covered	T6,T20,T21
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T7,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T38,T78,T172
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T7,T10
DetectSt	-	-	-	-	1	-	-	Covered	T39,T77,T171
DetectSt	-	-	-	-	0	1	-	Covered	T3,T7,T10
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T10,T36
StableSt	-	-	-	-	-	-	0	Covered	T3,T7,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10142749	147	0	0
CntIncr_A	10142749	201592	0	0
CntNoWrap_A	10142749	9507028	0	0
DetectStDropOut_A	10142749	3	0	0
DetectedOut_A	10142749	16653	0	0
DetectedPulseOut_A	10142749	67	0	0
DisabledIdleSt_A	10142749	8817676	0	0
DisabledNoDetection_A	10142749	8819959	0	0
EnterDebounceSt_A	10142749	77	0	0
EnterDetectSt_A	10142749	70	0	0
EnterStableSt_A	10142749	67	0	0
PulseIsPulse_A	10142749	67	0	0
StayInStableSt	10142749	16554	0	0
gen_high_level_sva.HighLevelEvent_A	10142749	9509518	0	0
gen_not_sticky_sva.StableStDropOut_A	10142749	35	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	147	0	0
T3	1108	2	0	0
T7	624	4	0	0
T8	21518	0	0	0
T10	0	4	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	4	0	0
T37	0	4	0	0
T38	0	7	0	0
T39	0	2	0	0
T40	778	0	0	0
T48	423	0	0	0
T56	0	4	0	0
T137	0	2	0	0
T139	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	201592	0	0
T3	1108	75	0	0
T7	624	26	0	0
T8	21518	0	0	0
T10	0	70	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	134	0	0
T37	0	20	0	0
T38	0	169	0	0
T39	0	44677	0	0
T40	778	0	0	0
T48	423	0	0	0
T56	0	146	0	0
T137	0	50	0	0
T139	0	28	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9507028	0	0
T1	24783	24321	0	0
T2	30367	29895	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	4265	0	0
T22	406	5	0	0
T23	535	134	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	3	0	0
T39	126204	1	0	0
T46	723	0	0	0
T50	736	0	0	0
T51	1319	0	0	0
T56	6875	0	0	0
T70	6994	0	0	0
T77	0	1	0	0
T123	344414	0	0	0
T127	502	0	0	0
T128	615	0	0	0
T171	0	1	0	0
T173	423	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	16653	0	0
T3	1108	497	0	0
T7	624	107	0	0
T8	21518	0	0	0
T10	0	80	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	78	0	0
T37	0	130	0	0
T38	0	134	0	0
T40	778	0	0	0
T48	423	0	0	0
T56	0	333	0	0
T77	0	3769	0	0
T137	0	42	0	0
T139	0	4	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	67	0	0
T3	1108	1	0	0
T7	624	2	0	0
T8	21518	0	0	0
T10	0	2	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	3	0	0
T40	778	0	0	0
T48	423	0	0	0
T56	0	2	0	0
T77	0	1	0	0
T137	0	1	0	0
T139	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	8817676	0	0
T1	24783	24321	0	0
T2	30367	29895	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	4265	0	0
T22	406	5	0	0
T23	535	134	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	8819959	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	77	0	0
T3	1108	1	0	0
T7	624	2	0	0
T8	21518	0	0	0
T10	0	2	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	4	0	0
T39	0	1	0	0
T40	778	0	0	0
T48	423	0	0	0
T56	0	2	0	0
T137	0	1	0	0
T139	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	70	0	0
T3	1108	1	0	0
T7	624	2	0	0
T8	21518	0	0	0
T10	0	2	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	3	0	0
T39	0	1	0	0
T40	778	0	0	0
T48	423	0	0	0
T56	0	2	0	0
T137	0	1	0	0
T139	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	67	0	0
T3	1108	1	0	0
T7	624	2	0	0
T8	21518	0	0	0
T10	0	2	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	3	0	0
T40	778	0	0	0
T48	423	0	0	0
T56	0	2	0	0
T77	0	1	0	0
T137	0	1	0	0
T139	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	67	0	0
T3	1108	1	0	0
T7	624	2	0	0
T8	21518	0	0	0
T10	0	2	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	3	0	0
T40	778	0	0	0
T48	423	0	0	0
T56	0	2	0	0
T77	0	1	0	0
T137	0	1	0	0
T139	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	16554	0	0
T3	1108	495	0	0
T7	624	104	0	0
T8	21518	0	0	0
T10	0	77	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	75	0	0
T37	0	127	0	0
T38	0	130	0	0
T40	778	0	0	0
T48	423	0	0	0
T56	0	329	0	0
T77	0	3768	0	0
T137	0	41	0	0
T139	0	3	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9509518	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	35	0	0
T7	624	1	0	0
T8	21518	0	0	0
T10	0	1	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T77	0	1	0	0
T78	0	3	0	0
T80	0	1	0	0
T137	0	1	0	0
T139	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T20,T21
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T20,T21
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T36,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T7,T36,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T36,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T36
1	0	Covered	T6,T20,T21
1	1	Covered	T7,T36,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T36,T38
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T36,T38
0	1	Covered	T7,T36,T38
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T36,T38
1	-	Covered	T7,T36,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T36,T38
DetectSt	168	Covered	T7,T36,T38
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T7,T36,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T36,T38
DebounceSt->IdleSt	163	Covered	T141,T174,T75
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T7,T36,T38
IdleSt->DebounceSt	148	Covered	T7,T36,T38
StableSt->IdleSt	206	Covered	T7,T36,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T36,T38
0	1	Covered	T7,T36,T38
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T36,T38
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T36,T38
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T36,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T141,T175
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T36,T38
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T7,T36,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T36,T38
StableSt	-	-	-	-	-	-	0	Covered	T7,T36,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10142749	98	0	0
CntIncr_A	10142749	208416	0	0
CntNoWrap_A	10142749	9507077	0	0
DetectStDropOut_A	10142749	0	0	0
DetectedOut_A	10142749	189356	0	0
DetectedPulseOut_A	10142749	47	0	0
DisabledIdleSt_A	10142749	8671116	0	0
DisabledNoDetection_A	10142749	8673396	0	0
EnterDebounceSt_A	10142749	52	0	0
EnterDetectSt_A	10142749	47	0	0
EnterStableSt_A	10142749	47	0	0
PulseIsPulse_A	10142749	47	0	0
StayInStableSt	10142749	189288	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	10142749	6670	0	0
gen_low_level_sva.LowLevelEvent_A	10142749	9509518	0	0
gen_not_sticky_sva.StableStDropOut_A	10142749	26	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	98	0	0
T7	624	2	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	2	0	0
T38	0	4	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T67	0	4	0	0
T77	0	4	0	0
T78	0	6	0	0
T80	0	2	0	0
T136	0	2	0	0
T137	0	2	0	0
T139	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	208416	0	0
T7	624	13	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	67	0	0
T38	0	80	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T67	0	42770	0	0
T77	0	94542	0	0
T78	0	232	0	0
T80	0	26	0	0
T136	0	63	0	0
T137	0	50	0	0
T139	0	28	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9507077	0	0
T1	24783	24321	0	0
T2	30367	29895	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	4265	0	0
T22	406	5	0	0
T23	535	134	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	189356	0	0
T7	624	66	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	48	0	0
T38	0	89	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T67	0	22633	0	0
T77	0	108545	0	0
T78	0	222	0	0
T80	0	166	0	0
T136	0	60	0	0
T137	0	125	0	0
T139	0	38	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	47	0	0
T7	624	1	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	1	0	0
T38	0	2	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T67	0	2	0	0
T77	0	2	0	0
T78	0	3	0	0
T80	0	1	0	0
T136	0	1	0	0
T137	0	1	0	0
T139	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	8671116	0	0
T1	24783	24321	0	0
T2	30367	29895	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	4265	0	0
T22	406	5	0	0
T23	535	134	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	8673396	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	52	0	0
T7	624	1	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	1	0	0
T38	0	2	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T67	0	2	0	0
T77	0	2	0	0
T78	0	3	0	0
T80	0	1	0	0
T136	0	1	0	0
T137	0	1	0	0
T139	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	47	0	0
T7	624	1	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	1	0	0
T38	0	2	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T67	0	2	0	0
T77	0	2	0	0
T78	0	3	0	0
T80	0	1	0	0
T136	0	1	0	0
T137	0	1	0	0
T139	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	47	0	0
T7	624	1	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	1	0	0
T38	0	2	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T67	0	2	0	0
T77	0	2	0	0
T78	0	3	0	0
T80	0	1	0	0
T136	0	1	0	0
T137	0	1	0	0
T139	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	47	0	0
T7	624	1	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	1	0	0
T38	0	2	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T67	0	2	0	0
T77	0	2	0	0
T78	0	3	0	0
T80	0	1	0	0
T136	0	1	0	0
T137	0	1	0	0
T139	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	189288	0	0
T7	624	65	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	47	0	0
T38	0	86	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T67	0	22630	0	0
T77	0	108542	0	0
T78	0	218	0	0
T80	0	164	0	0
T136	0	59	0	0
T137	0	123	0	0
T139	0	36	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	6670	0	0
T1	24783	9	0	0
T2	30367	29	0	0
T3	1108	0	0	0
T6	2902	17	0	0
T7	0	1	0	0
T8	0	9	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	0	5	0	0
T18	0	2	0	0
T19	0	4	0	0
T20	492	8	0	0
T21	4666	28	0	0
T22	406	0	0	0
T23	535	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9509518	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	26	0	0
T7	624	1	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T67	0	1	0	0
T77	0	1	0	0
T78	0	2	0	0
T136	0	1	0	0
T141	0	1	0	0
T170	0	1	0	0
T176	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T20,T21

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T20,T21
1	1	Covered	T6,T20,T21

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T10,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T7,T10,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T10,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T10,T36
1	0	Covered	T6,T20,T21
1	1	Covered	T7,T10,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T36
0	1	Covered	T7,T158
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T36
0	1	Covered	T7,T10,T36
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T10,T36
1	-	Covered	T7,T10,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T10,T36
DetectSt	168	Covered	T7,T10,T36
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T7,T10,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T10,T36
DebounceSt->IdleSt	163	Covered	T38,T161,T95
DetectSt->IdleSt	186	Covered	T7,T158
DetectSt->StableSt	191	Covered	T7,T10,T36
IdleSt->DebounceSt	148	Covered	T7,T10,T36
StableSt->IdleSt	206	Covered	T7,T10,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T10,T36
0	1	Covered	T7,T10,T36
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T36
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T10,T36
IdleSt	0	-	-	-	-	-	-	Covered	T6,T20,T21
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T10,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T38,T161,T95
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T10,T36
DetectSt	-	-	-	-	1	-	-	Covered	T7,T158
DetectSt	-	-	-	-	0	1	-	Covered	T7,T10,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T10,T36
StableSt	-	-	-	-	-	-	0	Covered	T7,T10,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10142749	147	0	0
CntIncr_A	10142749	156453	0	0
CntNoWrap_A	10142749	9507028	0	0
DetectStDropOut_A	10142749	2	0	0
DetectedOut_A	10142749	297231	0	0
DetectedPulseOut_A	10142749	66	0	0
DisabledIdleSt_A	10142749	8992841	0	0
DisabledNoDetection_A	10142749	8995128	0	0
EnterDebounceSt_A	10142749	79	0	0
EnterDetectSt_A	10142749	68	0	0
EnterStableSt_A	10142749	66	0	0
PulseIsPulse_A	10142749	66	0	0
StayInStableSt	10142749	297133	0	0
gen_high_level_sva.HighLevelEvent_A	10142749	9509518	0	0
gen_not_sticky_sva.StableStDropOut_A	10142749	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	147	0	0
T7	624	4	0	0
T8	21518	0	0	0
T10	0	4	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	2	0	0
T38	0	11	0	0
T39	0	2	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T56	0	2	0	0
T109	0	2	0	0
T137	0	2	0	0
T161	0	5	0	0
T177	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	156453	0	0
T7	624	26	0	0
T8	21518	0	0	0
T10	0	70	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	67	0	0
T38	0	210	0	0
T39	0	44677	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T56	0	83	0	0
T109	0	46	0	0
T137	0	50	0	0
T161	0	206	0	0
T177	0	27	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9507028	0	0
T1	24783	24321	0	0
T2	30367	29895	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	4265	0	0
T22	406	5	0	0
T23	535	134	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	2	0	0
T7	624	1	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T158	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	297231	0	0
T7	624	81	0	0
T8	21518	0	0	0
T10	0	185	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	158	0	0
T38	0	290	0	0
T39	0	44716	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T56	0	125	0	0
T109	0	106	0	0
T137	0	26	0	0
T161	0	317	0	0
T177	0	92	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	66	0	0
T7	624	1	0	0
T8	21518	0	0	0
T10	0	2	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	1	0	0
T38	0	5	0	0
T39	0	1	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T56	0	1	0	0
T109	0	1	0	0
T137	0	1	0	0
T161	0	2	0	0
T177	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	8992841	0	0
T1	24783	24321	0	0
T2	30367	29895	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	4265	0	0
T22	406	5	0	0
T23	535	134	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	8995128	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	79	0	0
T7	624	2	0	0
T8	21518	0	0	0
T10	0	2	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	1	0	0
T38	0	6	0	0
T39	0	1	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T56	0	1	0	0
T109	0	1	0	0
T137	0	1	0	0
T161	0	3	0	0
T177	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	68	0	0
T7	624	2	0	0
T8	21518	0	0	0
T10	0	2	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	1	0	0
T38	0	5	0	0
T39	0	1	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T56	0	1	0	0
T109	0	1	0	0
T137	0	1	0	0
T161	0	2	0	0
T177	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	66	0	0
T7	624	1	0	0
T8	21518	0	0	0
T10	0	2	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	1	0	0
T38	0	5	0	0
T39	0	1	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T56	0	1	0	0
T109	0	1	0	0
T137	0	1	0	0
T161	0	2	0	0
T177	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	66	0	0
T7	624	1	0	0
T8	21518	0	0	0
T10	0	2	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	1	0	0
T38	0	5	0	0
T39	0	1	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T56	0	1	0	0
T109	0	1	0	0
T137	0	1	0	0
T161	0	2	0	0
T177	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	297133	0	0
T7	624	80	0	0
T8	21518	0	0	0
T10	0	182	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	157	0	0
T38	0	282	0	0
T39	0	44714	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T56	0	123	0	0
T109	0	104	0	0
T137	0	25	0	0
T161	0	313	0	0
T177	0	90	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9509518	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	34	0	0
T7	624	1	0	0
T8	21518	0	0	0
T10	0	1	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	1	0	0
T38	0	2	0	0
T40	778	0	0	0
T48	423	0	0	0
T52	457	0	0	0
T77	0	1	0	0
T137	0	1	0	0
T140	0	2	0	0
T141	0	1	0	0
T152	0	1	0	0
T170	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T20,T21
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T20,T21
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T7,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T7,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T7,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T36
1	0	Covered	T6,T20,T21
1	1	Covered	T3,T7,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T36
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T36
0	1	Covered	T3,T7,T38
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T7,T36
1	-	Covered	T3,T7,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T7,T36
DetectSt	168	Covered	T3,T7,T36
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T7,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T7,T36
DebounceSt->IdleSt	163	Covered	T78,T75,T178
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T7,T36
IdleSt->DebounceSt	148	Covered	T3,T7,T36
StableSt->IdleSt	206	Covered	T3,T7,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T7,T36
0	1	Covered	T3,T7,T36
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T36
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T7,T36
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T7,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T78,T178
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T7,T36
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T7,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T7,T38
StableSt	-	-	-	-	-	-	0	Covered	T3,T7,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10142749	94	0	0
CntIncr_A	10142749	87829	0	0
CntNoWrap_A	10142749	9507081	0	0
DetectStDropOut_A	10142749	0	0	0
DetectedOut_A	10142749	40396	0	0
DetectedPulseOut_A	10142749	45	0	0
DisabledIdleSt_A	10142749	8837951	0	0
DisabledNoDetection_A	10142749	8840235	0	0
EnterDebounceSt_A	10142749	49	0	0
EnterDetectSt_A	10142749	45	0	0
EnterStableSt_A	10142749	45	0	0
PulseIsPulse_A	10142749	45	0	0
StayInStableSt	10142749	40334	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	10142749	6359	0	0
gen_low_level_sva.LowLevelEvent_A	10142749	9509518	0	0
gen_not_sticky_sva.StableStDropOut_A	10142749	28	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	94	0	0
T3	1108	4	0	0
T7	624	4	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	2	0	0
T38	0	4	0	0
T40	778	0	0	0
T48	423	0	0	0
T66	0	4	0	0
T67	0	2	0	0
T77	0	2	0	0
T136	0	2	0	0
T139	0	4	0	0
T140	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	87829	0	0
T3	1108	150	0	0
T7	624	26	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	67	0	0
T38	0	53	0	0
T40	778	0	0	0
T48	423	0	0	0
T66	0	96	0	0
T67	0	21385	0	0
T77	0	47271	0	0
T136	0	95	0	0
T139	0	56	0	0
T140	0	134	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9507081	0	0
T1	24783	24321	0	0
T2	30367	29895	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	4265	0	0
T22	406	5	0	0
T23	535	134	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	40396	0	0
T3	1108	272	0	0
T7	624	78	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	154	0	0
T38	0	76	0	0
T40	778	0	0	0
T48	423	0	0	0
T66	0	83	0	0
T67	0	33268	0	0
T77	0	3768	0	0
T136	0	196	0	0
T139	0	77	0	0
T140	0	83	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	45	0	0
T3	1108	2	0	0
T7	624	2	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	1	0	0
T38	0	2	0	0
T40	778	0	0	0
T48	423	0	0	0
T66	0	2	0	0
T67	0	1	0	0
T77	0	1	0	0
T136	0	1	0	0
T139	0	2	0	0
T140	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	8837951	0	0
T1	24783	24321	0	0
T2	30367	29895	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	4265	0	0
T22	406	5	0	0
T23	535	134	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	8840235	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	49	0	0
T3	1108	2	0	0
T7	624	2	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	1	0	0
T38	0	2	0	0
T40	778	0	0	0
T48	423	0	0	0
T66	0	2	0	0
T67	0	1	0	0
T77	0	1	0	0
T136	0	1	0	0
T139	0	2	0	0
T140	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	45	0	0
T3	1108	2	0	0
T7	624	2	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	1	0	0
T38	0	2	0	0
T40	778	0	0	0
T48	423	0	0	0
T66	0	2	0	0
T67	0	1	0	0
T77	0	1	0	0
T136	0	1	0	0
T139	0	2	0	0
T140	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	45	0	0
T3	1108	2	0	0
T7	624	2	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	1	0	0
T38	0	2	0	0
T40	778	0	0	0
T48	423	0	0	0
T66	0	2	0	0
T67	0	1	0	0
T77	0	1	0	0
T136	0	1	0	0
T139	0	2	0	0
T140	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	45	0	0
T3	1108	2	0	0
T7	624	2	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	1	0	0
T38	0	2	0	0
T40	778	0	0	0
T48	423	0	0	0
T66	0	2	0	0
T67	0	1	0	0
T77	0	1	0	0
T136	0	1	0	0
T139	0	2	0	0
T140	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	40334	0	0
T3	1108	269	0	0
T7	624	75	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	152	0	0
T38	0	74	0	0
T40	778	0	0	0
T48	423	0	0	0
T66	0	80	0	0
T67	0	33267	0	0
T77	0	3767	0	0
T136	0	195	0	0
T139	0	74	0	0
T140	0	81	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	6359	0	0
T1	24783	9	0	0
T2	30367	22	0	0
T3	1108	2	0	0
T6	2902	19	0	0
T7	0	2	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	0	5	0	0
T18	0	2	0	0
T19	0	4	0	0
T20	492	6	0	0
T21	4666	23	0	0
T22	406	0	0	0
T23	535	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9509518	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	28	0	0
T3	1108	1	0	0
T7	624	1	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T38	0	2	0	0
T40	778	0	0	0
T48	423	0	0	0
T66	0	1	0	0
T67	0	1	0	0
T77	0	1	0	0
T78	0	3	0	0
T136	0	1	0	0
T139	0	1	0	0
T140	0	2	0	0