Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T20,T21

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T20,T21
1	1	Covered	T6,T20,T21

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T36,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T36,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T36,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T36,T38
1	0	Covered	T6,T20,T21
1	1	Covered	T3,T36,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T36,T38
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T36,T38
0	1	Covered	T3,T36,T38
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T36,T38
1	-	Covered	T3,T36,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T36,T38
DetectSt	168	Covered	T3,T36,T38
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T36,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T36,T38
DebounceSt->IdleSt	163	Covered	T179,T75,T180
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T36,T38
IdleSt->DebounceSt	148	Covered	T3,T36,T38
StableSt->IdleSt	206	Covered	T3,T36,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T36,T38
0	1	Covered	T3,T36,T38
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T36,T38
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T36,T38
IdleSt	0	-	-	-	-	-	-	Covered	T6,T20,T21
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T36,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T179,T180,T126
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T36,T38
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T36,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T36,T38
StableSt	-	-	-	-	-	-	0	Covered	T3,T36,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10142749	144	0	0
CntIncr_A	10142749	106660	0	0
CntNoWrap_A	10142749	9507031	0	0
DetectStDropOut_A	10142749	0	0	0
DetectedOut_A	10142749	97462	0	0
DetectedPulseOut_A	10142749	69	0	0
DisabledIdleSt_A	10142749	8902276	0	0
DisabledNoDetection_A	10142749	8904560	0	0
EnterDebounceSt_A	10142749	75	0	0
EnterDetectSt_A	10142749	69	0	0
EnterStableSt_A	10142749	69	0	0
PulseIsPulse_A	10142749	69	0	0
StayInStableSt	10142749	97363	0	0
gen_high_level_sva.HighLevelEvent_A	10142749	9509518	0	0
gen_not_sticky_sva.StableStDropOut_A	10142749	39	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	144	0	0
T3	1108	4	0	0
T7	624	0	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	2	0	0
T38	0	4	0	0
T40	778	0	0	0
T48	423	0	0	0
T77	0	2	0	0
T80	0	4	0	0
T109	0	2	0	0
T136	0	4	0	0
T137	0	2	0	0
T161	0	2	0	0
T179	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	106660	0	0
T3	1108	150	0	0
T7	624	0	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	67	0	0
T38	0	104	0	0
T40	778	0	0	0
T48	423	0	0	0
T77	0	47271	0	0
T80	0	170	0	0
T109	0	46	0	0
T136	0	126	0	0
T137	0	50	0	0
T161	0	27	0	0
T179	0	92	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9507031	0	0
T1	24783	24321	0	0
T2	30367	29895	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	4265	0	0
T22	406	5	0	0
T23	535	134	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	97462	0	0
T3	1108	349	0	0
T7	624	0	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	272	0	0
T38	0	162	0	0
T40	778	0	0	0
T48	423	0	0	0
T77	0	47311	0	0
T80	0	243	0	0
T109	0	39	0	0
T136	0	400	0	0
T137	0	297	0	0
T152	0	62	0	0
T161	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	69	0	0
T3	1108	2	0	0
T7	624	0	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	1	0	0
T38	0	2	0	0
T40	778	0	0	0
T48	423	0	0	0
T77	0	1	0	0
T80	0	2	0	0
T109	0	1	0	0
T136	0	2	0	0
T137	0	1	0	0
T152	0	1	0	0
T161	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	8902276	0	0
T1	24783	24321	0	0
T2	30367	29895	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	4265	0	0
T22	406	5	0	0
T23	535	134	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	8904560	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	75	0	0
T3	1108	2	0	0
T7	624	0	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	1	0	0
T38	0	2	0	0
T40	778	0	0	0
T48	423	0	0	0
T77	0	1	0	0
T80	0	2	0	0
T109	0	1	0	0
T136	0	2	0	0
T137	0	1	0	0
T161	0	1	0	0
T179	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	69	0	0
T3	1108	2	0	0
T7	624	0	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	1	0	0
T38	0	2	0	0
T40	778	0	0	0
T48	423	0	0	0
T77	0	1	0	0
T80	0	2	0	0
T109	0	1	0	0
T136	0	2	0	0
T137	0	1	0	0
T152	0	1	0	0
T161	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	69	0	0
T3	1108	2	0	0
T7	624	0	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	1	0	0
T38	0	2	0	0
T40	778	0	0	0
T48	423	0	0	0
T77	0	1	0	0
T80	0	2	0	0
T109	0	1	0	0
T136	0	2	0	0
T137	0	1	0	0
T152	0	1	0	0
T161	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	69	0	0
T3	1108	2	0	0
T7	624	0	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	1	0	0
T38	0	2	0	0
T40	778	0	0	0
T48	423	0	0	0
T77	0	1	0	0
T80	0	2	0	0
T109	0	1	0	0
T136	0	2	0	0
T137	0	1	0	0
T152	0	1	0	0
T161	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	97363	0	0
T3	1108	346	0	0
T7	624	0	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	271	0	0
T38	0	160	0	0
T40	778	0	0	0
T48	423	0	0	0
T77	0	47310	0	0
T80	0	240	0	0
T109	0	37	0	0
T136	0	397	0	0
T137	0	295	0	0
T152	0	60	0	0
T161	0	37	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9509518	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	39	0	0
T3	1108	1	0	0
T7	624	0	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	1	0	0
T38	0	2	0	0
T40	778	0	0	0
T48	423	0	0	0
T77	0	1	0	0
T78	0	1	0	0
T80	0	1	0	0
T136	0	1	0	0
T153	0	2	0	0
T170	0	2	0	0
T176	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T20,T21
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T20,T21
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T36,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T36,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T37,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T36,T37
1	0	Covered	T6,T20,T21
1	1	Covered	T3,T36,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T36,T37,T39
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T36,T37,T39
0	1	Covered	T37,T56,T38
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T36,T37,T39
1	-	Covered	T37,T56,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T36,T37
DetectSt	168	Covered	T36,T37,T39
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T36,T37,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T36,T37,T39
DebounceSt->IdleSt	163	Covered	T3,T75,T76
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T36,T37,T39
IdleSt->DebounceSt	148	Covered	T3,T36,T37
StableSt->IdleSt	206	Covered	T37,T39,T56

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T36,T37
0	1	Covered	T3,T36,T37
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T36,T37,T39
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T36,T37
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T36,T37,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T3
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T36,T37
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T36,T37,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T37,T56,T38
StableSt	-	-	-	-	-	-	0	Covered	T36,T37,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10142749	125	0	0
CntIncr_A	10142749	126264	0	0
CntNoWrap_A	10142749	9507050	0	0
DetectStDropOut_A	10142749	0	0	0
DetectedOut_A	10142749	241761	0	0
DetectedPulseOut_A	10142749	61	0	0
DisabledIdleSt_A	10142749	8915664	0	0
DisabledNoDetection_A	10142749	8917937	0	0
EnterDebounceSt_A	10142749	64	0	0
EnterDetectSt_A	10142749	61	0	0
EnterStableSt_A	10142749	61	0	0
PulseIsPulse_A	10142749	61	0	0
StayInStableSt	10142749	241665	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	10142749	6373	0	0
gen_low_level_sva.LowLevelEvent_A	10142749	9509518	0	0
gen_not_sticky_sva.StableStDropOut_A	10142749	26	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	125	0	0
T3	1108	1	0	0
T7	624	0	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	6	0	0
T39	0	2	0	0
T40	778	0	0	0
T48	423	0	0	0
T56	0	2	0	0
T67	0	2	0	0
T77	0	2	0	0
T139	0	2	0	0
T161	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	126264	0	0
T3	1108	75	0	0
T7	624	0	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	67	0	0
T37	0	10	0	0
T38	0	117	0	0
T39	0	44677	0	0
T40	778	0	0	0
T48	423	0	0	0
T56	0	83	0	0
T67	0	21385	0	0
T77	0	47271	0	0
T139	0	28	0	0
T161	0	92	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9507050	0	0
T1	24783	24321	0	0
T2	30367	29895	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	4265	0	0
T22	406	5	0	0
T23	535	134	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	241761	0	0
T36	856	39	0	0
T37	0	57	0	0
T38	0	194	0	0
T39	0	37	0	0
T43	599	0	0	0
T44	30678	0	0	0
T56	0	40	0	0
T61	523	0	0	0
T62	1947	0	0	0
T63	522	0	0	0
T67	0	77244	0	0
T77	0	159547	0	0
T80	0	102	0	0
T82	11358	0	0	0
T133	416	0	0	0
T134	630	0	0	0
T139	0	39	0	0
T161	0	41	0	0
T181	431	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	61	0	0
T36	856	1	0	0
T37	0	1	0	0
T38	0	3	0	0
T39	0	1	0	0
T43	599	0	0	0
T44	30678	0	0	0
T56	0	1	0	0
T61	523	0	0	0
T62	1947	0	0	0
T63	522	0	0	0
T67	0	1	0	0
T77	0	1	0	0
T80	0	2	0	0
T82	11358	0	0	0
T133	416	0	0	0
T134	630	0	0	0
T139	0	1	0	0
T161	0	1	0	0
T181	431	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	8915664	0	0
T1	24783	24321	0	0
T2	30367	29895	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	4265	0	0
T22	406	5	0	0
T23	535	134	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	8917937	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	64	0	0
T3	1108	1	0	0
T7	624	0	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	3	0	0
T39	0	1	0	0
T40	778	0	0	0
T48	423	0	0	0
T56	0	1	0	0
T67	0	1	0	0
T77	0	1	0	0
T139	0	1	0	0
T161	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	61	0	0
T36	856	1	0	0
T37	0	1	0	0
T38	0	3	0	0
T39	0	1	0	0
T43	599	0	0	0
T44	30678	0	0	0
T56	0	1	0	0
T61	523	0	0	0
T62	1947	0	0	0
T63	522	0	0	0
T67	0	1	0	0
T77	0	1	0	0
T80	0	2	0	0
T82	11358	0	0	0
T133	416	0	0	0
T134	630	0	0	0
T139	0	1	0	0
T161	0	1	0	0
T181	431	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	61	0	0
T36	856	1	0	0
T37	0	1	0	0
T38	0	3	0	0
T39	0	1	0	0
T43	599	0	0	0
T44	30678	0	0	0
T56	0	1	0	0
T61	523	0	0	0
T62	1947	0	0	0
T63	522	0	0	0
T67	0	1	0	0
T77	0	1	0	0
T80	0	2	0	0
T82	11358	0	0	0
T133	416	0	0	0
T134	630	0	0	0
T139	0	1	0	0
T161	0	1	0	0
T181	431	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	61	0	0
T36	856	1	0	0
T37	0	1	0	0
T38	0	3	0	0
T39	0	1	0	0
T43	599	0	0	0
T44	30678	0	0	0
T56	0	1	0	0
T61	523	0	0	0
T62	1947	0	0	0
T63	522	0	0	0
T67	0	1	0	0
T77	0	1	0	0
T80	0	2	0	0
T82	11358	0	0	0
T133	416	0	0	0
T134	630	0	0	0
T139	0	1	0	0
T161	0	1	0	0
T181	431	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	241665	0	0
T36	856	37	0	0
T37	0	56	0	0
T38	0	189	0	0
T39	0	35	0	0
T43	599	0	0	0
T44	30678	0	0	0
T56	0	39	0	0
T61	523	0	0	0
T62	1947	0	0	0
T63	522	0	0	0
T67	0	77243	0	0
T77	0	159545	0	0
T80	0	99	0	0
T82	11358	0	0	0
T133	416	0	0	0
T134	630	0	0	0
T139	0	37	0	0
T161	0	39	0	0
T181	431	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	6373	0	0
T1	24783	8	0	0
T2	30367	24	0	0
T3	1108	1	0	0
T6	2902	14	0	0
T7	0	1	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	0	3	0	0
T18	0	1	0	0
T19	0	3	0	0
T20	492	7	0	0
T21	4666	33	0	0
T22	406	0	0	0
T23	535	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9509518	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	26	0	0
T37	2838	1	0	0
T38	0	1	0	0
T39	126204	0	0	0
T50	736	0	0	0
T51	1319	0	0	0
T56	0	1	0	0
T67	0	1	0	0
T70	6994	0	0	0
T78	0	1	0	0
T80	0	1	0	0
T122	405	0	0	0
T123	344414	0	0	0
T127	502	0	0	0
T128	615	0	0	0
T131	0	1	0	0
T140	0	1	0	0
T154	0	1	0	0
T173	423	0	0	0
T182	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T20,T21

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T20,T21
1	1	Covered	T6,T20,T21

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T7,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T7,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T7,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T10
1	0	Covered	T6,T20,T21
1	1	Covered	T3,T7,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T10
0	1	Covered	T38,T183,T171
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T10
0	1	Covered	T3,T7,T10
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T7,T10
1	-	Covered	T3,T7,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T7,T10
DetectSt	168	Covered	T3,T7,T10
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T7,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T7,T10
DebounceSt->IdleSt	163	Covered	T3,T56,T136
DetectSt->IdleSt	186	Covered	T38,T183,T171
DetectSt->StableSt	191	Covered	T3,T7,T10
IdleSt->DebounceSt	148	Covered	T3,T7,T10
StableSt->IdleSt	206	Covered	T3,T7,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T7,T10
0	1	Covered	T3,T7,T10
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T10
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T7,T10
IdleSt	0	-	-	-	-	-	-	Covered	T6,T20,T21
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T7,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T56,T136
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T7,T10
DetectSt	-	-	-	-	1	-	-	Covered	T38,T183,T171
DetectSt	-	-	-	-	0	1	-	Covered	T3,T7,T10
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T7,T10
StableSt	-	-	-	-	-	-	0	Covered	T3,T7,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10142749	162	0	0
CntIncr_A	10142749	88950	0	0
CntNoWrap_A	10142749	9507013	0	0
DetectStDropOut_A	10142749	4	0	0
DetectedOut_A	10142749	50340	0	0
DetectedPulseOut_A	10142749	71	0	0
DisabledIdleSt_A	10142749	9128188	0	0
DisabledNoDetection_A	10142749	9130466	0	0
EnterDebounceSt_A	10142749	87	0	0
EnterDetectSt_A	10142749	75	0	0
EnterStableSt_A	10142749	71	0	0
PulseIsPulse_A	10142749	71	0	0
StayInStableSt	10142749	50242	0	0
gen_high_level_sva.HighLevelEvent_A	10142749	9509518	0	0
gen_not_sticky_sva.StableStDropOut_A	10142749	44	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	162	0	0
T3	1108	3	0	0
T7	624	4	0	0
T8	21518	0	0	0
T10	0	4	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T38	0	8	0	0
T40	778	0	0	0
T48	423	0	0	0
T56	0	3	0	0
T67	0	4	0	0
T109	0	2	0	0
T136	0	7	0	0
T161	0	2	0	0
T177	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	88950	0	0
T3	1108	150	0	0
T7	624	26	0	0
T8	21518	0	0	0
T10	0	70	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T38	0	145	0	0
T40	778	0	0	0
T48	423	0	0	0
T56	0	146	0	0
T67	0	42770	0	0
T109	0	46	0	0
T136	0	316	0	0
T161	0	92	0	0
T177	0	27	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9507013	0	0
T1	24783	24321	0	0
T2	30367	29895	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	4265	0	0
T22	406	5	0	0
T23	535	134	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	4	0	0
T38	28026	1	0	0
T58	490	0	0	0
T124	0	1	0	0
T171	0	1	0	0
T183	0	1	0	0
T184	526	0	0	0
T185	406	0	0	0
T186	592	0	0	0
T187	422	0	0	0
T188	527	0	0	0
T189	529	0	0	0
T190	406	0	0	0
T191	491	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	50340	0	0
T3	1108	192	0	0
T7	624	97	0	0
T8	21518	0	0	0
T10	0	47	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T38	0	275	0	0
T40	778	0	0	0
T48	423	0	0	0
T56	0	205	0	0
T67	0	1206	0	0
T109	0	105	0	0
T136	0	336	0	0
T161	0	63	0	0
T177	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	71	0	0
T3	1108	1	0	0
T7	624	2	0	0
T8	21518	0	0	0
T10	0	2	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T38	0	3	0	0
T40	778	0	0	0
T48	423	0	0	0
T56	0	1	0	0
T67	0	2	0	0
T109	0	1	0	0
T136	0	3	0	0
T161	0	1	0	0
T177	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9128188	0	0
T1	24783	24321	0	0
T2	30367	29895	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	4265	0	0
T22	406	5	0	0
T23	535	134	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9130466	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	87	0	0
T3	1108	2	0	0
T7	624	2	0	0
T8	21518	0	0	0
T10	0	2	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T38	0	4	0	0
T40	778	0	0	0
T48	423	0	0	0
T56	0	2	0	0
T67	0	2	0	0
T109	0	1	0	0
T136	0	4	0	0
T161	0	1	0	0
T177	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	75	0	0
T3	1108	1	0	0
T7	624	2	0	0
T8	21518	0	0	0
T10	0	2	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T38	0	4	0	0
T40	778	0	0	0
T48	423	0	0	0
T56	0	1	0	0
T67	0	2	0	0
T109	0	1	0	0
T136	0	3	0	0
T161	0	1	0	0
T177	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	71	0	0
T3	1108	1	0	0
T7	624	2	0	0
T8	21518	0	0	0
T10	0	2	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T38	0	3	0	0
T40	778	0	0	0
T48	423	0	0	0
T56	0	1	0	0
T67	0	2	0	0
T109	0	1	0	0
T136	0	3	0	0
T161	0	1	0	0
T177	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	71	0	0
T3	1108	1	0	0
T7	624	2	0	0
T8	21518	0	0	0
T10	0	2	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T38	0	3	0	0
T40	778	0	0	0
T48	423	0	0	0
T56	0	1	0	0
T67	0	2	0	0
T109	0	1	0	0
T136	0	3	0	0
T161	0	1	0	0
T177	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	50242	0	0
T3	1108	191	0	0
T7	624	95	0	0
T8	21518	0	0	0
T10	0	45	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T38	0	270	0	0
T40	778	0	0	0
T48	423	0	0	0
T56	0	204	0	0
T67	0	1204	0	0
T109	0	103	0	0
T136	0	332	0	0
T161	0	62	0	0
T177	0	41	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9509518	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	44	0	0
T3	1108	1	0	0
T7	624	2	0	0
T8	21518	0	0	0
T10	0	2	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T38	0	1	0	0
T40	778	0	0	0
T48	423	0	0	0
T56	0	1	0	0
T67	0	2	0	0
T80	0	2	0	0
T136	0	2	0	0
T139	0	1	0	0
T161	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T20,T21
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T20,T21
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T10,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T10,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T10,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T39
1	0	Covered	T6,T20,T21
1	1	Covered	T3,T10,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T39
0	1	Covered	T160
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T39
0	1	Covered	T3,T10,T77
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T10,T39
1	-	Covered	T3,T10,T77

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T10,T39
DetectSt	168	Covered	T3,T10,T39
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T10,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T10,T39
DebounceSt->IdleSt	163	Covered	T78,T141,T75
DetectSt->IdleSt	186	Covered	T160
DetectSt->StableSt	191	Covered	T3,T10,T39
IdleSt->DebounceSt	148	Covered	T3,T10,T39
StableSt->IdleSt	206	Covered	T3,T10,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T10,T39
0	1	Covered	T3,T10,T39
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T39
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T10,T39
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T10,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T78,T141,T192
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T10,T39
DetectSt	-	-	-	-	1	-	-	Covered	T160
DetectSt	-	-	-	-	0	1	-	Covered	T3,T10,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T10,T77
StableSt	-	-	-	-	-	-	0	Covered	T3,T10,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10142749	108	0	0
CntIncr_A	10142749	142168	0	0
CntNoWrap_A	10142749	9507067	0	0
DetectStDropOut_A	10142749	1	0	0
DetectedOut_A	10142749	102425	0	0
DetectedPulseOut_A	10142749	51	0	0
DisabledIdleSt_A	10142749	9024628	0	0
DisabledNoDetection_A	10142749	9026911	0	0
EnterDebounceSt_A	10142749	57	0	0
EnterDetectSt_A	10142749	52	0	0
EnterStableSt_A	10142749	50	0	0
PulseIsPulse_A	10142749	50	0	0
StayInStableSt	10142749	102346	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	10142749	6469	0	0
gen_low_level_sva.LowLevelEvent_A	10142749	9509518	0	0
gen_not_sticky_sva.StableStDropOut_A	10142749	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	108	0	0
T3	1108	4	0	0
T7	624	0	0	0
T8	21518	0	0	0
T10	0	4	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T39	0	2	0	0
T40	778	0	0	0
T48	423	0	0	0
T56	0	1	0	0
T77	0	4	0	0
T80	0	4	0	0
T137	0	2	0	0
T138	0	2	0	0
T152	0	2	0	0
T193	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	142168	0	0
T3	1108	150	0	0
T7	624	0	0	0
T8	21518	0	0	0
T10	0	70	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T39	0	44677	0	0
T40	778	0	0	0
T48	423	0	0	0
T56	0	83	0	0
T77	0	94542	0	0
T80	0	111	0	0
T137	0	50	0	0
T138	0	43	0	0
T152	0	17	0	0
T193	0	40	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9507067	0	0
T1	24783	24321	0	0
T2	30367	29895	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	4265	0	0
T22	406	5	0	0
T23	535	134	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	1	0	0
T76	7657	0	0	0
T126	6438	0	0	0
T160	794	1	0	0
T192	35027	0	0	0
T194	441	0	0	0
T195	782	0	0	0
T196	507	0	0	0
T197	422	0	0	0
T198	762	0	0	0
T199	6167	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	102425	0	0
T3	1108	83	0	0
T7	624	0	0	0
T8	21518	0	0	0
T10	0	150	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T39	0	38	0	0
T40	778	0	0	0
T48	423	0	0	0
T56	0	1	0	0
T77	0	98451	0	0
T80	0	237	0	0
T137	0	40	0	0
T138	0	44	0	0
T152	0	45	0	0
T193	0	44	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	51	0	0
T3	1108	2	0	0
T7	624	0	0	0
T8	21518	0	0	0
T10	0	2	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T39	0	1	0	0
T40	778	0	0	0
T48	423	0	0	0
T56	0	1	0	0
T77	0	2	0	0
T80	0	2	0	0
T137	0	1	0	0
T138	0	1	0	0
T152	0	1	0	0
T193	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9024628	0	0
T1	24783	24321	0	0
T2	30367	29895	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	4265	0	0
T22	406	5	0	0
T23	535	134	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9026911	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	57	0	0
T3	1108	2	0	0
T7	624	0	0	0
T8	21518	0	0	0
T10	0	2	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T39	0	1	0	0
T40	778	0	0	0
T48	423	0	0	0
T56	0	1	0	0
T77	0	2	0	0
T80	0	2	0	0
T137	0	1	0	0
T138	0	1	0	0
T152	0	1	0	0
T193	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	52	0	0
T3	1108	2	0	0
T7	624	0	0	0
T8	21518	0	0	0
T10	0	2	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T39	0	1	0	0
T40	778	0	0	0
T48	423	0	0	0
T56	0	1	0	0
T77	0	2	0	0
T80	0	2	0	0
T137	0	1	0	0
T138	0	1	0	0
T152	0	1	0	0
T193	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	50	0	0
T3	1108	2	0	0
T7	624	0	0	0
T8	21518	0	0	0
T10	0	2	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T39	0	1	0	0
T40	778	0	0	0
T48	423	0	0	0
T77	0	2	0	0
T78	0	2	0	0
T80	0	2	0	0
T137	0	1	0	0
T138	0	1	0	0
T152	0	1	0	0
T193	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	50	0	0
T3	1108	2	0	0
T7	624	0	0	0
T8	21518	0	0	0
T10	0	2	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T39	0	1	0	0
T40	778	0	0	0
T48	423	0	0	0
T77	0	2	0	0
T78	0	2	0	0
T80	0	2	0	0
T137	0	1	0	0
T138	0	1	0	0
T152	0	1	0	0
T193	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	102346	0	0
T3	1108	80	0	0
T7	624	0	0	0
T8	21518	0	0	0
T10	0	147	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T39	0	36	0	0
T40	778	0	0	0
T48	423	0	0	0
T77	0	98448	0	0
T78	0	620	0	0
T80	0	234	0	0
T137	0	38	0	0
T138	0	42	0	0
T152	0	43	0	0
T193	0	42	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	6469	0	0
T1	24783	13	0	0
T2	30367	28	0	0
T3	1108	2	0	0
T6	2902	12	0	0
T7	0	2	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	0	4	0	0
T18	0	2	0	0
T19	0	4	0	0
T20	492	8	0	0
T21	4666	29	0	0
T22	406	0	0	0
T23	535	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9509518	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	22	0	0
T3	1108	1	0	0
T7	624	0	0	0
T8	21518	0	0	0
T10	0	1	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T40	778	0	0	0
T48	423	0	0	0
T77	0	1	0	0
T78	0	1	0	0
T80	0	1	0	0
T131	0	1	0	0
T154	0	1	0	0
T182	0	1	0	0
T183	0	2	0	0
T200	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T36,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T36,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T36,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T36,T39
1	0	Covered	T4,T5,T6
1	1	Covered	T3,T36,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T36,T39
0	1	Covered	T38,T152,T182
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T36,T39
0	1	Covered	T3,T36,T56
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T36,T39
1	-	Covered	T3,T36,T56

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T36,T39
DetectSt	168	Covered	T3,T36,T39
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T36,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T36,T39
DebounceSt->IdleSt	163	Covered	T201,T75,T76
DetectSt->IdleSt	186	Covered	T38,T152,T182
DetectSt->StableSt	191	Covered	T3,T36,T39
IdleSt->DebounceSt	148	Covered	T3,T36,T39
StableSt->IdleSt	206	Covered	T3,T36,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T36,T39
0	1	Covered	T3,T36,T39
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T36,T39
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T36,T39
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T36,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T201
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T36,T39
DetectSt	-	-	-	-	1	-	-	Covered	T38,T152,T182
DetectSt	-	-	-	-	0	1	-	Covered	T3,T36,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T36,T56
StableSt	-	-	-	-	-	-	0	Covered	T3,T36,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10142749	167	0	0
CntIncr_A	10142749	282784	0	0
CntNoWrap_A	10142749	9507008	0	0
DetectStDropOut_A	10142749	3	0	0
DetectedOut_A	10142749	201505	0	0
DetectedPulseOut_A	10142749	79	0	0
DisabledIdleSt_A	10142749	8639656	0	0
DisabledNoDetection_A	10142749	8641935	0	0
EnterDebounceSt_A	10142749	85	0	0
EnterDetectSt_A	10142749	82	0	0
EnterStableSt_A	10142749	79	0	0
PulseIsPulse_A	10142749	79	0	0
StayInStableSt	10142749	201390	0	0
gen_high_level_sva.HighLevelEvent_A	10142749	9509518	0	0
gen_not_sticky_sva.StableStDropOut_A	10142749	43	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	167	0	0
T3	1108	6	0	0
T7	624	0	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	4	0	0
T38	0	4	0	0
T39	0	2	0	0
T40	778	0	0	0
T48	423	0	0	0
T56	0	4	0	0
T66	0	2	0	0
T137	0	4	0	0
T138	0	2	0	0
T144	0	2	0	0
T161	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	282784	0	0
T3	1108	225	0	0
T7	624	0	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	134	0	0
T38	0	92	0	0
T39	0	44677	0	0
T40	778	0	0	0
T48	423	0	0	0
T56	0	146	0	0
T66	0	48	0	0
T137	0	100	0	0
T138	0	43	0	0
T144	0	30	0	0
T161	0	92	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9507008	0	0
T1	24783	24321	0	0
T2	30367	29895	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	4265	0	0
T22	406	5	0	0
T23	535	134	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	3	0	0
T38	28026	1	0	0
T58	490	0	0	0
T152	0	1	0	0
T182	0	1	0	0
T184	526	0	0	0
T185	406	0	0	0
T186	592	0	0	0
T187	422	0	0	0
T188	527	0	0	0
T189	529	0	0	0
T190	406	0	0	0
T191	491	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	201505	0	0
T3	1108	124	0	0
T7	624	0	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	195	0	0
T38	0	79	0	0
T39	0	44716	0	0
T40	778	0	0	0
T48	423	0	0	0
T56	0	147	0	0
T66	0	92	0	0
T137	0	152	0	0
T138	0	5	0	0
T144	0	39	0	0
T161	0	320	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	79	0	0
T3	1108	3	0	0
T7	624	0	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	778	0	0	0
T48	423	0	0	0
T56	0	2	0	0
T66	0	1	0	0
T137	0	2	0	0
T138	0	1	0	0
T144	0	1	0	0
T161	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	8639656	0	0
T1	24783	24321	0	0
T2	30367	29895	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	4265	0	0
T22	406	5	0	0
T23	535	134	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	8641935	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	85	0	0
T3	1108	3	0	0
T7	624	0	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	2	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	778	0	0	0
T48	423	0	0	0
T56	0	2	0	0
T66	0	1	0	0
T137	0	2	0	0
T138	0	1	0	0
T144	0	1	0	0
T161	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	82	0	0
T3	1108	3	0	0
T7	624	0	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	2	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	778	0	0	0
T48	423	0	0	0
T56	0	2	0	0
T66	0	1	0	0
T137	0	2	0	0
T138	0	1	0	0
T144	0	1	0	0
T161	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	79	0	0
T3	1108	3	0	0
T7	624	0	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	778	0	0	0
T48	423	0	0	0
T56	0	2	0	0
T66	0	1	0	0
T137	0	2	0	0
T138	0	1	0	0
T144	0	1	0	0
T161	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	79	0	0
T3	1108	3	0	0
T7	624	0	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	778	0	0	0
T48	423	0	0	0
T56	0	2	0	0
T66	0	1	0	0
T137	0	2	0	0
T138	0	1	0	0
T144	0	1	0	0
T161	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	201390	0	0
T3	1108	120	0	0
T7	624	0	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	192	0	0
T38	0	78	0	0
T39	0	44714	0	0
T40	778	0	0	0
T48	423	0	0	0
T56	0	144	0	0
T66	0	90	0	0
T137	0	149	0	0
T138	0	4	0	0
T144	0	37	0	0
T161	0	318	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9509518	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	43	0	0
T3	1108	2	0	0
T7	624	0	0	0
T8	21518	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T33	975	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T40	778	0	0	0
T48	423	0	0	0
T56	0	1	0	0
T73	0	1	0	0
T77	0	1	0	0
T80	0	3	0	0
T137	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T37,T56

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T36,T37,T56

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T37,T56

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T36,T37
1	0	Covered	T4,T5,T6
1	1	Covered	T36,T37,T56

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T36,T37,T56
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T36,T37,T56
0	1	Covered	T36,T137,T139
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T36,T37,T56
1	-	Covered	T36,T137,T139

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T36,T37,T56
DetectSt	168	Covered	T36,T37,T56
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T36,T37,T56

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T36,T37,T56
DebounceSt->IdleSt	163	Covered	T78,T141,T75
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T36,T37,T56
IdleSt->DebounceSt	148	Covered	T36,T37,T56
StableSt->IdleSt	206	Covered	T36,T37,T56

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T36,T37,T56
0	1	Covered	T36,T37,T56
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T36,T37,T56
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T36,T37,T56
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T36,T37,T56
DebounceSt	-	0	1	0	-	-	-	Covered	T78,T141
DebounceSt	-	0	0	-	-	-	-	Covered	T36,T37,T56
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T36,T37,T56
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T36,T137,T139
StableSt	-	-	-	-	-	-	0	Covered	T36,T37,T56
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10142749	99	0	0
CntIncr_A	10142749	107431	0	0
CntNoWrap_A	10142749	9507076	0	0
DetectStDropOut_A	10142749	0	0	0
DetectedOut_A	10142749	151486	0	0
DetectedPulseOut_A	10142749	48	0	0
DisabledIdleSt_A	10142749	8659519	0	0
DisabledNoDetection_A	10142749	8661790	0	0
EnterDebounceSt_A	10142749	52	0	0
EnterDetectSt_A	10142749	48	0	0
EnterStableSt_A	10142749	47	0	0
PulseIsPulse_A	10142749	47	0	0
StayInStableSt	10142749	151413	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	10142749	7002	0	0
gen_low_level_sva.LowLevelEvent_A	10142749	9509518	0	0
gen_not_sticky_sva.StableStDropOut_A	10142749	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	99	0	0
T36	856	2	0	0
T37	0	2	0	0
T38	0	4	0	0
T43	599	0	0	0
T44	30678	0	0	0
T56	0	1	0	0
T61	523	0	0	0
T62	1947	0	0	0
T63	522	0	0	0
T73	0	2	0	0
T77	0	2	0	0
T80	0	6	0	0
T82	11358	0	0	0
T133	416	0	0	0
T134	630	0	0	0
T137	0	2	0	0
T138	0	2	0	0
T139	0	2	0	0
T181	431	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	107431	0	0
T36	856	67	0	0
T37	0	10	0	0
T38	0	92	0	0
T43	599	0	0	0
T44	30678	0	0	0
T56	0	83	0	0
T61	523	0	0	0
T62	1947	0	0	0
T63	522	0	0	0
T73	0	96	0	0
T77	0	47271	0	0
T80	0	137	0	0
T82	11358	0	0	0
T133	416	0	0	0
T134	630	0	0	0
T137	0	50	0	0
T138	0	43	0	0
T139	0	28	0	0
T181	431	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9507076	0	0
T1	24783	24321	0	0
T2	30367	29895	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	4265	0	0
T22	406	5	0	0
T23	535	134	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	151486	0	0
T36	856	48	0	0
T37	0	173	0	0
T38	0	476	0	0
T43	599	0	0	0
T44	30678	0	0	0
T56	0	1	0	0
T61	523	0	0	0
T62	1947	0	0	0
T63	522	0	0	0
T73	0	42	0	0
T77	0	112219	0	0
T80	0	121	0	0
T82	11358	0	0	0
T133	416	0	0	0
T134	630	0	0	0
T137	0	42	0	0
T138	0	44	0	0
T139	0	2	0	0
T181	431	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	48	0	0
T36	856	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T43	599	0	0	0
T44	30678	0	0	0
T56	0	1	0	0
T61	523	0	0	0
T62	1947	0	0	0
T63	522	0	0	0
T73	0	1	0	0
T77	0	1	0	0
T80	0	3	0	0
T82	11358	0	0	0
T133	416	0	0	0
T134	630	0	0	0
T137	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0
T181	431	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	8659519	0	0
T1	24783	24321	0	0
T2	30367	29895	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	4265	0	0
T22	406	5	0	0
T23	535	134	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	8661790	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	52	0	0
T36	856	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T43	599	0	0	0
T44	30678	0	0	0
T56	0	1	0	0
T61	523	0	0	0
T62	1947	0	0	0
T63	522	0	0	0
T73	0	1	0	0
T77	0	1	0	0
T80	0	3	0	0
T82	11358	0	0	0
T133	416	0	0	0
T134	630	0	0	0
T137	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0
T181	431	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	48	0	0
T36	856	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T43	599	0	0	0
T44	30678	0	0	0
T56	0	1	0	0
T61	523	0	0	0
T62	1947	0	0	0
T63	522	0	0	0
T73	0	1	0	0
T77	0	1	0	0
T80	0	3	0	0
T82	11358	0	0	0
T133	416	0	0	0
T134	630	0	0	0
T137	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0
T181	431	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	47	0	0
T36	856	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T43	599	0	0	0
T44	30678	0	0	0
T61	523	0	0	0
T62	1947	0	0	0
T63	522	0	0	0
T73	0	1	0	0
T77	0	1	0	0
T80	0	3	0	0
T82	11358	0	0	0
T133	416	0	0	0
T134	630	0	0	0
T137	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0
T152	0	1	0	0
T181	431	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	47	0	0
T36	856	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T43	599	0	0	0
T44	30678	0	0	0
T61	523	0	0	0
T62	1947	0	0	0
T63	522	0	0	0
T73	0	1	0	0
T77	0	1	0	0
T80	0	3	0	0
T82	11358	0	0	0
T133	416	0	0	0
T134	630	0	0	0
T137	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0
T152	0	1	0	0
T181	431	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	151413	0	0
T36	856	47	0	0
T37	0	171	0	0
T38	0	472	0	0
T43	599	0	0	0
T44	30678	0	0	0
T61	523	0	0	0
T62	1947	0	0	0
T63	522	0	0	0
T73	0	40	0	0
T77	0	112218	0	0
T80	0	118	0	0
T82	11358	0	0	0
T133	416	0	0	0
T134	630	0	0	0
T137	0	41	0	0
T138	0	42	0	0
T139	0	1	0	0
T152	0	43	0	0
T181	431	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	7002	0	0
T1	24783	12	0	0
T2	30367	34	0	0
T3	0	2	0	0
T4	727	3	0	0
T5	703	3	0	0
T6	2902	18	0	0
T14	8024	3	0	0
T15	0	3	0	0
T20	492	11	0	0
T21	4666	28	0	0
T22	406	0	0	0
T23	535	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9509518	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	22	0	0
T36	856	1	0	0
T43	599	0	0	0
T44	30678	0	0	0
T61	523	0	0	0
T62	1947	0	0	0
T63	522	0	0	0
T77	0	1	0	0
T78	0	1	0	0
T80	0	3	0	0
T82	11358	0	0	0
T133	416	0	0	0
T134	630	0	0	0
T137	0	1	0	0
T139	0	1	0	0
T153	0	1	0	0
T170	0	1	0	0
T176	0	1	0	0
T181	431	0	0	0
T200	0	1	0	0