Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T21,T2,T9
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T21,T2,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T21,T2,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T21,T2,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T2,T9
1	0	Covered	T2,T13,T34
1	1	Covered	T21,T2,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T21,T2,T9
0	1	Covered	T35,T87,T89
1	0	Covered	T35,T202,T203

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T21,T2,T9
0	1	Covered	T21,T2,T9
1	0	Covered	T204,T205

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T21,T2,T9
1	-	Covered	T21,T2,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T21,T2,T9
DetectSt	168	Covered	T21,T2,T9
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T21,T2,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T21,T2,T9
DebounceSt->IdleSt	163	Covered	T21,T206,T75
DetectSt->IdleSt	186	Covered	T35,T87,T89
DetectSt->StableSt	191	Covered	T21,T2,T9
IdleSt->DebounceSt	148	Covered	T21,T2,T9
StableSt->IdleSt	206	Covered	T21,T2,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T21,T2,T9
0	1	Covered	T21,T2,T9
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T2,T9
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T21,T2,T9
IdleSt	0	-	-	-	-	-	-	Covered	T21,T2,T9
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T21,T2,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T21,T206,T75
DebounceSt	-	0	0	-	-	-	-	Covered	T21,T2,T9
DetectSt	-	-	-	-	1	-	-	Covered	T35,T87,T89
DetectSt	-	-	-	-	0	1	-	Covered	T21,T2,T9
DetectSt	-	-	-	-	0	0	-	Covered	T21,T2,T9
StableSt	-	-	-	-	-	-	1	Covered	T21,T2,T9
StableSt	-	-	-	-	-	-	0	Covered	T21,T2,T9
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10142749	3416	0	0
CntIncr_A	10142749	114985	0	0
CntNoWrap_A	10142749	9503759	0	0
DetectStDropOut_A	10142749	430	0	0
DetectedOut_A	10142749	114434	0	0
DetectedPulseOut_A	10142749	1048	0	0
DisabledIdleSt_A	10142749	9000710	0	0
DisabledNoDetection_A	10142749	9002797	0	0
EnterDebounceSt_A	10142749	1733	0	0
EnterDetectSt_A	10142749	1684	0	0
EnterStableSt_A	10142749	1048	0	0
PulseIsPulse_A	10142749	1048	0	0
StayInStableSt	10142749	113226	0	0
gen_high_event_sva.HighLevelEvent_A	10142749	9509518	0	0
gen_high_level_sva.HighLevelEvent_A	10142749	9509518	0	0
gen_not_sticky_sva.StableStDropOut_A	10142749	873	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	3416	0	0
T1	24783	0	0	0
T2	30367	30	0	0
T3	1108	0	0	0
T7	624	0	0	0
T9	0	24	0	0
T13	0	10	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T21	4666	19	0	0
T22	406	0	0	0
T23	535	0	0	0
T34	0	10	0	0
T35	0	22	0	0
T42	0	26	0	0
T68	0	42	0	0
T69	0	46	0	0
T70	0	46	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	114985	0	0
T1	24783	0	0	0
T2	30367	690	0	0
T3	1108	0	0	0
T7	624	0	0	0
T9	0	600	0	0
T13	0	230	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T21	4666	822	0	0
T22	406	0	0	0
T23	535	0	0	0
T34	0	435	0	0
T35	0	605	0	0
T42	0	663	0	0
T68	0	1197	0	0
T69	0	1955	0	0
T70	0	1334	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9503759	0	0
T1	24783	24321	0	0
T2	30367	29865	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	4246	0	0
T22	406	5	0	0
T23	535	134	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	430	0	0
T35	6737	8	0	0
T85	20284	0	0	0
T87	0	11	0	0
T89	0	21	0	0
T91	0	26	0	0
T92	0	3	0	0
T93	0	12	0	0
T94	0	29	0	0
T97	0	24	0	0
T98	0	27	0	0
T109	561	0	0	0
T110	687	0	0	0
T111	578	0	0	0
T112	971	0	0	0
T113	429	0	0	0
T114	428	0	0	0
T115	17493	0	0	0
T116	768	0	0	0
T207	0	12	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	114434	0	0
T1	24783	0	0	0
T2	30367	1040	0	0
T3	1108	0	0	0
T7	624	0	0	0
T9	0	1406	0	0
T13	0	161	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T21	4666	11	0	0
T22	406	0	0	0
T23	535	0	0	0
T34	0	391	0	0
T42	0	1948	0	0
T68	0	1893	0	0
T69	0	7181	0	0
T70	0	1423	0	0
T208	0	1857	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	1048	0	0
T1	24783	0	0	0
T2	30367	15	0	0
T3	1108	0	0	0
T7	624	0	0	0
T9	0	12	0	0
T13	0	5	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T21	4666	1	0	0
T22	406	0	0	0
T23	535	0	0	0
T34	0	5	0	0
T42	0	13	0	0
T68	0	21	0	0
T69	0	23	0	0
T70	0	23	0	0
T208	0	21	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9000710	0	0
T1	24783	24321	0	0
T2	30367	25605	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	2015	0	0
T22	406	5	0	0
T23	535	134	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9002797	0	0
T1	24783	24331	0	0
T2	30367	25612	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	2015	0	0
T22	406	6	0	0
T23	535	135	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	1733	0	0
T1	24783	0	0	0
T2	30367	15	0	0
T3	1108	0	0	0
T7	624	0	0	0
T9	0	12	0	0
T13	0	5	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T21	4666	18	0	0
T22	406	0	0	0
T23	535	0	0	0
T34	0	5	0	0
T35	0	11	0	0
T42	0	13	0	0
T68	0	21	0	0
T69	0	23	0	0
T70	0	23	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	1684	0	0
T1	24783	0	0	0
T2	30367	15	0	0
T3	1108	0	0	0
T7	624	0	0	0
T9	0	12	0	0
T13	0	5	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T21	4666	1	0	0
T22	406	0	0	0
T23	535	0	0	0
T34	0	5	0	0
T35	0	11	0	0
T42	0	13	0	0
T68	0	21	0	0
T69	0	23	0	0
T70	0	23	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	1048	0	0
T1	24783	0	0	0
T2	30367	15	0	0
T3	1108	0	0	0
T7	624	0	0	0
T9	0	12	0	0
T13	0	5	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T21	4666	1	0	0
T22	406	0	0	0
T23	535	0	0	0
T34	0	5	0	0
T42	0	13	0	0
T68	0	21	0	0
T69	0	23	0	0
T70	0	23	0	0
T208	0	21	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	1048	0	0
T1	24783	0	0	0
T2	30367	15	0	0
T3	1108	0	0	0
T7	624	0	0	0
T9	0	12	0	0
T13	0	5	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T21	4666	1	0	0
T22	406	0	0	0
T23	535	0	0	0
T34	0	5	0	0
T42	0	13	0	0
T68	0	21	0	0
T69	0	23	0	0
T70	0	23	0	0
T208	0	21	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	113226	0	0
T1	24783	0	0	0
T2	30367	1021	0	0
T3	1108	0	0	0
T7	624	0	0	0
T9	0	1394	0	0
T13	0	156	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T21	4666	10	0	0
T22	406	0	0	0
T23	535	0	0	0
T34	0	384	0	0
T42	0	1930	0	0
T68	0	1869	0	0
T69	0	7152	0	0
T70	0	1400	0	0
T208	0	1834	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9509518	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9509518	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	873	0	0
T1	24783	0	0	0
T2	30367	11	0	0
T3	1108	0	0	0
T7	624	0	0	0
T9	0	12	0	0
T13	0	5	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T21	4666	1	0	0
T22	406	0	0	0
T23	535	0	0	0
T34	0	3	0	0
T42	0	8	0	0
T68	0	18	0	0
T69	0	17	0	0
T70	0	23	0	0
T208	0	19	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T21,T1,T2
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T21,T1,T2
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T2,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T1,T2
1	0	Covered	T6,T21,T1
1	1	Covered	T1,T2,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Covered	T84,T85,T80
1	0	Covered	T75,T76

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Covered	T1,T2,T8
1	0	Covered	T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T8
1	-	Covered	T1,T2,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T8
DetectSt	168	Covered	T1,T2,T8
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T2,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T8
DebounceSt->IdleSt	163	Covered	T10,T64,T121
DetectSt->IdleSt	186	Covered	T84,T85,T80
DetectSt->StableSt	191	Covered	T1,T2,T8
IdleSt->DebounceSt	148	Covered	T1,T2,T8
StableSt->IdleSt	206	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T8
0	1	Covered	T1,T2,T8
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T8
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T10,T64,T121
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T8
DetectSt	-	-	-	-	1	-	-	Covered	T84,T85,T80
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T8
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T8
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T8
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10142749	1003	0	0
CntIncr_A	10142749	54552	0	0
CntNoWrap_A	10142749	9506172	0	0
DetectStDropOut_A	10142749	34	0	0
DetectedOut_A	10142749	20261	0	0
DetectedPulseOut_A	10142749	424	0	0
DisabledIdleSt_A	10142749	9089592	0	0
DisabledNoDetection_A	10142749	9091146	0	0
EnterDebounceSt_A	10142749	543	0	0
EnterDetectSt_A	10142749	463	0	0
EnterStableSt_A	10142749	423	0	0
PulseIsPulse_A	10142749	423	0	0
StayInStableSt	10142749	19794	0	0
gen_high_level_sva.HighLevelEvent_A	10142749	9509518	0	0
gen_not_sticky_sva.StableStDropOut_A	10142749	379	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	1003	0	0
T1	24783	2	0	0
T2	30367	6	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	0	14	0	0
T9	0	10	0	0
T10	0	2	0	0
T11	0	6	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	4	0	0
T42	0	8	0	0
T64	0	1	0	0
T82	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	54552	0	0
T1	24783	141	0	0
T2	30367	138	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	0	1246	0	0
T9	0	430	0	0
T10	0	40	0	0
T11	0	426	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	108	0	0
T42	0	276	0	0
T64	0	20	0	0
T82	0	550	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9506172	0	0
T1	24783	24319	0	0
T2	30367	29889	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	4265	0	0
T22	406	5	0	0
T23	535	134	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	34	0	0
T66	830	0	0	0
T67	160371	0	0	0
T80	0	1	0	0
T84	21460	10	0	0
T85	0	4	0	0
T86	0	2	0	0
T88	0	1	0	0
T90	0	5	0	0
T95	0	3	0	0
T96	0	5	0	0
T99	0	3	0	0
T102	502	0	0	0
T103	422	0	0	0
T104	582	0	0	0
T105	505	0	0	0
T106	422	0	0	0
T107	724	0	0	0
T108	524	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	20261	0	0
T1	24783	7	0	0
T2	30367	145	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	0	85	0	0
T9	0	215	0	0
T11	0	61	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	118	0	0
T42	0	191	0	0
T68	0	147	0	0
T69	0	2124	0	0
T82	0	17	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	424	0	0
T1	24783	1	0	0
T2	30367	3	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	0	7	0	0
T9	0	5	0	0
T11	0	3	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	2	0	0
T42	0	4	0	0
T68	0	2	0	0
T69	0	6	0	0
T82	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9089592	0	0
T1	24783	20143	0	0
T2	30367	28859	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	4254	0	0
T22	406	5	0	0
T23	535	134	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9091146	0	0
T1	24783	20143	0	0
T2	30367	28867	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4255	0	0
T22	406	6	0	0
T23	535	135	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	543	0	0
T1	24783	1	0	0
T2	30367	3	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	0	7	0	0
T9	0	5	0	0
T10	0	2	0	0
T11	0	3	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	2	0	0
T42	0	4	0	0
T64	0	1	0	0
T82	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	463	0	0
T1	24783	1	0	0
T2	30367	3	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	0	7	0	0
T9	0	5	0	0
T11	0	3	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	2	0	0
T42	0	4	0	0
T68	0	2	0	0
T69	0	6	0	0
T82	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	423	0	0
T1	24783	1	0	0
T2	30367	3	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	0	7	0	0
T9	0	5	0	0
T11	0	3	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	2	0	0
T42	0	4	0	0
T68	0	2	0	0
T69	0	6	0	0
T82	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	423	0	0
T1	24783	1	0	0
T2	30367	3	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	0	7	0	0
T9	0	5	0	0
T11	0	3	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	2	0	0
T42	0	4	0	0
T68	0	2	0	0
T69	0	6	0	0
T82	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	19794	0	0
T1	24783	6	0	0
T2	30367	141	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	0	78	0	0
T9	0	210	0	0
T11	0	58	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	116	0	0
T42	0	187	0	0
T68	0	145	0	0
T69	0	2118	0	0
T82	0	15	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9509518	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	379	0	0
T1	24783	1	0	0
T2	30367	2	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	0	7	0	0
T9	0	5	0	0
T11	0	3	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	2	0	0
T42	0	4	0	0
T68	0	2	0	0
T69	0	6	0	0
T82	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T21,T2,T9
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T21,T2,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T21,T2,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T21,T2,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T2,T9
1	0	Covered	T2,T9,T13
1	1	Covered	T21,T2,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T21,T2,T9
0	1	Covered	T9,T42,T87
1	0	Covered	T9,T42,T68

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T21,T2,T13
0	1	Covered	T21,T2,T13
1	0	Covered	T42,T75,T209

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T21,T2,T13
1	-	Covered	T21,T2,T13

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T21,T2,T9
DetectSt	168	Covered	T21,T2,T9
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T21,T2,T13

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T21,T2,T9
DebounceSt->IdleSt	163	Covered	T21,T206,T75
DetectSt->IdleSt	186	Covered	T9,T42,T68
DetectSt->StableSt	191	Covered	T21,T2,T13
IdleSt->DebounceSt	148	Covered	T21,T2,T9
StableSt->IdleSt	206	Covered	T21,T2,T13

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T21,T2,T9
0	1	Covered	T21,T2,T9
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T2,T9
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T21,T2,T9
IdleSt	0	-	-	-	-	-	-	Covered	T21,T2,T9
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T21,T2,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T21,T206,T75
DebounceSt	-	0	0	-	-	-	-	Covered	T21,T2,T9
DetectSt	-	-	-	-	1	-	-	Covered	T9,T42,T68
DetectSt	-	-	-	-	0	1	-	Covered	T21,T2,T13
DetectSt	-	-	-	-	0	0	-	Covered	T21,T2,T9
StableSt	-	-	-	-	-	-	1	Covered	T21,T2,T13
StableSt	-	-	-	-	-	-	0	Covered	T21,T2,T13
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10142749	3034	0	0
CntIncr_A	10142749	102592	0	0
CntNoWrap_A	10142749	9504141	0	0
DetectStDropOut_A	10142749	403	0	0
DetectedOut_A	10142749	71288	0	0
DetectedPulseOut_A	10142749	753	0	0
DisabledIdleSt_A	10142749	9034025	0	0
DisabledNoDetection_A	10142749	9036181	0	0
EnterDebounceSt_A	10142749	1542	0	0
EnterDetectSt_A	10142749	1493	0	0
EnterStableSt_A	10142749	753	0	0
PulseIsPulse_A	10142749	753	0	0
StayInStableSt	10142749	70443	0	0
gen_high_event_sva.HighLevelEvent_A	10142749	9509518	0	0
gen_high_level_sva.HighLevelEvent_A	10142749	9509518	0	0
gen_not_sticky_sva.StableStDropOut_A	10142749	637	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	3034	0	0
T1	24783	0	0	0
T2	30367	48	0	0
T3	1108	0	0	0
T7	624	0	0	0
T9	0	42	0	0
T13	0	14	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T21	4666	17	0	0
T22	406	0	0	0
T23	535	0	0	0
T34	0	8	0	0
T35	0	56	0	0
T42	0	42	0	0
T68	0	32	0	0
T69	0	10	0	0
T70	0	30	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	102592	0	0
T1	24783	0	0	0
T2	30367	912	0	0
T3	1108	0	0	0
T7	624	0	0	0
T9	0	1078	0	0
T13	0	399	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T21	4666	688	0	0
T22	406	0	0	0
T23	535	0	0	0
T34	0	204	0	0
T35	0	1574	0	0
T42	0	1605	0	0
T68	0	1006	0	0
T69	0	380	0	0
T70	0	901	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9504141	0	0
T1	24783	24321	0	0
T2	30367	29847	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	4248	0	0
T22	406	5	0	0
T23	535	134	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	403	0	0
T9	6573	14	0	0
T10	4586	0	0	0
T11	6472	0	0	0
T12	944	0	0	0
T13	16325	0	0	0
T29	492	0	0	0
T30	527	0	0	0
T41	631	0	0	0
T42	0	8	0	0
T53	427	0	0	0
T59	524	0	0	0
T79	0	11	0	0
T87	0	21	0	0
T89	0	8	0	0
T91	0	15	0	0
T93	0	8	0	0
T94	0	15	0	0
T97	0	5	0	0
T210	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	71288	0	0
T1	24783	0	0	0
T2	30367	2732	0	0
T3	1108	0	0	0
T7	624	0	0	0
T13	0	284	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T21	4666	54	0	0
T22	406	0	0	0
T23	535	0	0	0
T34	0	289	0	0
T42	0	2	0	0
T69	0	130	0	0
T208	0	989	0	0
T211	0	1839	0	0
T212	0	2051	0	0
T213	0	2133	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	753	0	0
T1	24783	0	0	0
T2	30367	24	0	0
T3	1108	0	0	0
T7	624	0	0	0
T13	0	7	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T21	4666	2	0	0
T22	406	0	0	0
T23	535	0	0	0
T34	0	4	0	0
T42	0	2	0	0
T69	0	5	0	0
T208	0	26	0	0
T211	0	27	0	0
T212	0	20	0	0
T213	0	16	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9034025	0	0
T1	24783	24321	0	0
T2	30367	24303	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	2015	0	0
T22	406	5	0	0
T23	535	134	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9036181	0	0
T1	24783	24331	0	0
T2	30367	24304	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	2015	0	0
T22	406	6	0	0
T23	535	135	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	1542	0	0
T1	24783	0	0	0
T2	30367	24	0	0
T3	1108	0	0	0
T7	624	0	0	0
T9	0	21	0	0
T13	0	7	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T21	4666	15	0	0
T22	406	0	0	0
T23	535	0	0	0
T34	0	4	0	0
T35	0	28	0	0
T42	0	21	0	0
T68	0	16	0	0
T69	0	5	0	0
T70	0	15	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	1493	0	0
T1	24783	0	0	0
T2	30367	24	0	0
T3	1108	0	0	0
T7	624	0	0	0
T9	0	21	0	0
T13	0	7	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T21	4666	2	0	0
T22	406	0	0	0
T23	535	0	0	0
T34	0	4	0	0
T35	0	28	0	0
T42	0	21	0	0
T68	0	16	0	0
T69	0	5	0	0
T70	0	15	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	753	0	0
T1	24783	0	0	0
T2	30367	24	0	0
T3	1108	0	0	0
T7	624	0	0	0
T13	0	7	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T21	4666	2	0	0
T22	406	0	0	0
T23	535	0	0	0
T34	0	4	0	0
T42	0	2	0	0
T69	0	5	0	0
T208	0	26	0	0
T211	0	27	0	0
T212	0	20	0	0
T213	0	16	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	753	0	0
T1	24783	0	0	0
T2	30367	24	0	0
T3	1108	0	0	0
T7	624	0	0	0
T13	0	7	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T21	4666	2	0	0
T22	406	0	0	0
T23	535	0	0	0
T34	0	4	0	0
T42	0	2	0	0
T69	0	5	0	0
T208	0	26	0	0
T211	0	27	0	0
T212	0	20	0	0
T213	0	16	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	70443	0	0
T1	24783	0	0	0
T2	30367	2698	0	0
T3	1108	0	0	0
T7	624	0	0	0
T13	0	277	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T21	4666	52	0	0
T22	406	0	0	0
T23	535	0	0	0
T34	0	284	0	0
T69	0	125	0	0
T208	0	961	0	0
T211	0	1808	0	0
T212	0	2025	0	0
T213	0	2111	0	0
T214	0	1471	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9509518	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9509518	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	637	0	0
T1	24783	0	0	0
T2	30367	14	0	0
T3	1108	0	0	0
T7	624	0	0	0
T13	0	7	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T21	4666	2	0	0
T22	406	0	0	0
T23	535	0	0	0
T34	0	3	0	0
T69	0	5	0	0
T208	0	24	0	0
T211	0	23	0	0
T212	0	14	0	0
T213	0	10	0	0
T214	0	19	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T21,T1,T2
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T21,T1,T2
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T2,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T1,T2
1	0	Covered	T6,T21,T1
1	1	Covered	T1,T2,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Covered	T11,T215,T80
1	0	Covered	T75,T76

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Covered	T1,T2,T8
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T8
1	-	Covered	T1,T2,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T8
DetectSt	168	Covered	T1,T2,T8
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T2,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T8
DebounceSt->IdleSt	163	Covered	T1,T2,T82
DetectSt->IdleSt	186	Covered	T11,T215,T80
DetectSt->StableSt	191	Covered	T1,T2,T8
IdleSt->DebounceSt	148	Covered	T1,T2,T8
StableSt->IdleSt	206	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T8
0	1	Covered	T1,T2,T8
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T8
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T2,T82
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T8
DetectSt	-	-	-	-	1	-	-	Covered	T11,T215,T80
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T8
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T8
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T8
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10142749	848	0	0
CntIncr_A	10142749	47652	0	0
CntNoWrap_A	10142749	9506327	0	0
DetectStDropOut_A	10142749	58	0	0
DetectedOut_A	10142749	18359	0	0
DetectedPulseOut_A	10142749	333	0	0
DisabledIdleSt_A	10142749	9129412	0	0
DisabledNoDetection_A	10142749	9131075	0	0
EnterDebounceSt_A	10142749	453	0	0
EnterDetectSt_A	10142749	395	0	0
EnterStableSt_A	10142749	333	0	0
PulseIsPulse_A	10142749	333	0	0
StayInStableSt	10142749	18007	0	0
gen_high_level_sva.HighLevelEvent_A	10142749	9509518	0	0
gen_not_sticky_sva.StableStDropOut_A	10142749	312	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	848	0	0
T1	24783	21	0	0
T2	30367	13	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	0	18	0	0
T11	0	2	0	0
T13	0	2	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	2	0	0
T39	0	27	0	0
T44	0	24	0	0
T82	0	3	0	0
T215	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	47652	0	0
T1	24783	927	0	0
T2	30367	236	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	0	1188	0	0
T11	0	162	0	0
T13	0	55	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	56	0	0
T39	0	2585	0	0
T44	0	1320	0	0
T82	0	440	0	0
T215	0	203	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9506327	0	0
T1	24783	24300	0	0
T2	30367	29882	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	4265	0	0
T22	406	5	0	0
T23	535	134	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	58	0	0
T11	6472	1	0	0
T12	944	0	0	0
T13	16325	0	0	0
T27	1497	0	0	0
T30	527	0	0	0
T34	36282	0	0	0
T54	489	0	0	0
T59	524	0	0	0
T60	503	0	0	0
T74	407	0	0	0
T80	0	2	0	0
T88	0	4	0	0
T96	0	4	0	0
T141	0	3	0	0
T215	0	2	0	0
T216	0	10	0	0
T217	0	9	0	0
T218	0	7	0	0
T219	0	9	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	18359	0	0
T1	24783	600	0	0
T2	30367	345	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	0	525	0	0
T13	0	66	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	57	0	0
T39	0	78	0	0
T44	0	428	0	0
T82	0	48	0	0
T84	0	36	0	0
T85	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	333	0	0
T1	24783	9	0	0
T2	30367	6	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	0	9	0	0
T13	0	1	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	1	0	0
T39	0	13	0	0
T44	0	12	0	0
T82	0	1	0	0
T84	0	2	0	0
T85	0	7	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9129412	0	0
T1	24783	20143	0	0
T2	30367	27173	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	4211	0	0
T22	406	5	0	0
T23	535	134	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9131075	0	0
T1	24783	20143	0	0
T2	30367	27175	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4212	0	0
T22	406	6	0	0
T23	535	135	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	453	0	0
T1	24783	12	0	0
T2	30367	7	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	0	9	0	0
T11	0	1	0	0
T13	0	1	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	1	0	0
T39	0	14	0	0
T44	0	12	0	0
T82	0	2	0	0
T215	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	395	0	0
T1	24783	9	0	0
T2	30367	6	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	0	9	0	0
T11	0	1	0	0
T13	0	1	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	1	0	0
T39	0	13	0	0
T44	0	12	0	0
T82	0	1	0	0
T215	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	333	0	0
T1	24783	9	0	0
T2	30367	6	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	0	9	0	0
T13	0	1	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	1	0	0
T39	0	13	0	0
T44	0	12	0	0
T82	0	1	0	0
T84	0	2	0	0
T85	0	7	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	333	0	0
T1	24783	9	0	0
T2	30367	6	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	0	9	0	0
T13	0	1	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	1	0	0
T39	0	13	0	0
T44	0	12	0	0
T82	0	1	0	0
T84	0	2	0	0
T85	0	7	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	18007	0	0
T1	24783	591	0	0
T2	30367	339	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	0	516	0	0
T13	0	65	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	56	0	0
T39	0	65	0	0
T44	0	416	0	0
T82	0	47	0	0
T84	0	34	0	0
T85	0	35	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9509518	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	312	0	0
T1	24783	9	0	0
T2	30367	6	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	0	9	0	0
T13	0	1	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	1	0	0
T39	0	13	0	0
T44	0	12	0	0
T82	0	1	0	0
T84	0	2	0	0
T85	0	7	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T21,T2,T9
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T21,T2,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T21,T2,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T9,T13

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T2,T9
1	0	Covered	T2,T9,T13
1	1	Covered	T21,T2,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T13
0	1	Covered	T70,T87,T89
1	0	Covered	T9,T68,T70

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T13,T34
0	1	Covered	T2,T13,T34
1	0	Covered	T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T13,T34
1	-	Covered	T2,T13,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T21,T2,T9
DetectSt	168	Covered	T2,T9,T13
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T13,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T9,T13
DebounceSt->IdleSt	163	Covered	T21,T206,T75
DetectSt->IdleSt	186	Covered	T9,T68,T70
DetectSt->StableSt	191	Covered	T2,T13,T34
IdleSt->DebounceSt	148	Covered	T21,T2,T9
StableSt->IdleSt	206	Covered	T2,T13,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T21,T2,T9
0	1	Covered	T21,T2,T9
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T13
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T21,T2,T9
IdleSt	0	-	-	-	-	-	-	Covered	T21,T2,T9
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T9,T13
DebounceSt	-	0	1	0	-	-	-	Covered	T21,T206,T75
DebounceSt	-	0	0	-	-	-	-	Covered	T21,T2,T9
DetectSt	-	-	-	-	1	-	-	Covered	T9,T68,T70
DetectSt	-	-	-	-	0	1	-	Covered	T2,T13,T34
DetectSt	-	-	-	-	0	0	-	Covered	T2,T9,T13
StableSt	-	-	-	-	-	-	1	Covered	T2,T13,T34
StableSt	-	-	-	-	-	-	0	Covered	T2,T13,T34
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10142749	3149	0	0
CntIncr_A	10142749	103502	0	0
CntNoWrap_A	10142749	9504026	0	0
DetectStDropOut_A	10142749	414	0	0
DetectedOut_A	10142749	80515	0	0
DetectedPulseOut_A	10142749	945	0	0
DisabledIdleSt_A	10142749	9027915	0	0
DisabledNoDetection_A	10142749	9030065	0	0
EnterDebounceSt_A	10142749	1594	0	0
EnterDetectSt_A	10142749	1555	0	0
EnterStableSt_A	10142749	945	0	0
PulseIsPulse_A	10142749	945	0	0
StayInStableSt	10142749	79471	0	0
gen_high_event_sva.HighLevelEvent_A	10142749	9509518	0	0
gen_high_level_sva.HighLevelEvent_A	10142749	9509518	0	0
gen_not_sticky_sva.StableStDropOut_A	10142749	837	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	3149	0	0
T1	24783	0	0	0
T2	30367	22	0	0
T3	1108	0	0	0
T7	624	0	0	0
T9	0	6	0	0
T13	0	26	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T21	4666	23	0	0
T22	406	0	0	0
T23	535	0	0	0
T34	0	16	0	0
T35	0	56	0	0
T42	0	26	0	0
T68	0	32	0	0
T69	0	16	0	0
T70	0	54	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	103502	0	0
T1	24783	0	0	0
T2	30367	495	0	0
T3	1108	0	0	0
T7	624	0	0	0
T9	0	153	0	0
T13	0	897	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T21	4666	1012	0	0
T22	406	0	0	0
T23	535	0	0	0
T34	0	712	0	0
T35	0	1344	0	0
T42	0	858	0	0
T68	0	1006	0	0
T69	0	496	0	0
T70	0	1612	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9504026	0	0
T1	24783	24321	0	0
T2	30367	29873	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	4242	0	0
T22	406	5	0	0
T23	535	134	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	414	0	0
T38	28026	0	0	0
T46	723	0	0	0
T47	671	0	0	0
T56	6875	0	0	0
T57	509	0	0	0
T70	6994	9	0	0
T83	48501	0	0	0
T87	0	25	0	0
T89	0	21	0	0
T91	0	27	0	0
T92	0	24	0	0
T93	0	8	0	0
T94	0	11	0	0
T215	4218	0	0	0
T220	0	3	0	0
T221	0	9	0	0
T222	0	8	0	0
T223	536	0	0	0
T224	4419	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	80515	0	0
T2	30367	761	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	21518	0	0	0
T13	0	634	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	644	0	0
T35	0	1558	0	0
T40	778	0	0	0
T42	0	1491	0	0
T69	0	323	0	0
T208	0	375	0	0
T211	0	2066	0	0
T212	0	745	0	0
T213	0	350	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	945	0	0
T2	30367	11	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	21518	0	0	0
T13	0	13	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	8	0	0
T35	0	28	0	0
T40	778	0	0	0
T42	0	13	0	0
T69	0	8	0	0
T208	0	15	0	0
T211	0	30	0	0
T212	0	11	0	0
T213	0	5	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9027915	0	0
T1	24783	24321	0	0
T2	30367	25814	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	2015	0	0
T22	406	5	0	0
T23	535	134	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9030065	0	0
T1	24783	24331	0	0
T2	30367	25821	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	2015	0	0
T22	406	6	0	0
T23	535	135	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	1594	0	0
T1	24783	0	0	0
T2	30367	11	0	0
T3	1108	0	0	0
T7	624	0	0	0
T9	0	3	0	0
T13	0	13	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T21	4666	23	0	0
T22	406	0	0	0
T23	535	0	0	0
T34	0	8	0	0
T35	0	28	0	0
T42	0	13	0	0
T68	0	16	0	0
T69	0	8	0	0
T70	0	27	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	1555	0	0
T2	30367	11	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	21518	0	0	0
T9	0	3	0	0
T13	0	13	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	8	0	0
T35	0	28	0	0
T40	778	0	0	0
T42	0	13	0	0
T68	0	16	0	0
T69	0	8	0	0
T70	0	27	0	0
T208	0	15	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	945	0	0
T2	30367	11	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	21518	0	0	0
T13	0	13	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	8	0	0
T35	0	28	0	0
T40	778	0	0	0
T42	0	13	0	0
T69	0	8	0	0
T208	0	15	0	0
T211	0	30	0	0
T212	0	11	0	0
T213	0	5	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	945	0	0
T2	30367	11	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	21518	0	0	0
T13	0	13	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	8	0	0
T35	0	28	0	0
T40	778	0	0	0
T42	0	13	0	0
T69	0	8	0	0
T208	0	15	0	0
T211	0	30	0	0
T212	0	11	0	0
T213	0	5	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	79471	0	0
T2	30367	746	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	21518	0	0	0
T13	0	621	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	632	0	0
T35	0	1530	0	0
T40	778	0	0	0
T42	0	1472	0	0
T69	0	315	0	0
T208	0	358	0	0
T211	0	2034	0	0
T212	0	732	0	0
T213	0	343	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9509518	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9509518	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	837	0	0
T2	30367	7	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	21518	0	0	0
T13	0	13	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	4	0	0
T35	0	28	0	0
T40	778	0	0	0
T42	0	7	0	0
T69	0	8	0	0
T208	0	13	0	0
T211	0	28	0	0
T212	0	9	0	0
T213	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T21,T1,T2
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T21,T1,T2
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T2,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Covered	T6,T21,T1
1	1	Covered	T1,T2,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Covered	T1,T11,T82
1	0	Covered	T75,T76

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T34
0	1	Covered	T2,T8,T34
1	0	Covered	T75,T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T8,T34
1	-	Covered	T2,T8,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T8
DetectSt	168	Covered	T1,T2,T8
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T8,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T8
DebounceSt->IdleSt	163	Covered	T82,T215,T85
DetectSt->IdleSt	186	Covered	T1,T11,T82
DetectSt->StableSt	191	Covered	T2,T8,T34
IdleSt->DebounceSt	148	Covered	T1,T2,T8
StableSt->IdleSt	206	Covered	T2,T8,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T8
0	1	Covered	T1,T2,T8
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T8
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T82,T215,T85
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T8
DetectSt	-	-	-	-	1	-	-	Covered	T1,T11,T82
DetectSt	-	-	-	-	0	1	-	Covered	T2,T8,T34
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T8
StableSt	-	-	-	-	-	-	1	Covered	T2,T8,T34
StableSt	-	-	-	-	-	-	0	Covered	T2,T8,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10142749	883	0	0
CntIncr_A	10142749	51172	0	0
CntNoWrap_A	10142749	9506292	0	0
DetectStDropOut_A	10142749	71	0	0
DetectedOut_A	10142749	15700	0	0
DetectedPulseOut_A	10142749	339	0	0
DisabledIdleSt_A	10142749	9122428	0	0
DisabledNoDetection_A	10142749	9124084	0	0
EnterDebounceSt_A	10142749	469	0	0
EnterDetectSt_A	10142749	415	0	0
EnterStableSt_A	10142749	339	0	0
PulseIsPulse_A	10142749	339	0	0
StayInStableSt	10142749	15342	0	0
gen_high_level_sva.HighLevelEvent_A	10142749	9509518	0	0
gen_not_sticky_sva.StableStDropOut_A	10142749	316	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	883	0	0
T1	24783	2	0	0
T2	30367	6	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	0	4	0	0
T11	0	2	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T42	0	10	0	0
T82	0	12	0	0
T84	0	8	0	0
T215	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	51172	0	0
T1	24783	148	0	0
T2	30367	180	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	0	228	0	0
T11	0	162	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	52	0	0
T35	0	45	0	0
T42	0	310	0	0
T82	0	1829	0	0
T84	0	440	0	0
T215	0	101	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9506292	0	0
T1	24783	24319	0	0
T2	30367	29889	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	4265	0	0
T22	406	5	0	0
T23	535	134	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	71	0	0
T1	24783	1	0	0
T2	30367	0	0	0
T3	1108	0	0	0
T7	624	0	0	0
T11	0	1	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T73	0	3	0	0
T80	0	2	0	0
T82	0	5	0	0
T84	0	4	0	0
T96	0	12	0	0
T215	0	1	0	0
T216	0	3	0	0
T225	0	6	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	15700	0	0
T2	30367	106	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	21518	150	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	60	0	0
T35	0	79	0	0
T40	778	0	0	0
T42	0	269	0	0
T85	0	154	0	0
T115	0	455	0	0
T208	0	58	0	0
T211	0	52	0	0
T212	0	118	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	339	0	0
T2	30367	3	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	21518	2	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T40	778	0	0	0
T42	0	5	0	0
T85	0	7	0	0
T115	0	7	0	0
T208	0	1	0	0
T211	0	1	0	0
T212	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9122428	0	0
T1	24783	20143	0	0
T2	30367	29138	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	4265	0	0
T22	406	5	0	0
T23	535	134	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9124084	0	0
T1	24783	20143	0	0
T2	30367	29146	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	469	0	0
T1	24783	1	0	0
T2	30367	3	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	0	2	0	0
T11	0	1	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T42	0	5	0	0
T82	0	7	0	0
T84	0	4	0	0
T215	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	415	0	0
T1	24783	1	0	0
T2	30367	3	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	0	2	0	0
T11	0	1	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T42	0	5	0	0
T82	0	5	0	0
T84	0	4	0	0
T215	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	339	0	0
T2	30367	3	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	21518	2	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T40	778	0	0	0
T42	0	5	0	0
T85	0	7	0	0
T115	0	7	0	0
T208	0	1	0	0
T211	0	1	0	0
T212	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	339	0	0
T2	30367	3	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	21518	2	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T40	778	0	0	0
T42	0	5	0	0
T85	0	7	0	0
T115	0	7	0	0
T208	0	1	0	0
T211	0	1	0	0
T212	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	15342	0	0
T2	30367	103	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	21518	148	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	59	0	0
T35	0	78	0	0
T40	778	0	0	0
T42	0	260	0	0
T85	0	147	0	0
T115	0	448	0	0
T208	0	57	0	0
T211	0	51	0	0
T212	0	114	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9509518	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	316	0	0
T2	30367	3	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	21518	2	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T40	778	0	0	0
T42	0	1	0	0
T85	0	7	0	0
T115	0	7	0	0
T208	0	1	0	0
T211	0	1	0	0
T226	0	3	0	0