Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T21,T2,T9
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T21,T2,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T21,T2,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T21,T2,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T2,T9
1	0	Covered	T2,T9,T13
1	1	Covered	T21,T2,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T21,T2,T9
0	1	Covered	T9,T35,T227
1	0	Covered	T9,T42,T35

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T21,T2,T13
0	1	Covered	T21,T2,T13
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T21,T2,T13
1	-	Covered	T21,T2,T13

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T21,T2,T9
DetectSt	168	Covered	T21,T2,T9
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T21,T2,T13

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T21,T2,T9
DebounceSt->IdleSt	163	Covered	T21,T206,T75
DetectSt->IdleSt	186	Covered	T9,T42,T35
DetectSt->StableSt	191	Covered	T21,T2,T13
IdleSt->DebounceSt	148	Covered	T21,T2,T9
StableSt->IdleSt	206	Covered	T21,T2,T13

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T21,T2,T9
0	1	Covered	T21,T2,T9
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T2,T9
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T21,T2,T9
IdleSt	0	-	-	-	-	-	-	Covered	T21,T2,T9
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T21,T2,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T21,T206,T75
DebounceSt	-	0	0	-	-	-	-	Covered	T21,T2,T9
DetectSt	-	-	-	-	1	-	-	Covered	T9,T42,T35
DetectSt	-	-	-	-	0	1	-	Covered	T21,T2,T13
DetectSt	-	-	-	-	0	0	-	Covered	T21,T2,T9
StableSt	-	-	-	-	-	-	1	Covered	T21,T2,T13
StableSt	-	-	-	-	-	-	0	Covered	T21,T2,T13
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10142749	3165	0	0
CntIncr_A	10142749	106448	0	0
CntNoWrap_A	10142749	9504010	0	0
DetectStDropOut_A	10142749	388	0	0
DetectedOut_A	10142749	108099	0	0
DetectedPulseOut_A	10142749	1025	0	0
DisabledIdleSt_A	10142749	9006872	0	0
DisabledNoDetection_A	10142749	9008983	0	0
EnterDebounceSt_A	10142749	1600	0	0
EnterDetectSt_A	10142749	1566	0	0
EnterStableSt_A	10142749	1025	0	0
PulseIsPulse_A	10142749	1025	0	0
StayInStableSt	10142749	106935	0	0
gen_high_event_sva.HighLevelEvent_A	10142749	9509518	0	0
gen_high_level_sva.HighLevelEvent_A	10142749	9509518	0	0
gen_not_sticky_sva.StableStDropOut_A	10142749	886	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	3165	0	0
T1	24783	0	0	0
T2	30367	48	0	0
T3	1108	0	0	0
T7	624	0	0	0
T9	0	42	0	0
T13	0	28	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T21	4666	12	0	0
T22	406	0	0	0
T23	535	0	0	0
T34	0	40	0	0
T35	0	28	0	0
T42	0	26	0	0
T68	0	32	0	0
T69	0	20	0	0
T70	0	22	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	106448	0	0
T1	24783	0	0	0
T2	30367	1032	0	0
T3	1108	0	0	0
T7	624	0	0	0
T9	0	1078	0	0
T13	0	574	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T21	4666	512	0	0
T22	406	0	0	0
T23	535	0	0	0
T34	0	1340	0	0
T35	0	774	0	0
T42	0	992	0	0
T68	0	912	0	0
T69	0	710	0	0
T70	0	561	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9504010	0	0
T1	24783	24321	0	0
T2	30367	29847	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	4253	0	0
T22	406	5	0	0
T23	535	134	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	388	0	0
T9	6573	14	0	0
T10	4586	0	0	0
T11	6472	0	0	0
T12	944	0	0	0
T13	16325	0	0	0
T29	492	0	0	0
T30	527	0	0	0
T35	0	7	0	0
T41	631	0	0	0
T53	427	0	0	0
T59	524	0	0	0
T87	0	22	0	0
T89	0	5	0	0
T91	0	21	0	0
T92	0	9	0	0
T93	0	4	0	0
T94	0	29	0	0
T210	0	15	0	0
T227	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	108099	0	0
T1	24783	0	0	0
T2	30367	2612	0	0
T3	1108	0	0	0
T7	624	0	0	0
T13	0	1893	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T21	4666	13	0	0
T22	406	0	0	0
T23	535	0	0	0
T34	0	2920	0	0
T68	0	662	0	0
T69	0	1219	0	0
T70	0	116	0	0
T208	0	206	0	0
T211	0	510	0	0
T212	0	222	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	1025	0	0
T1	24783	0	0	0
T2	30367	24	0	0
T3	1108	0	0	0
T7	624	0	0	0
T13	0	14	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T21	4666	1	0	0
T22	406	0	0	0
T23	535	0	0	0
T34	0	20	0	0
T68	0	16	0	0
T69	0	10	0	0
T70	0	11	0	0
T208	0	3	0	0
T211	0	11	0	0
T212	0	6	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9006872	0	0
T1	24783	24321	0	0
T2	30367	24303	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	2015	0	0
T22	406	5	0	0
T23	535	134	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9008983	0	0
T1	24783	24331	0	0
T2	30367	24304	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	2015	0	0
T22	406	6	0	0
T23	535	135	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	1600	0	0
T1	24783	0	0	0
T2	30367	24	0	0
T3	1108	0	0	0
T7	624	0	0	0
T9	0	21	0	0
T13	0	14	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T21	4666	11	0	0
T22	406	0	0	0
T23	535	0	0	0
T34	0	20	0	0
T35	0	14	0	0
T42	0	13	0	0
T68	0	16	0	0
T69	0	10	0	0
T70	0	11	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	1566	0	0
T1	24783	0	0	0
T2	30367	24	0	0
T3	1108	0	0	0
T7	624	0	0	0
T9	0	21	0	0
T13	0	14	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T21	4666	1	0	0
T22	406	0	0	0
T23	535	0	0	0
T34	0	20	0	0
T35	0	14	0	0
T42	0	13	0	0
T68	0	16	0	0
T69	0	10	0	0
T70	0	11	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	1025	0	0
T1	24783	0	0	0
T2	30367	24	0	0
T3	1108	0	0	0
T7	624	0	0	0
T13	0	14	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T21	4666	1	0	0
T22	406	0	0	0
T23	535	0	0	0
T34	0	20	0	0
T68	0	16	0	0
T69	0	10	0	0
T70	0	11	0	0
T208	0	3	0	0
T211	0	11	0	0
T212	0	6	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	1025	0	0
T1	24783	0	0	0
T2	30367	24	0	0
T3	1108	0	0	0
T7	624	0	0	0
T13	0	14	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T21	4666	1	0	0
T22	406	0	0	0
T23	535	0	0	0
T34	0	20	0	0
T68	0	16	0	0
T69	0	10	0	0
T70	0	11	0	0
T208	0	3	0	0
T211	0	11	0	0
T212	0	6	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	106935	0	0
T1	24783	0	0	0
T2	30367	2578	0	0
T3	1108	0	0	0
T7	624	0	0	0
T13	0	1875	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T21	4666	12	0	0
T22	406	0	0	0
T23	535	0	0	0
T34	0	2889	0	0
T68	0	644	0	0
T69	0	1208	0	0
T70	0	105	0	0
T208	0	202	0	0
T211	0	498	0	0
T212	0	215	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9509518	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9509518	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	886	0	0
T1	24783	0	0	0
T2	30367	14	0	0
T3	1108	0	0	0
T7	624	0	0	0
T13	0	10	0	0
T14	8024	0	0	0
T15	629	0	0	0
T16	435	0	0	0
T21	4666	1	0	0
T22	406	0	0	0
T23	535	0	0	0
T34	0	9	0	0
T68	0	14	0	0
T69	0	9	0	0
T70	0	11	0	0
T208	0	2	0	0
T211	0	10	0	0
T212	0	5	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T21,T2,T8
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T21,T2,T8
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T8,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T8,T11

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T8,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T2,T8
1	0	Covered	T6,T21,T1
1	1	Covered	T2,T8,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T11
0	1	Covered	T44,T215,T85
1	0	Covered	T75,T76

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T11
0	1	Covered	T2,T8,T11
1	0	Covered	T75

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T8,T11
1	-	Covered	T2,T8,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T8,T11
DetectSt	168	Covered	T2,T8,T11
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T8,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T8,T11
DebounceSt->IdleSt	163	Covered	T2,T215,T84
DetectSt->IdleSt	186	Covered	T44,T215,T85
DetectSt->StableSt	191	Covered	T2,T8,T11
IdleSt->DebounceSt	148	Covered	T2,T8,T11
StableSt->IdleSt	206	Covered	T2,T8,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T8,T11
0	1	Covered	T2,T8,T11
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T11
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T8,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T8,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T215,T84
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T8,T11
DetectSt	-	-	-	-	1	-	-	Covered	T44,T215,T85
DetectSt	-	-	-	-	0	1	-	Covered	T2,T8,T11
DetectSt	-	-	-	-	0	0	-	Covered	T2,T8,T11
StableSt	-	-	-	-	-	-	1	Covered	T2,T8,T11
StableSt	-	-	-	-	-	-	0	Covered	T2,T8,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10142749	1009	0	0
CntIncr_A	10142749	58086	0	0
CntNoWrap_A	10142749	9506166	0	0
DetectStDropOut_A	10142749	92	0	0
DetectedOut_A	10142749	19672	0	0
DetectedPulseOut_A	10142749	377	0	0
DisabledIdleSt_A	10142749	9095324	0	0
DisabledNoDetection_A	10142749	9096948	0	0
EnterDebounceSt_A	10142749	536	0	0
EnterDetectSt_A	10142749	473	0	0
EnterStableSt_A	10142749	377	0	0
PulseIsPulse_A	10142749	377	0	0
StayInStableSt	10142749	19250	0	0
gen_high_level_sva.HighLevelEvent_A	10142749	9509518	0	0
gen_not_sticky_sva.StableStDropOut_A	10142749	329	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	1009	0	0
T2	30367	11	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	21518	6	0	0
T11	0	6	0	0
T13	0	8	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	22	0	0
T40	778	0	0	0
T44	0	4	0	0
T68	0	2	0	0
T69	0	2	0	0
T82	0	2	0	0
T215	0	21	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	58086	0	0
T2	30367	249	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	21518	312	0	0
T11	0	474	0	0
T13	0	284	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	682	0	0
T40	778	0	0	0
T44	0	290	0	0
T68	0	64	0	0
T69	0	167	0	0
T82	0	270	0	0
T215	0	750	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9506166	0	0
T1	24783	24321	0	0
T2	30367	29884	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	4265	0	0
T22	406	5	0	0
T23	535	134	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	92	0	0
T28	1114	0	0	0
T44	30678	2	0	0
T45	764	0	0	0
T49	747	0	0	0
T64	2915	0	0	0
T65	2124	0	0	0
T68	13585	0	0	0
T82	11358	0	0	0
T85	0	2	0	0
T90	0	9	0	0
T115	0	12	0	0
T121	432	0	0	0
T141	0	1	0	0
T181	431	0	0	0
T215	0	10	0	0
T225	0	10	0	0
T228	0	7	0	0
T229	0	8	0	0
T230	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	19672	0	0
T2	30367	236	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	21518	256	0	0
T11	0	13	0	0
T13	0	198	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	559	0	0
T40	778	0	0	0
T68	0	65	0	0
T69	0	278	0	0
T82	0	13	0	0
T84	0	58	0	0
T208	0	94	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	377	0	0
T2	30367	5	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	21518	3	0	0
T11	0	3	0	0
T13	0	4	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	11	0	0
T40	778	0	0	0
T68	0	1	0	0
T69	0	1	0	0
T82	0	1	0	0
T84	0	7	0	0
T208	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9095324	0	0
T1	24783	24321	0	0
T2	30367	27293	0	0
T4	727	326	0	0
T5	703	302	0	0
T6	2902	497	0	0
T14	8024	7623	0	0
T20	492	91	0	0
T21	4666	4252	0	0
T22	406	5	0	0
T23	535	134	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9096948	0	0
T1	24783	24331	0	0
T2	30367	27295	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4253	0	0
T22	406	6	0	0
T23	535	135	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	536	0	0
T2	30367	6	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	21518	3	0	0
T11	0	3	0	0
T13	0	4	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	11	0	0
T40	778	0	0	0
T44	0	2	0	0
T68	0	1	0	0
T69	0	1	0	0
T82	0	1	0	0
T215	0	11	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	473	0	0
T2	30367	5	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	21518	3	0	0
T11	0	3	0	0
T13	0	4	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	11	0	0
T40	778	0	0	0
T44	0	2	0	0
T68	0	1	0	0
T69	0	1	0	0
T82	0	1	0	0
T215	0	10	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	377	0	0
T2	30367	5	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	21518	3	0	0
T11	0	3	0	0
T13	0	4	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	11	0	0
T40	778	0	0	0
T68	0	1	0	0
T69	0	1	0	0
T82	0	1	0	0
T84	0	7	0	0
T208	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	377	0	0
T2	30367	5	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	21518	3	0	0
T11	0	3	0	0
T13	0	4	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	11	0	0
T40	778	0	0	0
T68	0	1	0	0
T69	0	1	0	0
T82	0	1	0	0
T84	0	7	0	0
T208	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	19250	0	0
T2	30367	229	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	21518	253	0	0
T11	0	10	0	0
T13	0	190	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	548	0	0
T40	778	0	0	0
T68	0	64	0	0
T69	0	277	0	0
T82	0	12	0	0
T84	0	50	0	0
T208	0	93	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	9509518	0	0
T1	24783	24331	0	0
T2	30367	29907	0	0
T4	727	327	0	0
T5	703	303	0	0
T6	2902	502	0	0
T14	8024	7624	0	0
T20	492	92	0	0
T21	4666	4266	0	0
T22	406	6	0	0
T23	535	135	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10142749	329	0	0
T2	30367	3	0	0
T3	1108	0	0	0
T7	624	0	0	0
T8	21518	3	0	0
T11	0	3	0	0
T15	629	0	0	0
T16	435	0	0	0
T17	612	0	0	0
T18	416	0	0	0
T19	502	0	0	0
T34	0	11	0	0
T40	778	0	0	0
T68	0	1	0	0
T69	0	1	0	0
T82	0	1	0	0
T84	0	6	0	0
T208	0	1	0	0
T226	0	5	0	0