Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1592125073	9594	0	0
auto_block_debounce_ctl_rd_A	1592125073	1675	0	0
auto_block_out_ctl_rd_A	1592125073	2179	0	0
com_det_ctl_0_rd_A	1592125073	4312	0	0
com_det_ctl_1_rd_A	1592125073	4411	0	0
com_det_ctl_2_rd_A	1592125073	4410	0	0
com_det_ctl_3_rd_A	1592125073	4366	0	0
com_out_ctl_0_rd_A	1592125073	4508	0	0
com_out_ctl_1_rd_A	1592125073	4723	0	0
com_out_ctl_2_rd_A	1592125073	4721	0	0
com_out_ctl_3_rd_A	1592125073	4880	0	0
com_pre_det_ctl_0_rd_A	1592125073	1214	0	0
com_pre_det_ctl_1_rd_A	1592125073	1283	0	0
com_pre_det_ctl_2_rd_A	1592125073	1388	0	0
com_pre_det_ctl_3_rd_A	1592125073	1322	0	0
com_pre_sel_ctl_0_rd_A	1592125073	4772	0	0
com_pre_sel_ctl_1_rd_A	1592125073	4884	0	0
com_pre_sel_ctl_2_rd_A	1592125073	4830	0	0
com_pre_sel_ctl_3_rd_A	1592125073	4968	0	0
com_sel_ctl_0_rd_A	1592125073	4913	0	0
com_sel_ctl_1_rd_A	1592125073	4794	0	0
com_sel_ctl_2_rd_A	1592125073	4883	0	0
com_sel_ctl_3_rd_A	1592125073	5018	0	0
ec_rst_ctl_rd_A	1592125073	2476	0	0
intr_enable_rd_A	1592125073	2195	0	0
key_intr_ctl_rd_A	1592125073	2971	0	0
key_intr_debounce_ctl_rd_A	1592125073	1312	0	0
key_invert_ctl_rd_A	1592125073	4304	0	0
pin_allowed_ctl_rd_A	1592125073	4792	0	0
pin_out_ctl_rd_A	1592125073	3543	0	0
pin_out_value_rd_A	1592125073	3771	0	0
regwen_rd_A	1592125073	1530	0	0
ulp_ac_debounce_ctl_rd_A	1592125073	1350	0	0
ulp_ctl_rd_A	1592125073	1346	0	0
ulp_lid_debounce_ctl_rd_A	1592125073	1390	0	0
ulp_pwrb_debounce_ctl_rd_A	1592125073	1354	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1592125073	9594	0	0
T10	210703	10	0	0
T11	776625	0	0	0
T12	29688	0	0	0
T13	179571	0	0	0
T29	118201	0	0	0
T30	63246	0	0	0
T34	435395	0	0	0
T38	0	10	0	0
T53	29960	0	0	0
T56	0	9	0	0
T59	62944	0	0	0
T73	0	12	0	0
T74	34677	0	0	0
T78	0	14	0	0
T80	0	6	0	0
T161	0	12	0	0
T250	0	8	0	0
T251	0	7	0	0
T252	0	11	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1592125073	1675	0	0
T8	107590	0	0	0
T9	788831	0	0	0
T10	210703	0	0	0
T29	118201	0	0	0
T33	84701	0	0	0
T38	0	50	0	0
T40	319347	5	0	0
T41	296910	3	0	0
T43	0	3	0	0
T48	101524	0	0	0
T52	57141	0	0	0
T53	29960	0	0	0
T56	0	27	0	0
T107	0	19	0	0
T110	0	9	0	0
T116	0	5	0	0
T161	0	41	0	0
T252	0	43	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1592125073	2179	0	0
T8	107590	0	0	0
T9	788831	0	0	0
T10	210703	0	0	0
T29	118201	0	0	0
T33	84701	0	0	0
T38	0	40	0	0
T40	319347	6	0	0
T41	296910	8	0	0
T43	0	10	0	0
T48	101524	0	0	0
T52	57141	0	0	0
T53	29960	0	0	0
T56	0	12	0	0
T107	0	12	0	0
T110	0	7	0	0
T116	0	4	0	0
T161	0	39	0	0
T252	0	34	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1592125073	4312	0	0
T8	107590	35	0	0
T9	788831	0	0	0
T10	210703	0	0	0
T11	776625	37	0	0
T29	118201	0	0	0
T33	84701	0	0	0
T38	0	54	0	0
T39	0	90	0	0
T41	296910	0	0	0
T42	0	91	0	0
T44	0	76	0	0
T48	101524	0	0	0
T52	57141	0	0	0
T53	29960	0	0	0
T56	0	10	0	0
T82	0	53	0	0
T84	0	28	0	0
T115	0	69	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1592125073	4411	0	0
T8	107590	40	0	0
T9	788831	0	0	0
T10	210703	0	0	0
T11	776625	35	0	0
T29	118201	0	0	0
T33	84701	0	0	0
T38	0	62	0	0
T39	0	77	0	0
T41	296910	0	0	0
T42	0	73	0	0
T44	0	38	0	0
T48	101524	0	0	0
T52	57141	0	0	0
T53	29960	0	0	0
T56	0	7	0	0
T82	0	49	0	0
T84	0	53	0	0
T115	0	91	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1592125073	4410	0	0
T8	107590	35	0	0
T9	788831	0	0	0
T10	210703	0	0	0
T11	776625	57	0	0
T29	118201	0	0	0
T33	84701	0	0	0
T38	0	52	0	0
T39	0	49	0	0
T41	296910	0	0	0
T42	0	104	0	0
T44	0	62	0	0
T48	101524	0	0	0
T52	57141	0	0	0
T53	29960	0	0	0
T56	0	6	0	0
T82	0	27	0	0
T84	0	49	0	0
T115	0	60	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1592125073	4366	0	0
T8	107590	42	0	0
T9	788831	0	0	0
T10	210703	0	0	0
T11	776625	59	0	0
T29	118201	0	0	0
T33	84701	0	0	0
T38	0	73	0	0
T39	0	79	0	0
T41	296910	0	0	0
T42	0	75	0	0
T44	0	49	0	0
T48	101524	0	0	0
T52	57141	0	0	0
T53	29960	0	0	0
T56	0	9	0	0
T82	0	45	0	0
T84	0	39	0	0
T115	0	57	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1592125073	4508	0	0
T8	107590	28	0	0
T9	788831	0	0	0
T10	210703	0	0	0
T11	776625	25	0	0
T29	118201	0	0	0
T33	84701	0	0	0
T38	0	79	0	0
T39	0	63	0	0
T41	296910	0	0	0
T42	0	63	0	0
T44	0	50	0	0
T48	101524	0	0	0
T52	57141	0	0	0
T53	29960	0	0	0
T56	0	10	0	0
T82	0	48	0	0
T84	0	12	0	0
T115	0	57	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1592125073	4723	0	0
T8	107590	59	0	0
T9	788831	0	0	0
T10	210703	0	0	0
T11	776625	46	0	0
T29	118201	0	0	0
T33	84701	0	0	0
T38	0	57	0	0
T39	0	54	0	0
T41	296910	0	0	0
T42	0	67	0	0
T44	0	52	0	0
T48	101524	0	0	0
T52	57141	0	0	0
T53	29960	0	0	0
T56	0	8	0	0
T82	0	54	0	0
T84	0	44	0	0
T115	0	81	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1592125073	4721	0	0
T8	107590	41	0	0
T9	788831	0	0	0
T10	210703	0	0	0
T11	776625	32	0	0
T29	118201	0	0	0
T33	84701	0	0	0
T38	0	65	0	0
T39	0	54	0	0
T41	296910	0	0	0
T42	0	77	0	0
T44	0	23	0	0
T48	101524	0	0	0
T52	57141	0	0	0
T53	29960	0	0	0
T56	0	6	0	0
T82	0	46	0	0
T84	0	68	0	0
T115	0	55	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1592125073	4880	0	0
T8	107590	52	0	0
T9	788831	0	0	0
T10	210703	0	0	0
T11	776625	30	0	0
T29	118201	0	0	0
T33	84701	0	0	0
T38	0	45	0	0
T39	0	65	0	0
T41	296910	0	0	0
T42	0	66	0	0
T44	0	51	0	0
T48	101524	0	0	0
T52	57141	0	0	0
T53	29960	0	0	0
T56	0	24	0	0
T82	0	44	0	0
T84	0	58	0	0
T115	0	62	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1592125073	1214	0	0
T38	326459	16	0	0
T47	120797	0	0	0
T56	687582	7	0	0
T57	20398	0	0	0
T58	238329	0	0	0
T73	0	17	0	0
T83	235240	0	0	0
T101	0	20	0	0
T124	0	9	0	0
T131	0	11	0	0
T157	0	2	0	0
T161	0	32	0	0
T184	73747	0	0	0
T215	204581	0	0	0
T223	21451	0	0	0
T224	375657	0	0	0
T252	0	16	0	0
T253	0	15	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1592125073	1283	0	0
T38	326459	17	0	0
T47	120797	0	0	0
T56	687582	2	0	0
T57	20398	0	0	0
T58	238329	0	0	0
T73	0	16	0	0
T83	235240	0	0	0
T101	0	28	0	0
T124	0	6	0	0
T131	0	9	0	0
T157	0	3	0	0
T161	0	49	0	0
T184	73747	0	0	0
T215	204581	0	0	0
T223	21451	0	0	0
T224	375657	0	0	0
T252	0	5	0	0
T253	0	16	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1592125073	1388	0	0
T38	326459	18	0	0
T47	120797	0	0	0
T56	687582	5	0	0
T57	20398	0	0	0
T58	238329	0	0	0
T73	0	12	0	0
T83	235240	0	0	0
T101	0	16	0	0
T124	0	7	0	0
T131	0	18	0	0
T161	0	19	0	0
T184	73747	0	0	0
T192	0	30	0	0
T215	204581	0	0	0
T223	21451	0	0	0
T224	375657	0	0	0
T252	0	13	0	0
T253	0	15	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1592125073	1322	0	0
T38	326459	25	0	0
T47	120797	0	0	0
T56	687582	12	0	0
T57	20398	0	0	0
T58	238329	0	0	0
T73	0	6	0	0
T83	235240	0	0	0
T101	0	23	0	0
T124	0	6	0	0
T131	0	12	0	0
T157	0	7	0	0
T161	0	19	0	0
T184	73747	0	0	0
T192	0	27	0	0
T215	204581	0	0	0
T223	21451	0	0	0
T224	375657	0	0	0
T252	0	17	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1592125073	4772	0	0
T8	107590	53	0	0
T9	788831	0	0	0
T10	210703	0	0	0
T11	776625	17	0	0
T29	118201	0	0	0
T33	84701	0	0	0
T38	0	57	0	0
T39	0	67	0	0
T41	296910	0	0	0
T42	0	80	0	0
T44	0	34	0	0
T48	101524	0	0	0
T52	57141	0	0	0
T53	29960	0	0	0
T56	0	1	0	0
T82	0	35	0	0
T84	0	36	0	0
T115	0	72	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1592125073	4884	0	0
T8	107590	38	0	0
T9	788831	0	0	0
T10	210703	0	0	0
T11	776625	29	0	0
T29	118201	0	0	0
T33	84701	0	0	0
T38	0	43	0	0
T39	0	57	0	0
T41	296910	0	0	0
T42	0	98	0	0
T44	0	44	0	0
T48	101524	0	0	0
T52	57141	0	0	0
T53	29960	0	0	0
T56	0	8	0	0
T82	0	51	0	0
T84	0	42	0	0
T115	0	77	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1592125073	4830	0	0
T8	107590	51	0	0
T9	788831	0	0	0
T10	210703	0	0	0
T11	776625	38	0	0
T29	118201	0	0	0
T33	84701	0	0	0
T38	0	71	0	0
T39	0	67	0	0
T41	296910	0	0	0
T42	0	66	0	0
T44	0	60	0	0
T48	101524	0	0	0
T52	57141	0	0	0
T53	29960	0	0	0
T56	0	4	0	0
T82	0	59	0	0
T84	0	33	0	0
T115	0	76	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1592125073	4968	0	0
T8	107590	70	0	0
T9	788831	0	0	0
T10	210703	0	0	0
T11	776625	62	0	0
T29	118201	0	0	0
T33	84701	0	0	0
T38	0	67	0	0
T39	0	76	0	0
T41	296910	0	0	0
T42	0	64	0	0
T44	0	36	0	0
T48	101524	0	0	0
T52	57141	0	0	0
T53	29960	0	0	0
T56	0	15	0	0
T82	0	44	0	0
T84	0	29	0	0
T115	0	72	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1592125073	4913	0	0
T8	107590	45	0	0
T9	788831	0	0	0
T10	210703	0	0	0
T11	776625	33	0	0
T29	118201	0	0	0
T33	84701	0	0	0
T38	0	49	0	0
T39	0	81	0	0
T41	296910	0	0	0
T42	0	86	0	0
T44	0	35	0	0
T48	101524	0	0	0
T52	57141	0	0	0
T53	29960	0	0	0
T56	0	11	0	0
T82	0	51	0	0
T84	0	34	0	0
T115	0	58	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1592125073	4794	0	0
T8	107590	19	0	0
T9	788831	0	0	0
T10	210703	0	0	0
T11	776625	38	0	0
T29	118201	0	0	0
T33	84701	0	0	0
T38	0	42	0	0
T39	0	72	0	0
T41	296910	0	0	0
T42	0	74	0	0
T44	0	69	0	0
T48	101524	0	0	0
T52	57141	0	0	0
T53	29960	0	0	0
T56	0	18	0	0
T82	0	42	0	0
T84	0	65	0	0
T115	0	62	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1592125073	4883	0	0
T8	107590	39	0	0
T9	788831	0	0	0
T10	210703	0	0	0
T11	776625	55	0	0
T29	118201	0	0	0
T33	84701	0	0	0
T38	0	64	0	0
T39	0	62	0	0
T41	296910	0	0	0
T42	0	66	0	0
T44	0	42	0	0
T48	101524	0	0	0
T52	57141	0	0	0
T53	29960	0	0	0
T56	0	4	0	0
T82	0	31	0	0
T84	0	25	0	0
T115	0	71	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1592125073	5018	0	0
T8	107590	34	0	0
T9	788831	0	0	0
T10	210703	0	0	0
T11	776625	53	0	0
T29	118201	0	0	0
T33	84701	0	0	0
T38	0	64	0	0
T39	0	64	0	0
T41	296910	0	0	0
T42	0	85	0	0
T44	0	31	0	0
T48	101524	0	0	0
T52	57141	0	0	0
T53	29960	0	0	0
T56	0	3	0	0
T82	0	55	0	0
T84	0	35	0	0
T115	0	89	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1592125073	2476	0	0
T8	107590	18	0	0
T9	788831	0	0	0
T10	210703	0	0	0
T11	776625	0	0	0
T29	118201	0	0	0
T33	84701	0	0	0
T38	0	37	0	0
T39	0	51	0	0
T41	296910	0	0	0
T42	0	26	0	0
T44	0	25	0	0
T48	101524	0	0	0
T52	57141	0	0	0
T53	29960	0	0	0
T56	0	10	0	0
T84	0	14	0	0
T112	0	2	0	0
T115	0	15	0	0
T211	0	15	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1592125073	2195	0	0
T38	0	45	0	0
T39	628003	9	0	0
T46	18086	0	0	0
T50	224041	0	0	0
T51	12113	0	0	0
T56	687582	12	0	0
T70	839339	0	0	0
T73	0	72	0	0
T123	137765	0	0	0
T124	0	10	0	0
T127	118139	0	0	0
T128	76900	0	0	0
T131	0	39	0	0
T161	0	37	0	0
T173	99491	0	0	0
T252	0	25	0	0
T253	0	38	0	0
T254	0	22	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1592125073	2971	0	0
T38	0	28	0	0
T39	628003	5	0	0
T46	18086	0	0	0
T50	224041	0	0	0
T51	12113	0	0	0
T56	687582	17	0	0
T70	839339	0	0	0
T73	0	5	0	0
T123	137765	0	0	0
T124	0	1	0	0
T127	118139	0	0	0
T128	76900	0	0	0
T131	0	24	0	0
T161	0	57	0	0
T173	99491	0	0	0
T252	0	8	0	0
T253	0	1	0	0
T255	0	2	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1592125073	1312	0	0
T38	326459	20	0	0
T47	120797	0	0	0
T56	687582	4	0	0
T57	20398	0	0	0
T58	238329	0	0	0
T73	0	1	0	0
T83	235240	0	0	0
T124	0	1	0	0
T131	0	14	0	0
T157	0	5	0	0
T161	0	15	0	0
T184	73747	0	0	0
T215	204581	0	0	0
T223	21451	0	0	0
T224	375657	0	0	0
T252	0	24	0	0
T253	0	9	0	0
T256	0	1	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1592125073	4304	0	0
T36	406774	0	0	0
T38	0	147	0	0
T43	278507	0	0	0
T44	736306	0	0	0
T55	36997	60	0	0
T56	0	53	0	0
T57	0	42	0	0
T58	0	57	0	0
T61	136185	0	0	0
T62	107117	0	0	0
T63	250584	0	0	0
T73	0	1	0	0
T133	101948	0	0	0
T134	314949	0	0	0
T161	0	100	0	0
T181	53998	0	0	0
T252	0	14	0	0
T257	0	57	0	0
T258	0	49	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1592125073	4792	0	0
T8	107590	0	0	0
T9	788831	0	0	0
T10	210703	0	0	0
T19	246321	73	0	0
T29	118201	0	0	0
T33	84701	0	0	0
T38	0	150	0	0
T40	319347	0	0	0
T41	296910	0	0	0
T48	101524	0	0	0
T52	57141	0	0	0
T56	0	9	0	0
T60	0	37	0	0
T73	0	5	0	0
T131	0	164	0	0
T146	0	82	0	0
T161	0	98	0	0
T252	0	6	0	0
T259	0	85	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1592125073	3543	0	0
T8	107590	0	0	0
T9	788831	0	0	0
T10	210703	0	0	0
T19	246321	83	0	0
T29	118201	0	0	0
T33	84701	0	0	0
T38	0	138	0	0
T40	319347	0	0	0
T41	296910	0	0	0
T48	101524	0	0	0
T52	57141	0	0	0
T56	0	6	0	0
T60	0	57	0	0
T73	0	11	0	0
T131	0	149	0	0
T146	0	46	0	0
T161	0	97	0	0
T252	0	22	0	0
T259	0	64	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1592125073	3771	0	0
T8	107590	0	0	0
T9	788831	0	0	0
T10	210703	0	0	0
T19	246321	69	0	0
T29	118201	0	0	0
T33	84701	0	0	0
T38	0	177	0	0
T40	319347	0	0	0
T41	296910	0	0	0
T48	101524	0	0	0
T52	57141	0	0	0
T56	0	10	0	0
T60	0	52	0	0
T73	0	20	0	0
T131	0	175	0	0
T146	0	70	0	0
T161	0	97	0	0
T252	0	23	0	0
T259	0	69	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1592125073	1530	0	0
T38	326459	30	0	0
T47	120797	0	0	0
T56	687582	19	0	0
T57	20398	0	0	0
T58	238329	0	0	0
T73	0	11	0	0
T83	235240	0	0	0
T101	0	23	0	0
T124	0	5	0	0
T131	0	22	0	0
T157	0	10	0	0
T161	0	41	0	0
T184	73747	0	0	0
T215	204581	0	0	0
T223	21451	0	0	0
T224	375657	0	0	0
T252	0	13	0	0
T253	0	10	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1592125073	1350	0	0
T9	788831	0	0	0
T10	210703	0	0	0
T11	776625	0	0	0
T12	29688	0	0	0
T29	118201	0	0	0
T30	63246	0	0	0
T33	84701	8	0	0
T38	0	17	0	0
T39	0	8	0	0
T41	296910	0	0	0
T49	0	2	0	0
T52	57141	0	0	0
T53	29960	0	0	0
T56	0	3	0	0
T73	0	34	0	0
T131	0	13	0	0
T145	0	2	0	0
T161	0	30	0	0
T252	0	13	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1592125073	1346	0	0
T9	788831	0	0	0
T10	210703	0	0	0
T11	776625	0	0	0
T12	29688	0	0	0
T29	118201	0	0	0
T30	63246	0	0	0
T33	84701	4	0	0
T38	0	21	0	0
T39	0	2	0	0
T41	296910	0	0	0
T49	0	5	0	0
T52	57141	0	0	0
T53	29960	0	0	0
T56	0	8	0	0
T73	0	35	0	0
T117	0	3	0	0
T145	0	3	0	0
T161	0	37	0	0
T252	0	24	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1592125073	1390	0	0
T9	788831	0	0	0
T10	210703	0	0	0
T11	776625	0	0	0
T12	29688	0	0	0
T29	118201	0	0	0
T30	63246	0	0	0
T33	84701	9	0	0
T38	0	28	0	0
T39	0	8	0	0
T41	296910	0	0	0
T49	0	2	0	0
T52	57141	0	0	0
T53	29960	0	0	0
T56	0	3	0	0
T73	0	17	0	0
T111	0	3	0	0
T131	0	16	0	0
T161	0	28	0	0
T252	0	11	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1592125073	1354	0	0
T9	788831	0	0	0
T10	210703	0	0	0
T11	776625	0	0	0
T12	29688	0	0	0
T29	118201	0	0	0
T30	63246	0	0	0
T33	84701	3	0	0
T38	0	38	0	0
T39	0	1	0	0
T41	296910	0	0	0
T49	0	3	0	0
T52	57141	0	0	0
T53	29960	0	0	0
T56	0	8	0	0
T73	0	24	0	0
T117	0	6	0	0
T131	0	8	0	0
T161	0	27	0	0
T252	0	16	0	0