Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T13,T26,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T13,T26,T27

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T26,T27,T49

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T26,T27
1	0	Covered	T4,T5,T1
1	1	Covered	T13,T26,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T26,T27,T49
0	1	Covered	T91
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T26,T27,T49
0	1	Covered	T26,T27,T49
1	0	Covered	T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T26,T27,T49
1	-	Covered	T26,T27,T49

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T13,T26,T27
DetectSt	168	Covered	T26,T27,T49
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T26,T27,T49

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T26,T27,T49
DebounceSt->IdleSt	163	Covered	T13,T48,T38
DetectSt->IdleSt	186	Covered	T91
DetectSt->StableSt	191	Covered	T26,T27,T49
IdleSt->DebounceSt	148	Covered	T13,T26,T27
StableSt->IdleSt	206	Covered	T26,T27,T49

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T26,T27
0	1	Covered	T13,T26,T27
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T49
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T26,T27
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T38
DebounceSt	-	0	1	1	-	-	-	Covered	T26,T27,T49
DebounceSt	-	0	1	0	-	-	-	Covered	T13,T48,T44
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T26,T27
DetectSt	-	-	-	-	1	-	-	Covered	T91
DetectSt	-	-	-	-	0	1	-	Covered	T26,T27,T49
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T26,T27,T49
StableSt	-	-	-	-	-	-	0	Covered	T26,T27,T49
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10916984	254	0	0
CntIncr_A	10916984	146760	0	0
CntNoWrap_A	10916984	10231976	0	0
DetectStDropOut_A	10916984	1	0	0
DetectedOut_A	10916984	789	0	0
DetectedPulseOut_A	10916984	112	0	0
DisabledIdleSt_A	10916984	10079429	0	0
DisabledNoDetection_A	10916984	10081847	0	0
EnterDebounceSt_A	10916984	143	0	0
EnterDetectSt_A	10916984	113	0	0
EnterStableSt_A	10916984	112	0	0
PulseIsPulse_A	10916984	112	0	0
StayInStableSt	10916984	677	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	10916984	7059	0	0
gen_low_level_sva.LowLevelEvent_A	10916984	10234697	0	0
gen_not_sticky_sva.StableStDropOut_A	10916984	111	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	254	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	1	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T26	0	2	0	0
T27	0	4	0	0
T28	11763	0	0	0
T38	0	1	0	0
T43	0	6	0	0
T44	0	3	0	0
T46	2675	0	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	2	0	0
T52	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	146760	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	54	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T26	0	13	0	0
T27	0	60	0	0
T28	11763	0	0	0
T38	0	39	0	0
T43	0	149	0	0
T44	0	71	0	0
T46	2675	0	0	0
T48	0	111	0	0
T49	0	99	0	0
T50	0	13	0	0
T52	0	6895	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10231976	0	0
T1	15812	15381	0	0
T2	136155	134552	0	0
T3	23948	21508	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	15579	0	0
T13	2041	437	0	0
T14	502	101	0	0
T15	5417	5016	0	0
T16	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	1	0	0
T91	8616	1	0	0
T99	974957	0	0	0
T100	421	0	0	0
T101	930671	0	0	0
T102	443	0	0	0
T103	524	0	0	0
T104	650	0	0	0
T105	1209	0	0	0
T106	501	0	0	0
T107	415	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	789	0	0
T22	190347	0	0	0
T26	584	4	0	0
T27	0	12	0	0
T33	10931	0	0	0
T34	2781	0	0	0
T35	625	0	0	0
T43	0	9	0	0
T44	0	13	0	0
T45	8816	0	0	0
T49	0	12	0	0
T50	0	9	0	0
T52	0	10	0	0
T72	5667	0	0	0
T109	0	13	0	0
T110	0	9	0	0
T111	0	10	0	0
T112	406	0	0	0
T113	444	0	0	0
T114	422	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	112	0	0
T22	190347	0	0	0
T26	584	1	0	0
T27	0	2	0	0
T33	10931	0	0	0
T34	2781	0	0	0
T35	625	0	0	0
T43	0	3	0	0
T44	0	1	0	0
T45	8816	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T52	0	1	0	0
T72	5667	0	0	0
T109	0	2	0	0
T110	0	1	0	0
T111	0	1	0	0
T112	406	0	0	0
T113	444	0	0	0
T114	422	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10079429	0	0
T1	15812	15381	0	0
T2	136155	134552	0	0
T3	23948	21508	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	15579	0	0
T13	2041	349	0	0
T14	502	101	0	0
T15	5417	5016	0	0
T16	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10081847	0	0
T1	15812	15387	0	0
T2	136155	134555	0	0
T3	23948	21518	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	351	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	143	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	1	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T26	0	1	0	0
T27	0	2	0	0
T28	11763	0	0	0
T38	0	1	0	0
T43	0	3	0	0
T44	0	2	0	0
T46	2675	0	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	0	1	0	0
T52	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	113	0	0
T22	190347	0	0	0
T26	584	1	0	0
T27	0	2	0	0
T33	10931	0	0	0
T34	2781	0	0	0
T35	625	0	0	0
T43	0	3	0	0
T44	0	1	0	0
T45	8816	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T52	0	1	0	0
T72	5667	0	0	0
T109	0	2	0	0
T110	0	1	0	0
T111	0	1	0	0
T112	406	0	0	0
T113	444	0	0	0
T114	422	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	112	0	0
T22	190347	0	0	0
T26	584	1	0	0
T27	0	2	0	0
T33	10931	0	0	0
T34	2781	0	0	0
T35	625	0	0	0
T43	0	3	0	0
T44	0	1	0	0
T45	8816	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T52	0	1	0	0
T72	5667	0	0	0
T109	0	2	0	0
T110	0	1	0	0
T111	0	1	0	0
T112	406	0	0	0
T113	444	0	0	0
T114	422	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	112	0	0
T22	190347	0	0	0
T26	584	1	0	0
T27	0	2	0	0
T33	10931	0	0	0
T34	2781	0	0	0
T35	625	0	0	0
T43	0	3	0	0
T44	0	1	0	0
T45	8816	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T52	0	1	0	0
T72	5667	0	0	0
T109	0	2	0	0
T110	0	1	0	0
T111	0	1	0	0
T112	406	0	0	0
T113	444	0	0	0
T114	422	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	677	0	0
T22	190347	0	0	0
T26	584	3	0	0
T27	0	10	0	0
T33	10931	0	0	0
T34	2781	0	0	0
T35	625	0	0	0
T43	0	6	0	0
T44	0	12	0	0
T45	8816	0	0	0
T49	0	11	0	0
T50	0	8	0	0
T52	0	9	0	0
T72	5667	0	0	0
T109	0	11	0	0
T110	0	8	0	0
T111	0	9	0	0
T112	406	0	0	0
T113	444	0	0	0
T114	422	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	7059	0	0
T1	15812	11	0	0
T2	136155	5	0	0
T3	23948	25	0	0
T4	3530	18	0	0
T5	422	1	0	0
T6	16014	13	0	0
T13	2041	12	0	0
T14	502	5	0	0
T15	5417	30	0	0
T16	505	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10234697	0	0
T1	15812	15387	0	0
T2	136155	134555	0	0
T3	23948	21518	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	111	0	0
T22	190347	0	0	0
T26	584	1	0	0
T27	0	2	0	0
T33	10931	0	0	0
T34	2781	0	0	0
T35	625	0	0	0
T43	0	3	0	0
T44	0	1	0	0
T45	8816	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T52	0	1	0	0
T72	5667	0	0	0
T109	0	2	0	0
T110	0	1	0	0
T111	0	1	0	0
T112	406	0	0	0
T113	444	0	0	0
T114	422	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T21,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T3,T21,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T21,T22,T59

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T21,T22
1	0	Covered	T4,T5,T1
1	1	Covered	T3,T21,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T21,T22,T59
0	1	Covered	T81,T82,T83
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T21,T22,T59
0	1	Unreachable
1	0	Covered	T21,T22,T59

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T21,T22
DetectSt	168	Covered	T21,T22,T59
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T21,T22,T59

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T21,T22,T59
DebounceSt->IdleSt	163	Covered	T3,T60,T62
DetectSt->IdleSt	186	Covered	T81,T82,T83
DetectSt->StableSt	191	Covered	T21,T22,T59
IdleSt->DebounceSt	148	Covered	T3,T21,T22
StableSt->IdleSt	206	Covered	T21,T22,T59

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T21,T22
0	1	Covered	T3,T21,T22
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T59
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T21,T22
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T38,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T21,T22,T59
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T60,T62
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T21,T22
DetectSt	-	-	-	-	1	-	-	Covered	T81,T82,T83
DetectSt	-	-	-	-	0	1	-	Covered	T21,T22,T59
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T21,T22,T59
StableSt	-	-	-	-	-	-	0	Covered	T21,T22,T59
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10916984	202	0	0
CntIncr_A	10916984	283342	0	0
CntNoWrap_A	10916984	10232028	0	0
DetectStDropOut_A	10916984	14	0	0
DetectedOut_A	10916984	776067	0	0
DetectedPulseOut_A	10916984	56	0	0
DisabledIdleSt_A	10916984	6508279	0	0
DisabledNoDetection_A	10916984	6510743	0	0
EnterDebounceSt_A	10916984	132	0	0
EnterDetectSt_A	10916984	70	0	0
EnterStableSt_A	10916984	56	0	0
PulseIsPulse_A	10916984	56	0	0
StayInStableSt	10916984	776011	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	10916984	7059	0	0
gen_low_level_sva.LowLevelEvent_A	10916984	10234697	0	0
gen_sticky_sva.StableStDropOut_A	10916984	2569416	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	202	0	0
T3	23948	3	0	0
T6	16014	0	0	0
T7	907	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	2	0	0
T22	0	2	0	0
T28	11763	0	0	0
T38	0	2	0	0
T46	2675	0	0	0
T48	0	1	0	0
T53	424	0	0	0
T54	751	0	0	0
T59	0	4	0	0
T60	0	5	0	0
T61	0	4	0	0
T62	0	5	0	0
T74	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	283342	0	0
T3	23948	117	0	0
T6	16014	0	0	0
T7	907	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	61	0	0
T22	0	30	0	0
T28	11763	0	0	0
T38	0	13	0	0
T46	2675	0	0	0
T48	0	87	0	0
T53	424	0	0	0
T54	751	0	0	0
T59	0	130	0	0
T60	0	185	0	0
T61	0	68	0	0
T62	0	295	0	0
T74	0	64	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10232028	0	0
T1	15812	15381	0	0
T2	136155	134552	0	0
T3	23948	21505	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	15579	0	0
T13	2041	438	0	0
T14	502	101	0	0
T15	5417	5016	0	0
T16	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	14	0	0
T81	1333	1	0	0
T82	0	2	0	0
T83	0	4	0	0
T116	10266	0	0	0
T120	0	1	0	0
T121	0	2	0	0
T122	0	1	0	0
T123	0	2	0	0
T124	0	1	0	0
T125	13494	0	0	0
T126	694	0	0	0
T127	402	0	0	0
T128	4870	0	0	0
T129	523	0	0	0
T130	413	0	0	0
T131	548	0	0	0
T132	424	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	776067	0	0
T21	12771	289	0	0
T22	190347	40	0	0
T26	584	0	0	0
T31	17816	0	0	0
T34	2781	0	0	0
T35	625	0	0	0
T36	526	0	0	0
T59	0	885	0	0
T61	0	225	0	0
T72	5667	0	0	0
T74	0	35	0	0
T82	0	13	0	0
T83	0	77	0	0
T112	406	0	0	0
T113	444	0	0	0
T116	0	28	0	0
T117	0	433	0	0
T118	0	26	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	56	0	0
T21	12771	1	0	0
T22	190347	1	0	0
T26	584	0	0	0
T31	17816	0	0	0
T34	2781	0	0	0
T35	625	0	0	0
T36	526	0	0	0
T59	0	2	0	0
T61	0	2	0	0
T72	5667	0	0	0
T74	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T112	406	0	0	0
T113	444	0	0	0
T116	0	1	0	0
T117	0	2	0	0
T118	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	6508279	0	0
T1	15812	15381	0	0
T2	136155	134552	0	0
T3	23948	21050	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	15579	0	0
T13	2041	438	0	0
T14	502	101	0	0
T15	5417	5016	0	0
T16	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	6510743	0	0
T1	15812	15387	0	0
T2	136155	134555	0	0
T3	23948	21060	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	132	0	0
T3	23948	3	0	0
T6	16014	0	0	0
T7	907	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	1	0	0
T22	0	1	0	0
T28	11763	0	0	0
T38	0	2	0	0
T46	2675	0	0	0
T48	0	1	0	0
T53	424	0	0	0
T54	751	0	0	0
T59	0	2	0	0
T60	0	5	0	0
T61	0	2	0	0
T62	0	5	0	0
T74	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	70	0	0
T21	12771	1	0	0
T22	190347	1	0	0
T26	584	0	0	0
T31	17816	0	0	0
T34	2781	0	0	0
T35	625	0	0	0
T36	526	0	0	0
T59	0	2	0	0
T61	0	2	0	0
T72	5667	0	0	0
T74	0	1	0	0
T81	0	1	0	0
T82	0	3	0	0
T83	0	5	0	0
T112	406	0	0	0
T113	444	0	0	0
T116	0	1	0	0
T117	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	56	0	0
T21	12771	1	0	0
T22	190347	1	0	0
T26	584	0	0	0
T31	17816	0	0	0
T34	2781	0	0	0
T35	625	0	0	0
T36	526	0	0	0
T59	0	2	0	0
T61	0	2	0	0
T72	5667	0	0	0
T74	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T112	406	0	0	0
T113	444	0	0	0
T116	0	1	0	0
T117	0	2	0	0
T118	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	56	0	0
T21	12771	1	0	0
T22	190347	1	0	0
T26	584	0	0	0
T31	17816	0	0	0
T34	2781	0	0	0
T35	625	0	0	0
T36	526	0	0	0
T59	0	2	0	0
T61	0	2	0	0
T72	5667	0	0	0
T74	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T112	406	0	0	0
T113	444	0	0	0
T116	0	1	0	0
T117	0	2	0	0
T118	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	776011	0	0
T21	12771	288	0	0
T22	190347	39	0	0
T26	584	0	0	0
T31	17816	0	0	0
T34	2781	0	0	0
T35	625	0	0	0
T36	526	0	0	0
T59	0	883	0	0
T61	0	223	0	0
T72	5667	0	0	0
T74	0	34	0	0
T82	0	12	0	0
T83	0	76	0	0
T112	406	0	0	0
T113	444	0	0	0
T116	0	27	0	0
T117	0	431	0	0
T118	0	25	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	7059	0	0
T1	15812	11	0	0
T2	136155	5	0	0
T3	23948	25	0	0
T4	3530	18	0	0
T5	422	1	0	0
T6	16014	13	0	0
T13	2041	12	0	0
T14	502	5	0	0
T15	5417	30	0	0
T16	505	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10234697	0	0
T1	15812	15387	0	0
T2	136155	134555	0	0
T3	23948	21518	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	2569416	0	0
T21	12771	87	0	0
T22	190347	126538	0	0
T26	584	0	0	0
T31	17816	0	0	0
T34	2781	0	0	0
T35	625	0	0	0
T36	526	0	0	0
T59	0	181	0	0
T61	0	222	0	0
T72	5667	0	0	0
T74	0	27	0	0
T82	0	94	0	0
T83	0	106	0	0
T112	406	0	0	0
T113	444	0	0	0
T116	0	228	0	0
T117	0	538542	0	0
T118	0	214	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T2
1	1	Covered	T4,T5,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T21,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T3,T21,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T21,T22,T59

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T21,T22
1	0	Covered	T4,T5,T2
1	1	Covered	T3,T21,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T21,T22,T59
0	1	Covered	T21,T59,T60
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T21,T22,T59
0	1	Unreachable
1	0	Covered	T21,T22,T59

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T21,T22
DetectSt	168	Covered	T21,T22,T59
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T21,T22,T59

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T21,T22,T59
DebounceSt->IdleSt	163	Covered	T3,T59,T48
DetectSt->IdleSt	186	Covered	T21,T59,T60
DetectSt->StableSt	191	Covered	T21,T22,T59
IdleSt->DebounceSt	148	Covered	T3,T21,T22
StableSt->IdleSt	206	Covered	T21,T22,T59

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T21,T22
0	1	Covered	T3,T21,T22
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T59
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T21,T22
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T38,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T21,T22,T59
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T59,T48
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T21,T22
DetectSt	-	-	-	-	1	-	-	Covered	T21,T59,T60
DetectSt	-	-	-	-	0	1	-	Covered	T21,T22,T59
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T21,T22,T59
StableSt	-	-	-	-	-	-	0	Covered	T21,T22,T59
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10916984	238	0	0
CntIncr_A	10916984	299483	0	0
CntNoWrap_A	10916984	10231992	0	0
DetectStDropOut_A	10916984	30	0	0
DetectedOut_A	10916984	9551	0	0
DetectedPulseOut_A	10916984	55	0	0
DisabledIdleSt_A	10916984	6508279	0	0
DisabledNoDetection_A	10916984	6510743	0	0
EnterDebounceSt_A	10916984	153	0	0
EnterDetectSt_A	10916984	85	0	0
EnterStableSt_A	10916984	55	0	0
PulseIsPulse_A	10916984	55	0	0
StayInStableSt	10916984	9496	0	0
gen_high_level_sva.HighLevelEvent_A	10916984	10234697	0	0
gen_sticky_sva.StableStDropOut_A	10916984	2423879	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	238	0	0
T3	23948	3	0	0
T6	16014	0	0	0
T7	907	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	8	0	0
T22	0	2	0	0
T28	11763	0	0	0
T38	0	2	0	0
T46	2675	0	0	0
T48	0	1	0	0
T53	424	0	0	0
T54	751	0	0	0
T59	0	10	0	0
T60	0	6	0	0
T61	0	4	0	0
T62	0	8	0	0
T74	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	299483	0	0
T3	23948	180	0	0
T6	16014	0	0	0
T7	907	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	164	0	0
T22	0	26	0	0
T28	11763	0	0	0
T38	0	15	0	0
T46	2675	0	0	0
T48	0	84	0	0
T53	424	0	0	0
T54	751	0	0	0
T59	0	594	0	0
T60	0	150	0	0
T61	0	146	0	0
T62	0	204	0	0
T74	0	30	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10231992	0	0
T1	15812	15381	0	0
T2	136155	134552	0	0
T3	23948	21505	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	15579	0	0
T13	2041	438	0	0
T14	502	101	0	0
T15	5417	5016	0	0
T16	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	30	0	0
T21	12771	3	0	0
T22	190347	0	0	0
T26	584	0	0	0
T31	17816	0	0	0
T34	2781	0	0	0
T35	625	0	0	0
T36	526	0	0	0
T59	0	3	0	0
T60	0	2	0	0
T62	0	3	0	0
T72	5667	0	0	0
T81	0	1	0	0
T82	0	1	0	0
T98	0	2	0	0
T112	406	0	0	0
T113	444	0	0	0
T122	0	1	0	0
T133	0	2	0	0
T134	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	9551	0	0
T21	12771	44	0	0
T22	190347	43	0	0
T26	584	0	0	0
T31	17816	0	0	0
T34	2781	0	0	0
T35	625	0	0	0
T36	526	0	0	0
T59	0	301	0	0
T60	0	104	0	0
T61	0	260	0	0
T62	0	53	0	0
T72	5667	0	0	0
T74	0	27	0	0
T76	0	68	0	0
T82	0	120	0	0
T112	406	0	0	0
T113	444	0	0	0
T119	0	24	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	55	0	0
T21	12771	1	0	0
T22	190347	1	0	0
T26	584	0	0	0
T31	17816	0	0	0
T34	2781	0	0	0
T35	625	0	0	0
T36	526	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	1	0	0
T72	5667	0	0	0
T74	0	1	0	0
T76	0	1	0	0
T82	0	2	0	0
T112	406	0	0	0
T113	444	0	0	0
T119	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	6508279	0	0
T1	15812	15381	0	0
T2	136155	134552	0	0
T3	23948	21050	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	15579	0	0
T13	2041	438	0	0
T14	502	101	0	0
T15	5417	5016	0	0
T16	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	6510743	0	0
T1	15812	15387	0	0
T2	136155	134555	0	0
T3	23948	21060	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	153	0	0
T3	23948	3	0	0
T6	16014	0	0	0
T7	907	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	4	0	0
T22	0	1	0	0
T28	11763	0	0	0
T38	0	2	0	0
T46	2675	0	0	0
T48	0	1	0	0
T53	424	0	0	0
T54	751	0	0	0
T59	0	6	0	0
T60	0	3	0	0
T61	0	2	0	0
T62	0	4	0	0
T74	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	85	0	0
T21	12771	4	0	0
T22	190347	1	0	0
T26	584	0	0	0
T31	17816	0	0	0
T34	2781	0	0	0
T35	625	0	0	0
T36	526	0	0	0
T59	0	4	0	0
T60	0	3	0	0
T61	0	2	0	0
T62	0	4	0	0
T72	5667	0	0	0
T74	0	1	0	0
T76	0	1	0	0
T81	0	1	0	0
T82	0	3	0	0
T112	406	0	0	0
T113	444	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	55	0	0
T21	12771	1	0	0
T22	190347	1	0	0
T26	584	0	0	0
T31	17816	0	0	0
T34	2781	0	0	0
T35	625	0	0	0
T36	526	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	1	0	0
T72	5667	0	0	0
T74	0	1	0	0
T76	0	1	0	0
T82	0	2	0	0
T112	406	0	0	0
T113	444	0	0	0
T119	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	55	0	0
T21	12771	1	0	0
T22	190347	1	0	0
T26	584	0	0	0
T31	17816	0	0	0
T34	2781	0	0	0
T35	625	0	0	0
T36	526	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	1	0	0
T72	5667	0	0	0
T74	0	1	0	0
T76	0	1	0	0
T82	0	2	0	0
T112	406	0	0	0
T113	444	0	0	0
T119	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	9496	0	0
T21	12771	43	0	0
T22	190347	42	0	0
T26	584	0	0	0
T31	17816	0	0	0
T34	2781	0	0	0
T35	625	0	0	0
T36	526	0	0	0
T59	0	300	0	0
T60	0	103	0	0
T61	0	258	0	0
T62	0	52	0	0
T72	5667	0	0	0
T74	0	26	0	0
T76	0	67	0	0
T82	0	118	0	0
T112	406	0	0	0
T113	444	0	0	0
T119	0	23	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10234697	0	0
T1	15812	15387	0	0
T2	136155	134555	0	0
T3	23948	21518	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	2423879	0	0
T21	12771	102	0	0
T22	190347	126534	0	0
T26	584	0	0	0
T31	17816	0	0	0
T34	2781	0	0	0
T35	625	0	0	0
T36	526	0	0	0
T59	0	115	0	0
T60	0	184	0	0
T61	0	124	0	0
T62	0	162	0	0
T72	5667	0	0	0
T74	0	84	0	0
T76	0	87611	0	0
T82	0	482	0	0
T112	406	0	0	0
T113	444	0	0	0
T119	0	25	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T21,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T3,T21,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T21,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T21,T22
1	0	Covered	T4,T5,T1
1	1	Covered	T3,T21,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T21,T59
0	1	Covered	T22,T59,T74
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T21,T59
0	1	Unreachable
1	0	Covered	T3,T21,T59

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T21,T22
DetectSt	168	Covered	T3,T21,T22
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T3,T21,T59

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T21,T22
DebounceSt->IdleSt	163	Covered	T22,T59,T48
DetectSt->IdleSt	186	Covered	T22,T59,T74
DetectSt->StableSt	191	Covered	T3,T21,T59
IdleSt->DebounceSt	148	Covered	T3,T21,T22
StableSt->IdleSt	206	Covered	T3,T21,T59

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T21,T22
0	1	Covered	T3,T21,T22
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T21,T22
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T21,T22
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T38,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T21,T22
DebounceSt	-	0	1	0	-	-	-	Covered	T22,T59,T48
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T21,T22
DetectSt	-	-	-	-	1	-	-	Covered	T22,T59,T74
DetectSt	-	-	-	-	0	1	-	Covered	T3,T21,T59
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T21,T59
StableSt	-	-	-	-	-	-	0	Covered	T3,T21,T59
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10916984	203	0	0
CntIncr_A	10916984	637501	0	0
CntNoWrap_A	10916984	10232027	0	0
DetectStDropOut_A	10916984	12	0	0
DetectedOut_A	10916984	1953068	0	0
DetectedPulseOut_A	10916984	59	0	0
DisabledIdleSt_A	10916984	6508279	0	0
DisabledNoDetection_A	10916984	6510743	0	0
EnterDebounceSt_A	10916984	132	0	0
EnterDetectSt_A	10916984	71	0	0
EnterStableSt_A	10916984	59	0	0
PulseIsPulse_A	10916984	59	0	0
StayInStableSt	10916984	1953009	0	0
gen_high_event_sva.HighLevelEvent_A	10916984	10234697	0	0
gen_high_level_sva.HighLevelEvent_A	10916984	10234697	0	0
gen_sticky_sva.StableStDropOut_A	10916984	151115	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	203	0	0
T3	23948	2	0	0
T6	16014	0	0	0
T7	907	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	2	0	0
T22	0	3	0	0
T28	11763	0	0	0
T38	0	2	0	0
T46	2675	0	0	0
T48	0	1	0	0
T53	424	0	0	0
T54	751	0	0	0
T59	0	13	0	0
T60	0	4	0	0
T61	0	4	0	0
T62	0	2	0	0
T74	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	637501	0	0
T3	23948	61	0	0
T6	16014	0	0	0
T7	907	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	55	0	0
T22	0	126570	0	0
T28	11763	0	0	0
T38	0	13	0	0
T46	2675	0	0	0
T48	0	20	0	0
T53	424	0	0	0
T54	751	0	0	0
T59	0	280	0	0
T60	0	122	0	0
T61	0	124	0	0
T62	0	79	0	0
T74	0	97	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10232027	0	0
T1	15812	15381	0	0
T2	136155	134552	0	0
T3	23948	21506	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	15579	0	0
T13	2041	438	0	0
T14	502	101	0	0
T15	5417	5016	0	0
T16	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	12	0	0
T22	190347	1	0	0
T32	19303	0	0	0
T33	10931	0	0	0
T45	8816	0	0	0
T59	1821	4	0	0
T60	1299	0	0	0
T71	502	0	0	0
T72	5667	0	0	0
T74	0	1	0	0
T114	422	0	0	0
T135	0	1	0	0
T136	0	2	0	0
T137	0	3	0	0
T138	406	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	1953068	0	0
T3	23948	291	0	0
T6	16014	0	0	0
T7	907	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	253	0	0
T28	11763	0	0	0
T46	2675	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T59	0	84	0	0
T60	0	226	0	0
T61	0	259	0	0
T62	0	396	0	0
T81	0	5	0	0
T82	0	289	0	0
T83	0	575	0	0
T116	0	102	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	59	0	0
T3	23948	1	0	0
T6	16014	0	0	0
T7	907	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	1	0	0
T28	11763	0	0	0
T46	2675	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T59	0	2	0	0
T60	0	2	0	0
T61	0	2	0	0
T62	0	1	0	0
T81	0	1	0	0
T82	0	2	0	0
T83	0	2	0	0
T116	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	6508279	0	0
T1	15812	15381	0	0
T2	136155	134552	0	0
T3	23948	21050	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	15579	0	0
T13	2041	438	0	0
T14	502	101	0	0
T15	5417	5016	0	0
T16	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	6510743	0	0
T1	15812	15387	0	0
T2	136155	134555	0	0
T3	23948	21060	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	132	0	0
T3	23948	1	0	0
T6	16014	0	0	0
T7	907	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	1	0	0
T22	0	2	0	0
T28	11763	0	0	0
T38	0	2	0	0
T46	2675	0	0	0
T48	0	1	0	0
T53	424	0	0	0
T54	751	0	0	0
T59	0	7	0	0
T60	0	2	0	0
T61	0	2	0	0
T62	0	1	0	0
T74	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	71	0	0
T3	23948	1	0	0
T6	16014	0	0	0
T7	907	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	1	0	0
T22	0	1	0	0
T28	11763	0	0	0
T46	2675	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T59	0	6	0	0
T60	0	2	0	0
T61	0	2	0	0
T62	0	1	0	0
T74	0	1	0	0
T81	0	1	0	0
T116	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	59	0	0
T3	23948	1	0	0
T6	16014	0	0	0
T7	907	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	1	0	0
T28	11763	0	0	0
T46	2675	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T59	0	2	0	0
T60	0	2	0	0
T61	0	2	0	0
T62	0	1	0	0
T81	0	1	0	0
T82	0	2	0	0
T83	0	2	0	0
T116	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	59	0	0
T3	23948	1	0	0
T6	16014	0	0	0
T7	907	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	1	0	0
T28	11763	0	0	0
T46	2675	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T59	0	2	0	0
T60	0	2	0	0
T61	0	2	0	0
T62	0	1	0	0
T81	0	1	0	0
T82	0	2	0	0
T83	0	2	0	0
T116	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	1953009	0	0
T3	23948	290	0	0
T6	16014	0	0	0
T7	907	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	252	0	0
T28	11763	0	0	0
T46	2675	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T59	0	82	0	0
T60	0	224	0	0
T61	0	257	0	0
T62	0	395	0	0
T81	0	4	0	0
T82	0	287	0	0
T83	0	573	0	0
T116	0	101	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10234697	0	0
T1	15812	15387	0	0
T2	136155	134555	0	0
T3	23948	21518	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10234697	0	0
T1	15812	15387	0	0
T2	136155	134555	0	0
T3	23948	21518	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	151115	0	0
T3	23948	100	0	0
T6	16014	0	0	0
T7	907	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	146	0	0
T28	11763	0	0	0
T46	2675	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T59	0	393	0	0
T60	0	250	0	0
T61	0	156	0	0
T62	0	188	0	0
T81	0	64	0	0
T82	0	385	0	0
T83	0	163	0	0
T116	0	77	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T43,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T43,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T43,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T11
1	0	Covered	T4,T5,T1
1	1	Covered	T2,T43,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T43,T38
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T43,T38
0	1	Covered	T2,T44,T80
1	0	Covered	T38,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T43,T38
1	-	Covered	T2,T44,T80

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T43,T38
DetectSt	168	Covered	T2,T43,T38
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T43,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T43,T38
DebounceSt->IdleSt	163	Covered	T139,T136,T140
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T2,T43,T38
IdleSt->DebounceSt	148	Covered	T2,T43,T38
StableSt->IdleSt	206	Covered	T2,T38,T44

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T43,T38
0	1	Covered	T2,T43,T38
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T43,T38
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T43,T38
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T43,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T139,T136,T140
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T43,T38
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T2,T43,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T38,T44
StableSt	-	-	-	-	-	-	0	Covered	T2,T43,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10916984	117	0	0
CntIncr_A	10916984	45183	0	0
CntNoWrap_A	10916984	10232113	0	0
DetectStDropOut_A	10916984	0	0	0
DetectedOut_A	10916984	29505	0	0
DetectedPulseOut_A	10916984	57	0	0
DisabledIdleSt_A	10916984	9742209	0	0
DisabledNoDetection_A	10916984	9744597	0	0
EnterDebounceSt_A	10916984	60	0	0
EnterDetectSt_A	10916984	57	0	0
EnterStableSt_A	10916984	57	0	0
PulseIsPulse_A	10916984	57	0	0
StayInStableSt	10916984	29416	0	0
gen_high_level_sva.HighLevelEvent_A	10916984	10234697	0	0
gen_not_sticky_sva.StableStDropOut_A	10916984	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	117	0	0
T2	136155	4	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T38	0	2	0	0
T43	0	2	0	0
T44	0	10	0	0
T46	2675	0	0	0
T76	0	2	0	0
T80	0	2	0	0
T126	0	2	0	0
T141	0	2	0	0
T142	0	2	0	0
T143	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	45183	0	0
T2	136155	42178	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T38	0	20	0	0
T43	0	72	0	0
T44	0	274	0	0
T46	2675	0	0	0
T76	0	99	0	0
T80	0	64	0	0
T126	0	37	0	0
T141	0	60	0	0
T142	0	87	0	0
T143	0	50	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10232113	0	0
T1	15812	15381	0	0
T2	136155	134548	0	0
T3	23948	21508	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	15579	0	0
T13	2041	438	0	0
T14	502	101	0	0
T15	5417	5016	0	0
T16	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	29505	0	0
T2	136155	24585	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T38	0	26	0	0
T43	0	167	0	0
T44	0	670	0	0
T46	2675	0	0	0
T76	0	55	0	0
T80	0	40	0	0
T126	0	98	0	0
T141	0	211	0	0
T142	0	260	0	0
T143	0	20	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	57	0	0
T2	136155	2	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T38	0	1	0	0
T43	0	1	0	0
T44	0	5	0	0
T46	2675	0	0	0
T76	0	1	0	0
T80	0	1	0	0
T126	0	1	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	9742209	0	0
T1	15812	15381	0	0
T2	136155	128	0	0
T3	23948	21508	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	15579	0	0
T13	2041	438	0	0
T14	502	101	0	0
T15	5417	5016	0	0
T16	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	9744597	0	0
T1	15812	15387	0	0
T2	136155	130	0	0
T3	23948	21518	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	60	0	0
T2	136155	2	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T38	0	1	0	0
T43	0	1	0	0
T44	0	5	0	0
T46	2675	0	0	0
T76	0	1	0	0
T80	0	1	0	0
T126	0	1	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	57	0	0
T2	136155	2	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T38	0	1	0	0
T43	0	1	0	0
T44	0	5	0	0
T46	2675	0	0	0
T76	0	1	0	0
T80	0	1	0	0
T126	0	1	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	57	0	0
T2	136155	2	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T38	0	1	0	0
T43	0	1	0	0
T44	0	5	0	0
T46	2675	0	0	0
T76	0	1	0	0
T80	0	1	0	0
T126	0	1	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	57	0	0
T2	136155	2	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T38	0	1	0	0
T43	0	1	0	0
T44	0	5	0	0
T46	2675	0	0	0
T76	0	1	0	0
T80	0	1	0	0
T126	0	1	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	29416	0	0
T2	136155	24583	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T38	0	25	0	0
T43	0	165	0	0
T44	0	661	0	0
T46	2675	0	0	0
T76	0	53	0	0
T80	0	39	0	0
T126	0	96	0	0
T141	0	209	0	0
T142	0	258	0	0
T143	0	19	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10234697	0	0
T1	15812	15387	0	0
T2	136155	134555	0	0
T3	23948	21518	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	23	0	0
T2	136155	2	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T44	0	1	0	0
T46	2675	0	0	0
T80	0	1	0	0
T94	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T9,T34,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T9,T34,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T9,T34,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T34,T35
1	0	Covered	T4,T5,T1
1	1	Covered	T9,T34,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T34,T35
0	1	Covered	T149,T150,T151
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T34,T35
0	1	Covered	T41,T39,T44
1	0	Covered	T38,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T34,T35
1	-	Covered	T41,T39,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T34,T35
DetectSt	168	Covered	T9,T34,T35
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T9,T34,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T34,T35
DebounceSt->IdleSt	163	Covered	T152
DetectSt->IdleSt	186	Covered	T149,T150,T151
DetectSt->StableSt	191	Covered	T9,T34,T35
IdleSt->DebounceSt	148	Covered	T9,T34,T35
StableSt->IdleSt	206	Covered	T9,T34,T27

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T34,T35
0	1	Covered	T9,T34,T35
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T34,T35
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T34,T35
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T34,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T152
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T34,T35
DetectSt	-	-	-	-	1	-	-	Covered	T149,T150,T151
DetectSt	-	-	-	-	0	1	-	Covered	T9,T34,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T41,T38,T39
StableSt	-	-	-	-	-	-	0	Covered	T9,T34,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10916984	147	0	0
CntIncr_A	10916984	3876	0	0
CntNoWrap_A	10916984	10232083	0	0
DetectStDropOut_A	10916984	3	0	0
DetectedOut_A	10916984	5917	0	0
DetectedPulseOut_A	10916984	70	0	0
DisabledIdleSt_A	10916984	10213051	0	0
DisabledNoDetection_A	10916984	10215460	0	0
EnterDebounceSt_A	10916984	74	0	0
EnterDetectSt_A	10916984	73	0	0
EnterStableSt_A	10916984	70	0	0
PulseIsPulse_A	10916984	70	0	0
StayInStableSt	10916984	5815	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	10916984	2780	0	0
gen_low_level_sva.LowLevelEvent_A	10916984	10234697	0	0
gen_not_sticky_sva.StableStDropOut_A	10916984	36	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	147	0	0
T9	123429	2	0	0
T10	15620	0	0	0
T11	653	0	0	0
T12	33816	0	0	0
T24	498	0	0	0
T25	493	0	0	0
T27	0	2	0	0
T34	0	2	0	0
T35	0	2	0	0
T37	0	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	547	0	0	0
T41	0	4	0	0
T42	0	2	0	0
T44	0	6	0	0
T69	896	0	0	0
T70	411	0	0	0
T153	402	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	3876	0	0
T9	123429	45	0	0
T10	15620	0	0	0
T11	653	0	0	0
T12	33816	0	0	0
T24	498	0	0	0
T25	493	0	0	0
T27	0	90	0	0
T34	0	11	0	0
T35	0	22	0	0
T37	0	77	0	0
T38	0	20	0	0
T39	0	90	0	0
T40	547	0	0	0
T41	0	138	0	0
T42	0	43	0	0
T44	0	176	0	0
T69	896	0	0	0
T70	411	0	0	0
T153	402	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10232083	0	0
T1	15812	15381	0	0
T2	136155	134552	0	0
T3	23948	21508	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	15579	0	0
T13	2041	438	0	0
T14	502	101	0	0
T15	5417	5016	0	0
T16	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	3	0	0
T95	29524	0	0	0
T96	14274	0	0	0
T97	33887	0	0	0
T147	12871	0	0	0
T149	22205	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T154	422	0	0	0
T155	990	0	0	0
T156	490	0	0	0
T157	522	0	0	0
T158	523	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	5917	0	0
T9	123429	42	0	0
T10	15620	0	0	0
T11	653	0	0	0
T12	33816	0	0	0
T24	498	0	0	0
T25	493	0	0	0
T27	0	37	0	0
T34	0	115	0	0
T35	0	91	0	0
T37	0	40	0	0
T38	0	26	0	0
T39	0	45	0	0
T40	547	0	0	0
T41	0	165	0	0
T42	0	184	0	0
T44	0	219	0	0
T69	896	0	0	0
T70	411	0	0	0
T153	402	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	70	0	0
T9	123429	1	0	0
T10	15620	0	0	0
T11	653	0	0	0
T12	33816	0	0	0
T24	498	0	0	0
T25	493	0	0	0
T27	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	547	0	0	0
T41	0	2	0	0
T42	0	1	0	0
T44	0	3	0	0
T69	896	0	0	0
T70	411	0	0	0
T153	402	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10213051	0	0
T1	15812	15381	0	0
T2	136155	134552	0	0
T3	23948	21508	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	15579	0	0
T13	2041	438	0	0
T14	502	101	0	0
T15	5417	5016	0	0
T16	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10215460	0	0
T1	15812	15387	0	0
T2	136155	134555	0	0
T3	23948	21518	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	74	0	0
T9	123429	1	0	0
T10	15620	0	0	0
T11	653	0	0	0
T12	33816	0	0	0
T24	498	0	0	0
T25	493	0	0	0
T27	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	547	0	0	0
T41	0	2	0	0
T42	0	1	0	0
T44	0	3	0	0
T69	896	0	0	0
T70	411	0	0	0
T153	402	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	73	0	0
T9	123429	1	0	0
T10	15620	0	0	0
T11	653	0	0	0
T12	33816	0	0	0
T24	498	0	0	0
T25	493	0	0	0
T27	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	547	0	0	0
T41	0	2	0	0
T42	0	1	0	0
T44	0	3	0	0
T69	896	0	0	0
T70	411	0	0	0
T153	402	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	70	0	0
T9	123429	1	0	0
T10	15620	0	0	0
T11	653	0	0	0
T12	33816	0	0	0
T24	498	0	0	0
T25	493	0	0	0
T27	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	547	0	0	0
T41	0	2	0	0
T42	0	1	0	0
T44	0	3	0	0
T69	896	0	0	0
T70	411	0	0	0
T153	402	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	70	0	0
T9	123429	1	0	0
T10	15620	0	0	0
T11	653	0	0	0
T12	33816	0	0	0
T24	498	0	0	0
T25	493	0	0	0
T27	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	547	0	0	0
T41	0	2	0	0
T42	0	1	0	0
T44	0	3	0	0
T69	896	0	0	0
T70	411	0	0	0
T153	402	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	5815	0	0
T9	123429	40	0	0
T10	15620	0	0	0
T11	653	0	0	0
T12	33816	0	0	0
T24	498	0	0	0
T25	493	0	0	0
T27	0	35	0	0
T34	0	113	0	0
T35	0	89	0	0
T37	0	38	0	0
T38	0	25	0	0
T39	0	44	0	0
T40	547	0	0	0
T41	0	162	0	0
T42	0	182	0	0
T44	0	215	0	0
T69	896	0	0	0
T70	411	0	0	0
T153	402	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	2780	0	0
T1	15812	0	0	0
T2	136155	8	0	0
T3	23948	1	0	0
T4	3530	6	0	0
T5	422	1	0	0
T6	16014	0	0	0
T7	0	2	0	0
T13	2041	9	0	0
T14	502	4	0	0
T15	5417	0	0	0
T16	505	5	0	0
T17	0	5	0	0
T53	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10234697	0	0
T1	15812	15387	0	0
T2	136155	134555	0	0
T3	23948	21518	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	36	0	0
T37	638	0	0	0
T39	0	1	0	0
T41	784	1	0	0
T43	3210	0	0	0
T44	0	2	0	0
T52	7455	0	0	0
T65	505	0	0	0
T76	0	1	0	0
T86	5266	0	0	0
T87	5175	0	0	0
T143	0	1	0	0
T159	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0
T164	954	0	0	0
T165	599	0	0	0
T166	32868	0	0	0