Unified Coverage Report :: Module :: sysrst_ctrl_detect

Module : sysrst_ctrl_detect

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.35	100.00	96.30		100.00	95.45	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l	85.00	89.13	90.48		66.67	85.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h	89.69	91.30	90.48		83.33	90.00	93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h	89.69	91.30	90.48		83.33	90.00	93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l	89.77	91.30	90.48		83.33	90.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l	89.77	91.30	90.48		83.33	90.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h	92.41	93.48	95.24		83.33	90.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre	97.99	100.00	94.74		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	LINE
89.77	91.30

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	LINE
85.00	89.13

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	LINE
89.77	91.30

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	LINE
89.69	91.30

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	LINE
92.41	93.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	LINE
89.69	91.30

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	LINE
97.99	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T15
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T3,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T3,T6

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T3,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T3,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T6
0	1	Covered	T1,T3,T8
1	0	Covered	T38,T58

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T6
0	1	Covered	T1,T3,T6
1	0	Covered	T75,T38,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T6
1	-	Covered	T1,T3,T6

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	COND
89.77	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	COND
85.00	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	COND
89.77	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T13,T9,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T13,T9,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T9,T11,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T9,T11
1	0	Covered	T4,T5,T1
1	1	Covered	T13,T9,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T11,T40
0	1	Covered	T34,T44,T76
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T11,T40
0	1	Covered	T26,T35,T27
1	0	Covered	T38,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T11,T40
1	-	Covered	T26,T35,T27

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	COND
97.99	94.74

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T15,T28,T29
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T15,T28,T29

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T15,T28,T29

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T15,T28,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T28,T29
1	0	Covered	T28,T10,T12
1	1	Covered	T15,T28,T29

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T28,T29
0	1	Covered	T15,T29,T10
1	0	Covered	T10,T77,T75

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T10,T12
0	1	Covered	T28,T10,T12
1	0	Covered	T78,T38,T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T28,T10,T12
1	-	Covered	T28,T10,T12

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.67	93.33

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T21,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T21,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T21,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T21,T22
1	0	Covered	T4,T5,T1
1	1	Covered	T3,T21,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T21,T59
0	1	Covered	T22,T59,T74
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T21,T59
0	1	Unreachable
1	0	Covered	T3,T21,T59

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
89.69	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	COND
92.41	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	COND
89.69	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T7,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T7,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T7,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T9
1	0	Covered	T4,T5,T1
1	1	Covered	T2,T7,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T9
0	1	Covered	T34,T27,T80
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T9
0	1	Covered	T2,T21,T35
1	0	Covered	T38,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T7,T9
1	-	Covered	T2,T21,T35

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T2
1	1	Covered	T4,T5,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T21,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T21,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T21,T22,T59

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T21,T22
1	0	Covered	T4,T5,T2
1	1	Covered	T3,T21,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T21,T22,T59
0	1	Covered	T21,T59,T60
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T21,T22,T59
0	1	Unreachable
1	0	Covered	T21,T22,T59

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T21,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T21,T22

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T21,T22,T59

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T21,T22
1	0	Covered	T4,T5,T1
1	1	Covered	T3,T21,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T21,T22,T59
0	1	Covered	T81,T82,T83
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T21,T22,T59
0	1	Unreachable
1	0	Covered	T21,T22,T59

---

FSM Coverage for Module : sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T13,T9,T11
DetectSt	168	Covered	T9,T11,T40
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T9,T11,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T11,T40
DebounceSt->IdleSt	163	Covered	T13,T3,T48
DetectSt->IdleSt	186	Covered	T21,T34,T44
DetectSt->StableSt	191	Covered	T9,T11,T40
IdleSt->DebounceSt	148	Covered	T13,T9,T11
StableSt->IdleSt	206	Covered	T9,T21,T26

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
89.77	90.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
85.00	85.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
89.77	90.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	BRANCH
89.69	90.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
92.41	90.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
89.69	90.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		23	22	95.65
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T13,T9,T11
0	1	Covered	T13,T9,T11
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T40
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T13,T9,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T38,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T11,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T13,T3,T60
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T9,T11
DetectSt	-	-	-	-	1	-	-	Covered	T21,T34,T44
DetectSt	-	-	-	-	0	1	-	Covered	T9,T11,T40
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T6
StableSt	-	-	-	-	-	-	1	Covered	T26,T35,T27
StableSt	-	-	-	-	-	-	0	Covered	T9,T11,T40
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
97.99	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T15,T28
0	1	Covered	T3,T15,T28
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T15,T28
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T3,T15,T28
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T38,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T15,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T22,T45,T59
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T15,T28
DetectSt	-	-	-	-	1	-	-	Covered	T15,T29,T10
DetectSt	-	-	-	-	0	1	-	Covered	T3,T28,T12
DetectSt	-	-	-	-	0	0	-	Covered	T15,T28,T29
StableSt	-	-	-	-	-	-	1	Covered	T3,T28,T12
StableSt	-	-	-	-	-	-	0	Covered	T3,T28,T12
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Module : sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	283841584	18754	0	0
CntIncr_A	283841584	2933123	0	0
CntNoWrap_A	283841584	266019226	0	0
DetectStDropOut_A	283841584	2135	0	0
DetectedOut_A	283841584	3479235	0	0
DetectedPulseOut_A	283841584	6007	0	0
DisabledIdleSt_A	283841584	247379601	0	0
DisabledNoDetection_A	283841584	247439069	0	0
EnterDebounceSt_A	283841584	9738	0	0
EnterDetectSt_A	283841584	9036	0	0
EnterStableSt_A	283841584	6007	0	0
PulseIsPulse_A	283841584	6007	0	0
StayInStableSt	283841584	3472090	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	98252856	53091	0	0
gen_high_event_sva.HighLevelEvent_A	54584920	51173485	0	0
gen_high_level_sva.HighLevelEvent_A	185588728	173989849	0	0
gen_low_level_sva.LowLevelEvent_A	98252856	92112273	0	0
gen_not_sticky_sva.StableStDropOut_A	251090632	4646	0	0
gen_sticky_sva.StableStDropOut_A	32750952	5144410	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	283841584	18754	0	0
T1	63248	4	0	0
T2	544620	0	0	0
T3	119740	14	0	0
T6	144126	4	0	0
T7	8163	0	0	0
T8	0	8	0	0
T9	123429	0	0	0
T10	15620	0	0	0
T11	653	0	0	0
T12	33816	62	0	0
T13	10205	1	0	0
T14	2510	0	0	0
T15	48753	52	0	0
T16	4545	0	0	0
T17	4518	0	0	0
T21	0	5	0	0
T24	498	0	0	0
T26	0	2	0	0
T27	0	4	0	0
T28	58815	30	0	0
T31	0	4	0	0
T38	0	1	0	0
T43	0	6	0	0
T44	0	3	0	0
T46	13375	2	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	2	0	0
T52	0	2	0	0
T53	1696	0	0	0
T54	3004	0	0	0
T55	1608	0	0	0
T69	896	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	283841584	2933123	0	0
T1	63248	241	0	0
T2	544620	0	0	0
T3	119740	539	0	0
T6	144126	216	0	0
T7	8163	0	0	0
T8	0	252	0	0
T9	123429	0	0	0
T10	15620	0	0	0
T11	653	0	0	0
T12	33816	1591	0	0
T13	10205	54	0	0
T14	2510	0	0	0
T15	48753	1459	0	0
T16	4545	0	0	0
T17	4518	0	0	0
T21	0	132	0	0
T24	498	0	0	0
T26	0	13	0	0
T27	0	60	0	0
T28	58815	870	0	0
T31	0	372	0	0
T38	0	39	0	0
T43	0	149	0	0
T44	0	71	0	0
T46	13375	40	0	0
T47	0	20	0	0
T48	0	111	0	0
T49	0	99	0	0
T50	0	13	0	0
T52	0	6895	0	0
T53	1696	0	0	0
T54	3004	0	0	0
T55	1608	0	0	0
T69	896	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	283841584	266019226	0	0
T1	411112	399890	0	0
T2	3540030	3498332	0	0
T3	622648	559145	0	0
T4	91780	39676	0	0
T5	10972	546	0	0
T6	416364	405030	0	0
T13	53066	11387	0	0
T14	13052	2626	0	0
T15	140842	130272	0	0
T16	13130	2704	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	283841584	2135	0	0
T1	15812	2	0	0
T2	136155	0	0	0
T3	23948	0	0	0
T6	32028	0	0	0
T7	1814	0	0	0
T10	0	13	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	10834	26	0	0
T16	1010	0	0	0
T17	1004	0	0	0
T29	0	8	0	0
T38	0	1	0	0
T46	2675	0	0	0
T72	0	20	0	0
T84	0	13	0	0
T85	0	8	0	0
T86	0	17	0	0
T87	0	24	0	0
T88	0	4	0	0
T89	0	7	0	0
T90	0	2	0	0
T91	8616	1	0	0
T92	0	5	0	0
T93	0	2	0	0
T94	0	1	0	0
T95	0	2	0	0
T96	0	4	0	0
T97	0	2	0	0
T98	0	5	0	0
T99	974957	0	0	0
T100	421	0	0	0
T101	930671	0	0	0
T102	443	0	0	0
T103	524	0	0	0
T104	650	0	0	0
T105	1209	0	0	0
T106	501	0	0	0
T107	415	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	283841584	3479235	0	0
T3	23948	231	0	0
T6	16014	38	0	0
T7	907	0	0	0
T8	0	64	0	0
T12	0	3863	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	12	0	0
T22	190347	0	0	0
T26	584	4	0	0
T27	0	16	0	0
T28	23526	2668	0	0
T31	0	38	0	0
T33	10931	134	0	0
T34	2781	0	0	0
T35	625	0	0	0
T43	0	9	0	0
T44	0	13	0	0
T45	8816	177	0	0
T46	2675	0	0	0
T49	0	12	0	0
T50	0	9	0	0
T52	0	10	0	0
T53	848	0	0	0
T54	1502	0	0	0
T55	402	0	0	0
T72	5667	0	0	0
T73	0	2588	0	0
T108	0	72	0	0
T109	0	13	0	0
T110	0	9	0	0
T111	0	10	0	0
T112	406	0	0	0
T113	444	0	0	0
T114	422	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	283841584	6007	0	0
T3	23948	7	0	0
T6	16014	2	0	0
T7	907	0	0	0
T8	0	4	0	0
T12	0	31	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	2	0	0
T22	190347	0	0	0
T26	584	1	0	0
T27	0	3	0	0
T28	23526	15	0	0
T31	0	2	0	0
T33	10931	10	0	0
T34	2781	0	0	0
T35	625	0	0	0
T43	0	3	0	0
T44	0	1	0	0
T45	8816	5	0	0
T46	2675	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T52	0	1	0	0
T53	848	0	0	0
T54	1502	0	0	0
T55	402	0	0	0
T72	5667	0	0	0
T73	0	31	0	0
T108	0	10	0	0
T109	0	2	0	0
T110	0	1	0	0
T111	0	1	0	0
T112	406	0	0	0
T113	444	0	0	0
T114	422	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	283841584	247379601	0	0
T1	411112	386734	0	0
T2	3540030	2557384	0	0
T3	622648	531014	0	0
T4	91780	39676	0	0
T5	10972	546	0	0
T6	416364	391086	0	0
T13	53066	11299	0	0
T14	13052	2626	0	0
T15	140842	118408	0	0
T16	13130	2704	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	283841584	247439069	0	0
T1	411112	386866	0	0
T2	3540030	2557455	0	0
T3	622648	531246	0	0
T4	91780	39780	0	0
T5	10972	572	0	0
T6	416364	391218	0	0
T13	53066	11376	0	0
T14	13052	2652	0	0
T15	140842	118430	0	0
T16	13130	2730	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	283841584	9738	0	0
T1	63248	2	0	0
T2	544620	0	0	0
T3	119740	7	0	0
T6	144126	2	0	0
T7	8163	0	0	0
T8	0	4	0	0
T9	123429	0	0	0
T10	15620	0	0	0
T11	653	0	0	0
T12	33816	31	0	0
T13	10205	1	0	0
T14	2510	0	0	0
T15	48753	26	0	0
T16	4545	0	0	0
T17	4518	0	0	0
T21	0	3	0	0
T24	498	0	0	0
T26	0	1	0	0
T27	0	2	0	0
T28	58815	15	0	0
T31	0	2	0	0
T38	0	1	0	0
T43	0	3	0	0
T44	0	2	0	0
T46	13375	2	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	0	1	0	0
T52	0	1	0	0
T53	1696	0	0	0
T54	3004	0	0	0
T55	1608	0	0	0
T69	896	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	283841584	9036	0	0
T1	15812	2	0	0
T2	136155	0	0	0
T3	23948	7	0	0
T6	32028	2	0	0
T7	1814	0	0	0
T8	0	4	0	0
T12	0	31	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	10834	26	0	0
T16	1010	0	0	0
T17	1004	0	0	0
T21	0	2	0	0
T22	190347	0	0	0
T26	584	1	0	0
T27	0	3	0	0
T28	0	15	0	0
T29	0	8	0	0
T31	0	2	0	0
T33	10931	0	0	0
T34	2781	0	0	0
T35	625	0	0	0
T43	0	3	0	0
T44	0	1	0	0
T45	8816	0	0	0
T46	2675	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T52	0	1	0	0
T72	5667	0	0	0
T73	0	31	0	0
T109	0	2	0	0
T110	0	1	0	0
T111	0	1	0	0
T112	406	0	0	0
T113	444	0	0	0
T114	422	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	283841584	6007	0	0
T3	23948	7	0	0
T6	16014	2	0	0
T7	907	0	0	0
T8	0	4	0	0
T12	0	31	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	2	0	0
T22	190347	0	0	0
T26	584	1	0	0
T27	0	3	0	0
T28	23526	15	0	0
T31	0	2	0	0
T33	10931	10	0	0
T34	2781	0	0	0
T35	625	0	0	0
T43	0	3	0	0
T44	0	1	0	0
T45	8816	5	0	0
T46	2675	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T52	0	1	0	0
T53	848	0	0	0
T54	1502	0	0	0
T55	402	0	0	0
T72	5667	0	0	0
T73	0	31	0	0
T108	0	10	0	0
T109	0	2	0	0
T110	0	1	0	0
T111	0	1	0	0
T112	406	0	0	0
T113	444	0	0	0
T114	422	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	283841584	6007	0	0
T3	23948	7	0	0
T6	16014	2	0	0
T7	907	0	0	0
T8	0	4	0	0
T12	0	31	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	2	0	0
T22	190347	0	0	0
T26	584	1	0	0
T27	0	3	0	0
T28	23526	15	0	0
T31	0	2	0	0
T33	10931	10	0	0
T34	2781	0	0	0
T35	625	0	0	0
T43	0	3	0	0
T44	0	1	0	0
T45	8816	5	0	0
T46	2675	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T52	0	1	0	0
T53	848	0	0	0
T54	1502	0	0	0
T55	402	0	0	0
T72	5667	0	0	0
T73	0	31	0	0
T108	0	10	0	0
T109	0	2	0	0
T110	0	1	0	0
T111	0	1	0	0
T112	406	0	0	0
T113	444	0	0	0
T114	422	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	283841584	3472090	0	0
T3	23948	224	0	0
T6	16014	36	0	0
T7	907	0	0	0
T8	0	60	0	0
T12	0	3821	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	10	0	0
T22	190347	0	0	0
T26	584	3	0	0
T27	0	13	0	0
T28	23526	2652	0	0
T31	0	36	0	0
T33	10931	124	0	0
T34	2781	0	0	0
T35	625	0	0	0
T43	0	6	0	0
T44	0	12	0	0
T45	8816	172	0	0
T46	2675	0	0	0
T49	0	11	0	0
T50	0	8	0	0
T52	0	9	0	0
T53	848	0	0	0
T54	1502	0	0	0
T55	402	0	0	0
T72	5667	0	0	0
T73	0	2545	0	0
T108	0	61	0	0
T109	0	11	0	0
T110	0	8	0	0
T111	0	9	0	0
T112	406	0	0	0
T113	444	0	0	0
T114	422	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98252856	53091	0	0
T1	142308	73	0	0
T2	1225395	55	0	0
T3	215532	189	0	0
T4	31770	103	0	0
T5	3798	12	0	0
T6	144126	81	0	0
T7	0	3	0	0
T13	18369	82	0	0
T14	4518	39	0	0
T15	48753	190	0	0
T16	4545	34	0	0
T17	0	9	0	0
T46	0	4	0	0
T53	0	3	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54584920	51173485	0	0
T1	79060	76935	0	0
T2	680775	672775	0	0
T3	119740	107590	0	0
T4	17650	7650	0	0
T5	2110	110	0	0
T6	80070	77925	0	0
T13	10205	2205	0	0
T14	2510	510	0	0
T15	27085	25085	0	0
T16	2525	525	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185588728	173989849	0	0
T1	268804	261579	0	0
T2	2314635	2287435	0	0
T3	407116	365806	0	0
T4	60010	26010	0	0
T5	7174	374	0	0
T6	272238	264945	0	0
T13	34697	7497	0	0
T14	8534	1734	0	0
T15	92089	85289	0	0
T16	8585	1785	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98252856	92112273	0	0
T1	142308	138483	0	0
T2	1225395	1210995	0	0
T3	215532	193662	0	0
T4	31770	13770	0	0
T5	3798	198	0	0
T6	144126	140265	0	0
T13	18369	3969	0	0
T14	4518	918	0	0
T15	48753	45153	0	0
T16	4545	945	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	251090632	4646	0	0
T3	23948	7	0	0
T6	16014	2	0	0
T7	907	0	0	0
T8	0	4	0	0
T12	0	20	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	2	0	0
T22	190347	0	0	0
T26	584	1	0	0
T27	0	3	0	0
T28	23526	14	0	0
T31	0	2	0	0
T33	10931	10	0	0
T34	2781	0	0	0
T35	625	0	0	0
T43	0	3	0	0
T44	0	1	0	0
T45	8816	5	0	0
T46	2675	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T52	0	1	0	0
T53	848	0	0	0
T54	1502	0	0	0
T55	402	0	0	0
T72	5667	0	0	0
T108	0	9	0	0
T109	0	2	0	0
T110	0	1	0	0
T111	0	1	0	0
T112	406	0	0	0
T113	444	0	0	0
T114	422	0	0	0
T115	0	4	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32750952	5144410	0	0
T3	23948	100	0	0
T6	16014	0	0	0
T7	907	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	25542	335	0	0
T22	380694	253072	0	0
T26	1168	0	0	0
T28	11763	0	0	0
T31	35632	0	0	0
T34	5562	0	0	0
T35	1250	0	0	0
T36	1052	0	0	0
T46	2675	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T59	0	689	0	0
T60	0	434	0	0
T61	0	502	0	0
T62	0	350	0	0
T72	11334	0	0	0
T74	0	111	0	0
T76	0	87611	0	0
T81	0	64	0	0
T82	0	961	0	0
T83	0	269	0	0
T112	812	0	0	0
T113	888	0	0	0
T116	0	305	0	0
T117	0	538542	0	0
T118	0	214	0	0
T119	0	25	0	0