Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.41	93.48	95.24		83.33	90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.41	93.48	95.24		83.33	90.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.00	89.13	90.48		66.67	85.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.00	89.13	90.48		66.67	85.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T7,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T7,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T7,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T21
1	0	Covered	T4,T5,T1
1	1	Covered	T2,T7,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T21
0	1	Covered	T136,T167
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T21
0	1	Covered	T2,T21,T35
1	0	Covered	T38,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T7,T21
1	-	Covered	T2,T21,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T7,T21
DetectSt	168	Covered	T2,T7,T21
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T7,T21

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T7,T21
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Covered	T136,T167
DetectSt->StableSt	191	Covered	T2,T7,T21
IdleSt->DebounceSt	148	Covered	T2,T7,T21
StableSt->IdleSt	206	Covered	T2,T21,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T7,T21
0	1	Covered	T2,T7,T21
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T21
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T7,T21
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T7,T21
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T7,T21
DetectSt	-	-	-	-	1	-	-	Covered	T136,T167
DetectSt	-	-	-	-	0	1	-	Covered	T2,T7,T21
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T21,T35
StableSt	-	-	-	-	-	-	0	Covered	T2,T7,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10916984	114	0	0
CntIncr_A	10916984	99204	0	0
CntNoWrap_A	10916984	10232116	0	0
DetectStDropOut_A	10916984	3	0	0
DetectedOut_A	10916984	3846	0	0
DetectedPulseOut_A	10916984	54	0	0
DisabledIdleSt_A	10916984	9974758	0	0
DisabledNoDetection_A	10916984	9977155	0	0
EnterDebounceSt_A	10916984	57	0	0
EnterDetectSt_A	10916984	57	0	0
EnterStableSt_A	10916984	54	0	0
PulseIsPulse_A	10916984	54	0	0
StayInStableSt	10916984	3764	0	0
gen_high_level_sva.HighLevelEvent_A	10916984	10234697	0	0
gen_not_sticky_sva.StableStDropOut_A	10916984	24	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	114	0	0
T2	136155	4	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	2	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	4	0	0
T34	0	2	0	0
T35	0	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T43	0	4	0	0
T44	0	2	0	0
T46	2675	0	0	0
T142	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	99204	0	0
T2	136155	42178	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	96	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	120	0	0
T34	0	11	0	0
T35	0	22	0	0
T38	0	20	0	0
T39	0	90	0	0
T43	0	144	0	0
T44	0	52	0	0
T46	2675	0	0	0
T142	0	87	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10232116	0	0
T1	15812	15381	0	0
T2	136155	134548	0	0
T3	23948	21508	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	15579	0	0
T13	2041	438	0	0
T14	502	101	0	0
T15	5417	5016	0	0
T16	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	3	0	0
T136	35987	1	0	0
T167	0	2	0	0
T168	714	0	0	0
T169	2615	0	0	0
T170	483	0	0	0
T171	782	0	0	0
T172	15530	0	0	0
T173	422	0	0	0
T174	502	0	0	0
T175	5116	0	0	0
T176	407	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	3846	0	0
T2	136155	85	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	59	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	101	0	0
T34	0	116	0	0
T35	0	44	0	0
T38	0	27	0	0
T39	0	188	0	0
T43	0	104	0	0
T44	0	241	0	0
T46	2675	0	0	0
T142	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	54	0	0
T2	136155	2	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	1	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	2	0	0
T34	0	1	0	0
T35	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T46	2675	0	0	0
T142	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	9974758	0	0
T1	15812	15381	0	0
T2	136155	128	0	0
T3	23948	21508	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	15579	0	0
T13	2041	438	0	0
T14	502	101	0	0
T15	5417	5016	0	0
T16	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	9977155	0	0
T1	15812	15387	0	0
T2	136155	130	0	0
T3	23948	21518	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	57	0	0
T2	136155	2	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	1	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	2	0	0
T34	0	1	0	0
T35	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T46	2675	0	0	0
T142	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	57	0	0
T2	136155	2	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	1	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	2	0	0
T34	0	1	0	0
T35	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T46	2675	0	0	0
T142	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	54	0	0
T2	136155	2	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	1	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	2	0	0
T34	0	1	0	0
T35	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T46	2675	0	0	0
T142	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	54	0	0
T2	136155	2	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	1	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	2	0	0
T34	0	1	0	0
T35	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T46	2675	0	0	0
T142	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	3764	0	0
T2	136155	82	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	57	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	98	0	0
T34	0	114	0	0
T35	0	43	0	0
T38	0	26	0	0
T39	0	187	0	0
T43	0	101	0	0
T44	0	240	0	0
T46	2675	0	0	0
T142	0	38	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10234697	0	0
T1	15812	15387	0	0
T2	136155	134555	0	0
T3	23948	21518	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	24	0	0
T2	136155	1	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	1	0	0
T35	0	1	0	0
T39	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	2675	0	0	0
T76	0	2	0	0
T163	0	1	0	0
T177	0	1	0	0
T178	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T11,T40,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T11,T40,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T11,T40,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T11,T40
1	0	Covered	T4,T5,T1
1	1	Covered	T11,T40,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T40,T21
0	1	Covered	T34,T179,T149
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T40,T21
0	1	Covered	T35,T44,T142
1	0	Covered	T38,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T40,T21
1	-	Covered	T35,T44,T142

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T40,T21
DetectSt	168	Covered	T11,T40,T21
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T11,T40,T21

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T40,T21
DebounceSt->IdleSt	163	Covered	T76,T147,T134
DetectSt->IdleSt	186	Covered	T34,T179,T149
DetectSt->StableSt	191	Covered	T11,T40,T21
IdleSt->DebounceSt	148	Covered	T11,T40,T21
StableSt->IdleSt	206	Covered	T21,T35,T27

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T40,T21
0	1	Covered	T11,T40,T21
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T40,T21
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T40,T21
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T40,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T76,T147,T134
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T40,T21
DetectSt	-	-	-	-	1	-	-	Covered	T34,T179,T149
DetectSt	-	-	-	-	0	1	-	Covered	T11,T40,T21
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T35,T38,T44
StableSt	-	-	-	-	-	-	0	Covered	T11,T40,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10916984	159	0	0
CntIncr_A	10916984	82557	0	0
CntNoWrap_A	10916984	10232071	0	0
DetectStDropOut_A	10916984	6	0	0
DetectedOut_A	10916984	66535	0	0
DetectedPulseOut_A	10916984	71	0	0
DisabledIdleSt_A	10916984	9949768	0	0
DisabledNoDetection_A	10916984	9952167	0	0
EnterDebounceSt_A	10916984	82	0	0
EnterDetectSt_A	10916984	77	0	0
EnterStableSt_A	10916984	71	0	0
PulseIsPulse_A	10916984	71	0	0
StayInStableSt	10916984	66431	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	10916984	3112	0	0
gen_low_level_sva.LowLevelEvent_A	10916984	10234697	0	0
gen_not_sticky_sva.StableStDropOut_A	10916984	36	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	159	0	0
T11	653	2	0	0
T12	33816	0	0	0
T21	12771	2	0	0
T25	493	0	0	0
T27	0	4	0	0
T34	0	2	0	0
T35	0	4	0	0
T36	526	0	0	0
T38	0	2	0	0
T40	547	2	0	0
T44	0	4	0	0
T69	896	0	0	0
T70	411	0	0	0
T142	0	2	0	0
T143	0	4	0	0
T153	402	0	0	0
T180	422	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	82557	0	0
T11	653	92	0	0
T12	33816	0	0	0
T21	12771	25	0	0
T25	493	0	0	0
T27	0	162	0	0
T34	0	11	0	0
T35	0	44	0	0
T36	526	0	0	0
T38	0	20	0	0
T40	547	45	0	0
T44	0	104	0	0
T69	896	0	0	0
T70	411	0	0	0
T142	0	87	0	0
T143	0	100	0	0
T153	402	0	0	0
T180	422	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10232071	0	0
T1	15812	15381	0	0
T2	136155	134552	0	0
T3	23948	21508	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	15579	0	0
T13	2041	438	0	0
T14	502	101	0	0
T15	5417	5016	0	0
T16	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	6	0	0
T22	190347	0	0	0
T33	10931	0	0	0
T34	2781	1	0	0
T35	625	0	0	0
T45	8816	0	0	0
T72	5667	0	0	0
T112	406	0	0	0
T113	444	0	0	0
T114	422	0	0	0
T138	406	0	0	0
T140	0	1	0	0
T149	0	1	0	0
T179	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	66535	0	0
T11	653	151	0	0
T12	33816	0	0	0
T21	12771	82	0	0
T25	493	0	0	0
T27	0	78	0	0
T35	0	102	0	0
T36	526	0	0	0
T38	0	26	0	0
T40	547	42	0	0
T44	0	57	0	0
T69	896	0	0	0
T70	411	0	0	0
T142	0	132	0	0
T143	0	126	0	0
T153	402	0	0	0
T180	422	0	0	0
T183	0	292	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	71	0	0
T11	653	1	0	0
T12	33816	0	0	0
T21	12771	1	0	0
T25	493	0	0	0
T27	0	2	0	0
T35	0	2	0	0
T36	526	0	0	0
T38	0	1	0	0
T40	547	1	0	0
T44	0	2	0	0
T69	896	0	0	0
T70	411	0	0	0
T142	0	1	0	0
T143	0	2	0	0
T153	402	0	0	0
T180	422	0	0	0
T183	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	9949768	0	0
T1	15812	15381	0	0
T2	136155	134552	0	0
T3	23948	21508	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	15579	0	0
T13	2041	438	0	0
T14	502	101	0	0
T15	5417	5016	0	0
T16	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	9952167	0	0
T1	15812	15387	0	0
T2	136155	134555	0	0
T3	23948	21518	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	82	0	0
T11	653	1	0	0
T12	33816	0	0	0
T21	12771	1	0	0
T25	493	0	0	0
T27	0	2	0	0
T34	0	1	0	0
T35	0	2	0	0
T36	526	0	0	0
T38	0	1	0	0
T40	547	1	0	0
T44	0	2	0	0
T69	896	0	0	0
T70	411	0	0	0
T142	0	1	0	0
T143	0	2	0	0
T153	402	0	0	0
T180	422	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	77	0	0
T11	653	1	0	0
T12	33816	0	0	0
T21	12771	1	0	0
T25	493	0	0	0
T27	0	2	0	0
T34	0	1	0	0
T35	0	2	0	0
T36	526	0	0	0
T38	0	1	0	0
T40	547	1	0	0
T44	0	2	0	0
T69	896	0	0	0
T70	411	0	0	0
T142	0	1	0	0
T143	0	2	0	0
T153	402	0	0	0
T180	422	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	71	0	0
T11	653	1	0	0
T12	33816	0	0	0
T21	12771	1	0	0
T25	493	0	0	0
T27	0	2	0	0
T35	0	2	0	0
T36	526	0	0	0
T38	0	1	0	0
T40	547	1	0	0
T44	0	2	0	0
T69	896	0	0	0
T70	411	0	0	0
T142	0	1	0	0
T143	0	2	0	0
T153	402	0	0	0
T180	422	0	0	0
T183	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	71	0	0
T11	653	1	0	0
T12	33816	0	0	0
T21	12771	1	0	0
T25	493	0	0	0
T27	0	2	0	0
T35	0	2	0	0
T36	526	0	0	0
T38	0	1	0	0
T40	547	1	0	0
T44	0	2	0	0
T69	896	0	0	0
T70	411	0	0	0
T142	0	1	0	0
T143	0	2	0	0
T153	402	0	0	0
T180	422	0	0	0
T183	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	66431	0	0
T11	653	149	0	0
T12	33816	0	0	0
T21	12771	80	0	0
T25	493	0	0	0
T27	0	74	0	0
T35	0	99	0	0
T36	526	0	0	0
T38	0	25	0	0
T40	547	40	0	0
T44	0	54	0	0
T69	896	0	0	0
T70	411	0	0	0
T142	0	131	0	0
T143	0	123	0	0
T153	402	0	0	0
T180	422	0	0	0
T183	0	289	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	3112	0	0
T1	15812	0	0	0
T2	136155	7	0	0
T3	23948	6	0	0
T4	3530	7	0	0
T5	422	2	0	0
T6	16014	0	0	0
T7	0	1	0	0
T13	2041	8	0	0
T14	502	4	0	0
T15	5417	0	0	0
T16	505	6	0	0
T17	0	4	0	0
T46	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10234697	0	0
T1	15812	15387	0	0
T2	136155	134555	0	0
T3	23948	21518	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	36	0	0
T22	190347	0	0	0
T33	10931	0	0	0
T35	625	1	0	0
T44	0	1	0	0
T45	8816	0	0	0
T59	1821	0	0	0
T71	502	0	0	0
T72	5667	0	0	0
T76	0	1	0	0
T113	444	0	0	0
T114	422	0	0	0
T138	406	0	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T183	0	1	0	0
T184	0	1	0	0
T185	0	1	0	0
T186	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T9,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T7,T9,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T9,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T9,T11
1	0	Covered	T4,T5,T1
1	1	Covered	T7,T9,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T9,T40
0	1	Covered	T34,T76,T184
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T9,T40
0	1	Covered	T43,T187,T44
1	0	Covered	T38,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T9,T40
1	-	Covered	T43,T187,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T9,T40
DetectSt	168	Covered	T7,T9,T40
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T7,T9,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T9,T40
DebounceSt->IdleSt	163	Covered	T146,T94,T147
DetectSt->IdleSt	186	Covered	T34,T76,T184
DetectSt->StableSt	191	Covered	T7,T9,T40
IdleSt->DebounceSt	148	Covered	T7,T9,T40
StableSt->IdleSt	206	Covered	T9,T27,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T9,T40
0	1	Covered	T7,T9,T40
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T40
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T9,T40
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T9,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T94,T147,T148
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T9,T40
DetectSt	-	-	-	-	1	-	-	Covered	T34,T76,T184
DetectSt	-	-	-	-	0	1	-	Covered	T7,T9,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T43,T187,T38
StableSt	-	-	-	-	-	-	0	Covered	T7,T9,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10916984	203	0	0
CntIncr_A	10916984	7040	0	0
CntNoWrap_A	10916984	10232027	0	0
DetectStDropOut_A	10916984	5	0	0
DetectedOut_A	10916984	9037	0	0
DetectedPulseOut_A	10916984	93	0	0
DisabledIdleSt_A	10916984	10104147	0	0
DisabledNoDetection_A	10916984	10106535	0	0
EnterDebounceSt_A	10916984	106	0	0
EnterDetectSt_A	10916984	98	0	0
EnterStableSt_A	10916984	93	0	0
PulseIsPulse_A	10916984	93	0	0
StayInStableSt	10916984	8903	0	0
gen_high_level_sva.HighLevelEvent_A	10916984	10234697	0	0
gen_not_sticky_sva.StableStDropOut_A	10916984	50	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	203	0	0
T7	907	2	0	0
T8	12734	0	0	0
T9	0	2	0	0
T27	0	2	0	0
T28	11763	0	0	0
T29	5617	0	0	0
T34	0	2	0	0
T38	0	2	0	0
T40	0	2	0	0
T41	0	2	0	0
T43	0	4	0	0
T44	0	8	0	0
T46	2675	0	0	0
T47	443	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T187	0	2	0	0
T188	434	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	7040	0	0
T7	907	96	0	0
T8	12734	0	0	0
T9	0	45	0	0
T27	0	72	0	0
T28	11763	0	0	0
T29	5617	0	0	0
T34	0	11	0	0
T38	0	20	0	0
T40	0	45	0	0
T41	0	69	0	0
T43	0	144	0	0
T44	0	247	0	0
T46	2675	0	0	0
T47	443	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T187	0	30	0	0
T188	434	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10232027	0	0
T1	15812	15381	0	0
T2	136155	134552	0	0
T3	23948	21508	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	15579	0	0
T13	2041	438	0	0
T14	502	101	0	0
T15	5417	5016	0	0
T16	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	5	0	0
T22	190347	0	0	0
T33	10931	0	0	0
T34	2781	1	0	0
T35	625	0	0	0
T45	8816	0	0	0
T72	5667	0	0	0
T76	0	1	0	0
T112	406	0	0	0
T113	444	0	0	0
T114	422	0	0	0
T138	406	0	0	0
T167	0	1	0	0
T184	0	1	0	0
T189	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	9037	0	0
T7	907	296	0	0
T8	12734	0	0	0
T9	0	109	0	0
T27	0	167	0	0
T28	11763	0	0	0
T29	5617	0	0	0
T38	0	25	0	0
T40	0	92	0	0
T41	0	235	0	0
T43	0	325	0	0
T44	0	607	0	0
T46	2675	0	0	0
T47	443	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T110	0	115	0	0
T187	0	14	0	0
T188	434	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	93	0	0
T7	907	1	0	0
T8	12734	0	0	0
T9	0	1	0	0
T27	0	1	0	0
T28	11763	0	0	0
T29	5617	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T43	0	2	0	0
T44	0	4	0	0
T46	2675	0	0	0
T47	443	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T110	0	1	0	0
T187	0	1	0	0
T188	434	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10104147	0	0
T1	15812	15381	0	0
T2	136155	134552	0	0
T3	23948	21508	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	15579	0	0
T13	2041	438	0	0
T14	502	101	0	0
T15	5417	5016	0	0
T16	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10106535	0	0
T1	15812	15387	0	0
T2	136155	134555	0	0
T3	23948	21518	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	106	0	0
T7	907	1	0	0
T8	12734	0	0	0
T9	0	1	0	0
T27	0	1	0	0
T28	11763	0	0	0
T29	5617	0	0	0
T34	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T43	0	2	0	0
T44	0	4	0	0
T46	2675	0	0	0
T47	443	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T187	0	1	0	0
T188	434	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	98	0	0
T7	907	1	0	0
T8	12734	0	0	0
T9	0	1	0	0
T27	0	1	0	0
T28	11763	0	0	0
T29	5617	0	0	0
T34	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T43	0	2	0	0
T44	0	4	0	0
T46	2675	0	0	0
T47	443	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T187	0	1	0	0
T188	434	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	93	0	0
T7	907	1	0	0
T8	12734	0	0	0
T9	0	1	0	0
T27	0	1	0	0
T28	11763	0	0	0
T29	5617	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T43	0	2	0	0
T44	0	4	0	0
T46	2675	0	0	0
T47	443	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T110	0	1	0	0
T187	0	1	0	0
T188	434	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	93	0	0
T7	907	1	0	0
T8	12734	0	0	0
T9	0	1	0	0
T27	0	1	0	0
T28	11763	0	0	0
T29	5617	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T43	0	2	0	0
T44	0	4	0	0
T46	2675	0	0	0
T47	443	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T110	0	1	0	0
T187	0	1	0	0
T188	434	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	8903	0	0
T7	907	294	0	0
T8	12734	0	0	0
T9	0	107	0	0
T27	0	165	0	0
T28	11763	0	0	0
T29	5617	0	0	0
T38	0	24	0	0
T40	0	90	0	0
T41	0	233	0	0
T43	0	322	0	0
T44	0	603	0	0
T46	2675	0	0	0
T47	443	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T110	0	113	0	0
T187	0	13	0	0
T188	434	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10234697	0	0
T1	15812	15387	0	0
T2	136155	134555	0	0
T3	23948	21518	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	50	0	0
T37	638	0	0	0
T42	1913	0	0	0
T43	3210	1	0	0
T44	0	4	0	0
T65	505	0	0	0
T76	0	1	0	0
T80	0	1	0	0
T87	5175	0	0	0
T118	0	2	0	0
T141	0	1	0	0
T144	0	1	0	0
T166	32868	0	0	0
T183	0	1	0	0
T187	524	1	0	0
T190	0	1	0	0
T191	405	0	0	0
T192	1266	0	0	0
T193	425	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T21,T37,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T21,T37,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T21,T37,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T11,T40
1	0	Covered	T4,T5,T1
1	1	Covered	T21,T37,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T21,T37,T38
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T21,T37,T38
0	1	Covered	T21,T184,T185
1	0	Covered	T38,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T21,T37,T38
1	-	Covered	T21,T184,T185

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T21,T37,T38
DetectSt	168	Covered	T21,T37,T38
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T21,T37,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T21,T37,T38
DebounceSt->IdleSt	163	Covered	T76,T184,T178
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T21,T37,T38
IdleSt->DebounceSt	148	Covered	T21,T37,T38
StableSt->IdleSt	206	Covered	T21,T38,T44

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T21,T37,T38
0	1	Covered	T21,T37,T38
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T37,T38
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T21,T37,T38
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T21,T37,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T76,T184,T178
DebounceSt	-	0	0	-	-	-	-	Covered	T21,T37,T38
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T21,T37,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T21,T38,T184
StableSt	-	-	-	-	-	-	0	Covered	T21,T37,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10916984	92	0	0
CntIncr_A	10916984	41861	0	0
CntNoWrap_A	10916984	10232138	0	0
DetectStDropOut_A	10916984	0	0	0
DetectedOut_A	10916984	3343	0	0
DetectedPulseOut_A	10916984	44	0	0
DisabledIdleSt_A	10916984	9782692	0	0
DisabledNoDetection_A	10916984	9785098	0	0
EnterDebounceSt_A	10916984	48	0	0
EnterDetectSt_A	10916984	44	0	0
EnterStableSt_A	10916984	44	0	0
PulseIsPulse_A	10916984	44	0	0
StayInStableSt	10916984	3276	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	10916984	6840	0	0
gen_low_level_sva.LowLevelEvent_A	10916984	10234697	0	0
gen_not_sticky_sva.StableStDropOut_A	10916984	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	92	0	0
T21	12771	2	0	0
T22	190347	0	0	0
T26	584	0	0	0
T31	17816	0	0	0
T34	2781	0	0	0
T35	625	0	0	0
T36	526	0	0	0
T37	0	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T44	0	2	0	0
T72	5667	0	0	0
T76	0	3	0	0
T80	0	2	0	0
T112	406	0	0	0
T113	444	0	0	0
T159	0	2	0	0
T183	0	2	0	0
T190	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	41861	0	0
T21	12771	60	0	0
T22	190347	0	0	0
T26	584	0	0	0
T31	17816	0	0	0
T34	2781	0	0	0
T35	625	0	0	0
T36	526	0	0	0
T37	0	77	0	0
T38	0	20	0	0
T39	0	90	0	0
T44	0	27	0	0
T72	5667	0	0	0
T76	0	125	0	0
T80	0	64	0	0
T112	406	0	0	0
T113	444	0	0	0
T159	0	72	0	0
T183	0	64	0	0
T190	0	40	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10232138	0	0
T1	15812	15381	0	0
T2	136155	134552	0	0
T3	23948	21508	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	15579	0	0
T13	2041	438	0	0
T14	502	101	0	0
T15	5417	5016	0	0
T16	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	3343	0	0
T21	12771	42	0	0
T22	190347	0	0	0
T26	584	0	0	0
T31	17816	0	0	0
T34	2781	0	0	0
T35	625	0	0	0
T36	526	0	0	0
T37	0	41	0	0
T38	0	27	0	0
T39	0	52	0	0
T44	0	45	0	0
T72	5667	0	0	0
T76	0	47	0	0
T80	0	41	0	0
T112	406	0	0	0
T113	444	0	0	0
T159	0	43	0	0
T183	0	400	0	0
T190	0	118	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	44	0	0
T21	12771	1	0	0
T22	190347	0	0	0
T26	584	0	0	0
T31	17816	0	0	0
T34	2781	0	0	0
T35	625	0	0	0
T36	526	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T44	0	1	0	0
T72	5667	0	0	0
T76	0	1	0	0
T80	0	1	0	0
T112	406	0	0	0
T113	444	0	0	0
T159	0	1	0	0
T183	0	1	0	0
T190	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	9782692	0	0
T1	15812	15381	0	0
T2	136155	134552	0	0
T3	23948	21508	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	15579	0	0
T13	2041	438	0	0
T14	502	101	0	0
T15	5417	5016	0	0
T16	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	9785098	0	0
T1	15812	15387	0	0
T2	136155	134555	0	0
T3	23948	21518	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	48	0	0
T21	12771	1	0	0
T22	190347	0	0	0
T26	584	0	0	0
T31	17816	0	0	0
T34	2781	0	0	0
T35	625	0	0	0
T36	526	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T44	0	1	0	0
T72	5667	0	0	0
T76	0	2	0	0
T80	0	1	0	0
T112	406	0	0	0
T113	444	0	0	0
T159	0	1	0	0
T183	0	1	0	0
T190	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	44	0	0
T21	12771	1	0	0
T22	190347	0	0	0
T26	584	0	0	0
T31	17816	0	0	0
T34	2781	0	0	0
T35	625	0	0	0
T36	526	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T44	0	1	0	0
T72	5667	0	0	0
T76	0	1	0	0
T80	0	1	0	0
T112	406	0	0	0
T113	444	0	0	0
T159	0	1	0	0
T183	0	1	0	0
T190	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	44	0	0
T21	12771	1	0	0
T22	190347	0	0	0
T26	584	0	0	0
T31	17816	0	0	0
T34	2781	0	0	0
T35	625	0	0	0
T36	526	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T44	0	1	0	0
T72	5667	0	0	0
T76	0	1	0	0
T80	0	1	0	0
T112	406	0	0	0
T113	444	0	0	0
T159	0	1	0	0
T183	0	1	0	0
T190	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	44	0	0
T21	12771	1	0	0
T22	190347	0	0	0
T26	584	0	0	0
T31	17816	0	0	0
T34	2781	0	0	0
T35	625	0	0	0
T36	526	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T44	0	1	0	0
T72	5667	0	0	0
T76	0	1	0	0
T80	0	1	0	0
T112	406	0	0	0
T113	444	0	0	0
T159	0	1	0	0
T183	0	1	0	0
T190	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	3276	0	0
T21	12771	41	0	0
T22	190347	0	0	0
T26	584	0	0	0
T31	17816	0	0	0
T34	2781	0	0	0
T35	625	0	0	0
T36	526	0	0	0
T37	0	39	0	0
T38	0	26	0	0
T39	0	50	0	0
T44	0	43	0	0
T72	5667	0	0	0
T76	0	45	0	0
T80	0	39	0	0
T112	406	0	0	0
T113	444	0	0	0
T159	0	41	0	0
T183	0	398	0	0
T190	0	116	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	6840	0	0
T1	15812	8	0	0
T2	136155	5	0	0
T3	23948	31	0	0
T4	3530	15	0	0
T5	422	1	0	0
T6	16014	10	0	0
T13	2041	9	0	0
T14	502	6	0	0
T15	5417	21	0	0
T16	505	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10234697	0	0
T1	15812	15387	0	0
T2	136155	134555	0	0
T3	23948	21518	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	19	0	0
T21	12771	1	0	0
T22	190347	0	0	0
T26	584	0	0	0
T31	17816	0	0	0
T34	2781	0	0	0
T35	625	0	0	0
T36	526	0	0	0
T72	5667	0	0	0
T94	0	1	0	0
T112	406	0	0	0
T113	444	0	0	0
T146	0	1	0	0
T149	0	1	0	0
T152	0	1	0	0
T184	0	1	0	0
T185	0	1	0	0
T186	0	1	0	0
T194	0	1	0	0
T195	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T40,T21,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T40,T21,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T40,T21,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T40,T21
1	0	Covered	T4,T5,T1
1	1	Covered	T40,T21,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T40,T21,T34
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T40,T21,T34
0	1	Covered	T40,T34,T41
1	0	Covered	T38,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T40,T21,T34
1	-	Covered	T40,T34,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T40,T21,T36
DetectSt	168	Covered	T40,T21,T34
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T40,T21,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T40,T21,T34
DebounceSt->IdleSt	163	Covered	T36,T44,T141
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T40,T21,T34
IdleSt->DebounceSt	148	Covered	T40,T21,T36
StableSt->IdleSt	206	Covered	T40,T21,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T40,T21,T36
0	1	Covered	T40,T21,T36
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T40,T21,T34
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T40,T21,T36
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T40,T21,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T36,T44,T141
DebounceSt	-	0	0	-	-	-	-	Covered	T40,T21,T36
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T40,T21,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T40,T34,T41
StableSt	-	-	-	-	-	-	0	Covered	T40,T21,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10916984	153	0	0
CntIncr_A	10916984	58261	0	0
CntNoWrap_A	10916984	10232077	0	0
DetectStDropOut_A	10916984	0	0	0
DetectedOut_A	10916984	6414	0	0
DetectedPulseOut_A	10916984	72	0	0
DisabledIdleSt_A	10916984	10111723	0	0
DisabledNoDetection_A	10916984	10114125	0	0
EnterDebounceSt_A	10916984	81	0	0
EnterDetectSt_A	10916984	72	0	0
EnterStableSt_A	10916984	72	0	0
PulseIsPulse_A	10916984	72	0	0
StayInStableSt	10916984	6312	0	0
gen_high_level_sva.HighLevelEvent_A	10916984	10234697	0	0
gen_not_sticky_sva.StableStDropOut_A	10916984	40	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	153	0	0
T21	12771	2	0	0
T25	493	0	0	0
T26	584	0	0	0
T31	17816	0	0	0
T34	2781	4	0	0
T36	526	1	0	0
T37	0	2	0	0
T38	0	2	0	0
T39	0	4	0	0
T40	547	2	0	0
T41	0	4	0	0
T42	0	4	0	0
T44	0	9	0	0
T112	406	0	0	0
T153	402	0	0	0
T180	422	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	58261	0	0
T21	12771	25	0	0
T25	493	0	0	0
T26	584	0	0	0
T31	17816	0	0	0
T34	2781	22	0	0
T36	526	44	0	0
T37	0	77	0	0
T38	0	20	0	0
T39	0	180	0	0
T40	547	45	0	0
T41	0	138	0	0
T42	0	86	0	0
T44	0	350	0	0
T112	406	0	0	0
T153	402	0	0	0
T180	422	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10232077	0	0
T1	15812	15381	0	0
T2	136155	134552	0	0
T3	23948	21508	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	15579	0	0
T13	2041	438	0	0
T14	502	101	0	0
T15	5417	5016	0	0
T16	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	6414	0	0
T21	12771	81	0	0
T25	493	0	0	0
T26	584	0	0	0
T31	17816	0	0	0
T34	2781	84	0	0
T36	526	0	0	0
T37	0	151	0	0
T38	0	27	0	0
T39	0	332	0	0
T40	547	4	0	0
T41	0	165	0	0
T42	0	85	0	0
T44	0	340	0	0
T112	406	0	0	0
T126	0	81	0	0
T153	402	0	0	0
T180	422	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	72	0	0
T21	12771	1	0	0
T25	493	0	0	0
T26	584	0	0	0
T31	17816	0	0	0
T34	2781	2	0	0
T36	526	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	547	1	0	0
T41	0	2	0	0
T42	0	2	0	0
T44	0	4	0	0
T112	406	0	0	0
T126	0	2	0	0
T153	402	0	0	0
T180	422	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10111723	0	0
T1	15812	15381	0	0
T2	136155	134552	0	0
T3	23948	21508	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	15579	0	0
T13	2041	438	0	0
T14	502	101	0	0
T15	5417	5016	0	0
T16	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10114125	0	0
T1	15812	15387	0	0
T2	136155	134555	0	0
T3	23948	21518	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	81	0	0
T21	12771	1	0	0
T25	493	0	0	0
T26	584	0	0	0
T31	17816	0	0	0
T34	2781	2	0	0
T36	526	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	547	1	0	0
T41	0	2	0	0
T42	0	2	0	0
T44	0	5	0	0
T112	406	0	0	0
T153	402	0	0	0
T180	422	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	72	0	0
T21	12771	1	0	0
T25	493	0	0	0
T26	584	0	0	0
T31	17816	0	0	0
T34	2781	2	0	0
T36	526	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	547	1	0	0
T41	0	2	0	0
T42	0	2	0	0
T44	0	4	0	0
T112	406	0	0	0
T126	0	2	0	0
T153	402	0	0	0
T180	422	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	72	0	0
T21	12771	1	0	0
T25	493	0	0	0
T26	584	0	0	0
T31	17816	0	0	0
T34	2781	2	0	0
T36	526	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	547	1	0	0
T41	0	2	0	0
T42	0	2	0	0
T44	0	4	0	0
T112	406	0	0	0
T126	0	2	0	0
T153	402	0	0	0
T180	422	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	72	0	0
T21	12771	1	0	0
T25	493	0	0	0
T26	584	0	0	0
T31	17816	0	0	0
T34	2781	2	0	0
T36	526	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	547	1	0	0
T41	0	2	0	0
T42	0	2	0	0
T44	0	4	0	0
T112	406	0	0	0
T126	0	2	0	0
T153	402	0	0	0
T180	422	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	6312	0	0
T21	12771	79	0	0
T25	493	0	0	0
T26	584	0	0	0
T31	17816	0	0	0
T34	2781	81	0	0
T36	526	0	0	0
T37	0	149	0	0
T38	0	26	0	0
T39	0	329	0	0
T40	547	3	0	0
T41	0	162	0	0
T42	0	82	0	0
T44	0	334	0	0
T112	406	0	0	0
T126	0	78	0	0
T153	402	0	0	0
T180	422	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10234697	0	0
T1	15812	15387	0	0
T2	136155	134555	0	0
T3	23948	21518	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	40	0	0
T21	12771	0	0	0
T25	493	0	0	0
T26	584	0	0	0
T31	17816	0	0	0
T34	2781	1	0	0
T36	526	0	0	0
T39	0	1	0	0
T40	547	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T44	0	2	0	0
T80	0	1	0	0
T112	406	0	0	0
T126	0	1	0	0
T153	402	0	0	0
T180	422	0	0	0
T196	0	1	0	0
T197	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	41	89.13
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	27	84.38
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T21,T36,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T21,T36,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T21,T36,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T9,T11
1	0	Covered	T4,T5,T1
1	1	Covered	T21,T36,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T21,T36,T34
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T21,T36,T34
0	1	Covered	T21,T34,T41
1	0	Covered	T38,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T21,T36,T34
1	-	Covered	T21,T34,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	4	66.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T21,T36,T34
DetectSt	168	Covered	T21,T36,T34
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T21,T36,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T21,T36,T34
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T21,T36,T34
IdleSt->DebounceSt	148	Covered	T21,T36,T34
StableSt->IdleSt	206	Covered	T21,T34,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	17	85.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	7	70.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T21,T36,T34
0	1	Covered	T21,T36,T34
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T21,T36,T34
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T21,T36,T34
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T21,T36,T34
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T21,T36,T34
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T21,T36,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T21,T34,T41
StableSt	-	-	-	-	-	-	0	Covered	T21,T36,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10916984	100	0	0
CntIncr_A	10916984	2962	0	0
CntNoWrap_A	10916984	10232130	0	0
DetectStDropOut_A	10916984	0	0	0
DetectedOut_A	10916984	4427	0	0
DetectedPulseOut_A	10916984	50	0	0
DisabledIdleSt_A	10916984	10040681	0	0
DisabledNoDetection_A	10916984	10043077	0	0
EnterDebounceSt_A	10916984	50	0	0
EnterDetectSt_A	10916984	50	0	0
EnterStableSt_A	10916984	50	0	0
PulseIsPulse_A	10916984	50	0	0
StayInStableSt	10916984	4349	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	10916984	6364	0	0
gen_low_level_sva.LowLevelEvent_A	10916984	10234697	0	0
gen_not_sticky_sva.StableStDropOut_A	10916984	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	100	0	0
T21	12771	4	0	0
T22	190347	0	0	0
T26	584	0	0	0
T31	17816	0	0	0
T34	2781	2	0	0
T35	625	2	0	0
T36	526	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T41	0	2	0	0
T44	0	8	0	0
T72	5667	0	0	0
T110	0	2	0	0
T112	406	0	0	0
T113	444	0	0	0
T198	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	2962	0	0
T21	12771	120	0	0
T22	190347	0	0	0
T26	584	0	0	0
T31	17816	0	0	0
T34	2781	11	0	0
T35	625	22	0	0
T36	526	44	0	0
T38	0	20	0	0
T39	0	90	0	0
T41	0	69	0	0
T44	0	274	0	0
T72	5667	0	0	0
T110	0	71	0	0
T112	406	0	0	0
T113	444	0	0	0
T198	0	180	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10232130	0	0
T1	15812	15381	0	0
T2	136155	134552	0	0
T3	23948	21508	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	15579	0	0
T13	2041	438	0	0
T14	502	101	0	0
T15	5417	5016	0	0
T16	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	4427	0	0
T21	12771	102	0	0
T22	190347	0	0	0
T26	584	0	0	0
T31	17816	0	0	0
T34	2781	7	0	0
T35	625	159	0	0
T36	526	44	0	0
T38	0	25	0	0
T39	0	220	0	0
T41	0	1	0	0
T44	0	563	0	0
T72	5667	0	0	0
T110	0	43	0	0
T112	406	0	0	0
T113	444	0	0	0
T198	0	81	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	50	0	0
T21	12771	2	0	0
T22	190347	0	0	0
T26	584	0	0	0
T31	17816	0	0	0
T34	2781	1	0	0
T35	625	1	0	0
T36	526	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T44	0	4	0	0
T72	5667	0	0	0
T110	0	1	0	0
T112	406	0	0	0
T113	444	0	0	0
T198	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10040681	0	0
T1	15812	15381	0	0
T2	136155	134552	0	0
T3	23948	21508	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	15579	0	0
T13	2041	438	0	0
T14	502	101	0	0
T15	5417	5016	0	0
T16	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10043077	0	0
T1	15812	15387	0	0
T2	136155	134555	0	0
T3	23948	21518	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	50	0	0
T21	12771	2	0	0
T22	190347	0	0	0
T26	584	0	0	0
T31	17816	0	0	0
T34	2781	1	0	0
T35	625	1	0	0
T36	526	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T44	0	4	0	0
T72	5667	0	0	0
T110	0	1	0	0
T112	406	0	0	0
T113	444	0	0	0
T198	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	50	0	0
T21	12771	2	0	0
T22	190347	0	0	0
T26	584	0	0	0
T31	17816	0	0	0
T34	2781	1	0	0
T35	625	1	0	0
T36	526	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T44	0	4	0	0
T72	5667	0	0	0
T110	0	1	0	0
T112	406	0	0	0
T113	444	0	0	0
T198	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	50	0	0
T21	12771	2	0	0
T22	190347	0	0	0
T26	584	0	0	0
T31	17816	0	0	0
T34	2781	1	0	0
T35	625	1	0	0
T36	526	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T44	0	4	0	0
T72	5667	0	0	0
T110	0	1	0	0
T112	406	0	0	0
T113	444	0	0	0
T198	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	50	0	0
T21	12771	2	0	0
T22	190347	0	0	0
T26	584	0	0	0
T31	17816	0	0	0
T34	2781	1	0	0
T35	625	1	0	0
T36	526	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T44	0	4	0	0
T72	5667	0	0	0
T110	0	1	0	0
T112	406	0	0	0
T113	444	0	0	0
T198	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	4349	0	0
T21	12771	99	0	0
T22	190347	0	0	0
T26	584	0	0	0
T31	17816	0	0	0
T34	2781	6	0	0
T35	625	157	0	0
T36	526	42	0	0
T38	0	24	0	0
T39	0	219	0	0
T44	0	557	0	0
T72	5667	0	0	0
T110	0	41	0	0
T112	406	0	0	0
T113	444	0	0	0
T190	0	31	0	0
T198	0	78	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	6364	0	0
T1	15812	11	0	0
T2	136155	7	0	0
T3	23948	28	0	0
T4	3530	8	0	0
T5	422	1	0	0
T6	16014	12	0	0
T13	2041	6	0	0
T14	502	4	0	0
T15	5417	26	0	0
T16	505	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10234697	0	0
T1	15812	15387	0	0
T2	136155	134555	0	0
T3	23948	21518	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	20	0	0
T21	12771	1	0	0
T22	190347	0	0	0
T26	584	0	0	0
T31	17816	0	0	0
T34	2781	1	0	0
T35	625	0	0	0
T36	526	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T44	0	2	0	0
T72	5667	0	0	0
T94	0	1	0	0
T112	406	0	0	0
T113	444	0	0	0
T118	0	1	0	0
T186	0	1	0	0
T190	0	1	0	0
T198	0	1	0	0