Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T27,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T7,T27,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T27,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T9,T27
1	0	Covered	T4,T5,T1
1	1	Covered	T7,T27,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T41,T42
0	1	Covered	T27,T80,T144
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T41,T42
0	1	Covered	T41,T42,T187
1	0	Covered	T38,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T41,T42
1	-	Covered	T41,T42,T187

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T27,T41
DetectSt	168	Covered	T7,T27,T41
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T7,T41,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T27,T41
DebounceSt->IdleSt	163	Covered	T199,T152,T146
DetectSt->IdleSt	186	Covered	T27,T80,T144
DetectSt->StableSt	191	Covered	T7,T41,T42
IdleSt->DebounceSt	148	Covered	T7,T27,T41
StableSt->IdleSt	206	Covered	T41,T42,T187

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T27,T41
0	1	Covered	T7,T27,T41
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T27,T41
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T27,T41
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T27,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T199,T152,T134
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T27,T41
DetectSt	-	-	-	-	1	-	-	Covered	T27,T80,T144
DetectSt	-	-	-	-	0	1	-	Covered	T7,T41,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T41,T42,T187
StableSt	-	-	-	-	-	-	0	Covered	T7,T41,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10916984	202	0	0
CntIncr_A	10916984	210291	0	0
CntNoWrap_A	10916984	10232028	0	0
DetectStDropOut_A	10916984	3	0	0
DetectedOut_A	10916984	11093	0	0
DetectedPulseOut_A	10916984	95	0	0
DisabledIdleSt_A	10916984	9777595	0	0
DisabledNoDetection_A	10916984	9779982	0	0
EnterDebounceSt_A	10916984	105	0	0
EnterDetectSt_A	10916984	98	0	0
EnterStableSt_A	10916984	95	0	0
PulseIsPulse_A	10916984	95	0	0
StayInStableSt	10916984	10960	0	0
gen_high_level_sva.HighLevelEvent_A	10916984	10234697	0	0
gen_not_sticky_sva.StableStDropOut_A	10916984	55	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	202	0	0
T7	907	2	0	0
T8	12734	0	0	0
T27	0	2	0	0
T28	11763	0	0	0
T29	5617	0	0	0
T38	0	2	0	0
T39	0	4	0	0
T41	0	4	0	0
T42	0	2	0	0
T44	0	12	0	0
T46	2675	0	0	0
T47	443	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T80	0	2	0	0
T110	0	2	0	0
T187	0	2	0	0
T188	434	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	210291	0	0
T7	907	96	0	0
T8	12734	0	0	0
T27	0	90	0	0
T28	11763	0	0	0
T29	5617	0	0	0
T38	0	20	0	0
T39	0	180	0	0
T41	0	138	0	0
T42	0	43	0	0
T44	0	398	0	0
T46	2675	0	0	0
T47	443	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T80	0	64	0	0
T110	0	71	0	0
T187	0	30	0	0
T188	434	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10232028	0	0
T1	15812	15381	0	0
T2	136155	134552	0	0
T3	23948	21508	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	15579	0	0
T13	2041	438	0	0
T14	502	101	0	0
T15	5417	5016	0	0
T16	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	3	0	0
T27	7713	1	0	0
T73	19489	0	0	0
T80	0	1	0	0
T84	5516	0	0	0
T108	26174	0	0	0
T144	0	1	0	0
T200	559	0	0	0
T201	503	0	0	0
T202	411	0	0	0
T203	402	0	0	0
T204	402	0	0	0
T205	562	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	11093	0	0
T7	907	297	0	0
T8	12734	0	0	0
T28	11763	0	0	0
T29	5617	0	0	0
T38	0	25	0	0
T39	0	96	0	0
T41	0	164	0	0
T42	0	44	0	0
T44	0	459	0	0
T46	2675	0	0	0
T47	443	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T110	0	42	0	0
T141	0	314	0	0
T187	0	16	0	0
T188	434	0	0	0
T196	0	133	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	95	0	0
T7	907	1	0	0
T8	12734	0	0	0
T28	11763	0	0	0
T29	5617	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T44	0	6	0	0
T46	2675	0	0	0
T47	443	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T110	0	1	0	0
T141	0	2	0	0
T187	0	1	0	0
T188	434	0	0	0
T196	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	9777595	0	0
T1	15812	15381	0	0
T2	136155	134552	0	0
T3	23948	21508	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	15579	0	0
T13	2041	438	0	0
T14	502	101	0	0
T15	5417	5016	0	0
T16	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	9779982	0	0
T1	15812	15387	0	0
T2	136155	134555	0	0
T3	23948	21518	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	105	0	0
T7	907	1	0	0
T8	12734	0	0	0
T27	0	1	0	0
T28	11763	0	0	0
T29	5617	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T44	0	6	0	0
T46	2675	0	0	0
T47	443	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T80	0	1	0	0
T110	0	1	0	0
T187	0	1	0	0
T188	434	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	98	0	0
T7	907	1	0	0
T8	12734	0	0	0
T27	0	1	0	0
T28	11763	0	0	0
T29	5617	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T44	0	6	0	0
T46	2675	0	0	0
T47	443	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T80	0	1	0	0
T110	0	1	0	0
T187	0	1	0	0
T188	434	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	95	0	0
T7	907	1	0	0
T8	12734	0	0	0
T28	11763	0	0	0
T29	5617	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T44	0	6	0	0
T46	2675	0	0	0
T47	443	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T110	0	1	0	0
T141	0	2	0	0
T187	0	1	0	0
T188	434	0	0	0
T196	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	95	0	0
T7	907	1	0	0
T8	12734	0	0	0
T28	11763	0	0	0
T29	5617	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T44	0	6	0	0
T46	2675	0	0	0
T47	443	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T110	0	1	0	0
T141	0	2	0	0
T187	0	1	0	0
T188	434	0	0	0
T196	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10960	0	0
T7	907	295	0	0
T8	12734	0	0	0
T28	11763	0	0	0
T29	5617	0	0	0
T38	0	24	0	0
T39	0	93	0	0
T41	0	161	0	0
T42	0	43	0	0
T44	0	451	0	0
T46	2675	0	0	0
T47	443	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T110	0	40	0	0
T141	0	311	0	0
T187	0	15	0	0
T188	434	0	0	0
T196	0	131	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10234697	0	0
T1	15812	15387	0	0
T2	136155	134555	0	0
T3	23948	21518	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	55	0	0
T37	638	0	0	0
T39	0	1	0	0
T41	784	1	0	0
T42	0	1	0	0
T43	3210	0	0	0
T44	0	4	0	0
T52	7455	0	0	0
T65	505	0	0	0
T76	0	4	0	0
T86	5266	0	0	0
T87	5175	0	0	0
T118	0	1	0	0
T141	0	1	0	0
T143	0	2	0	0
T164	954	0	0	0
T165	599	0	0	0
T166	32868	0	0	0
T183	0	2	0	0
T187	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T21,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T21,T27

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T21,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T40
1	0	Covered	T4,T5,T1
1	1	Covered	T2,T21,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T21,T27
0	1	Covered	T76,T149,T206
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T21,T27
0	1	Covered	T2,T21,T43
1	0	Covered	T38,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T21,T27
1	-	Covered	T2,T21,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T21,T27
DetectSt	168	Covered	T2,T21,T27
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T21,T27

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T21,T27
DebounceSt->IdleSt	163	Covered	T76,T177,T207
DetectSt->IdleSt	186	Covered	T76,T149,T206
DetectSt->StableSt	191	Covered	T2,T21,T27
IdleSt->DebounceSt	148	Covered	T2,T21,T27
StableSt->IdleSt	206	Covered	T2,T21,T27

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T21,T27
0	1	Covered	T2,T21,T27
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T21,T27
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T21,T27
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T21,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T76,T177,T207
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T21,T27
DetectSt	-	-	-	-	1	-	-	Covered	T76,T149,T206
DetectSt	-	-	-	-	0	1	-	Covered	T2,T21,T27
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T21,T43
StableSt	-	-	-	-	-	-	0	Covered	T2,T21,T27
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10916984	137	0	0
CntIncr_A	10916984	79079	0	0
CntNoWrap_A	10916984	10232093	0	0
DetectStDropOut_A	10916984	3	0	0
DetectedOut_A	10916984	47620	0	0
DetectedPulseOut_A	10916984	64	0	0
DisabledIdleSt_A	10916984	9969659	0	0
DisabledNoDetection_A	10916984	9972048	0	0
EnterDebounceSt_A	10916984	70	0	0
EnterDetectSt_A	10916984	67	0	0
EnterStableSt_A	10916984	64	0	0
PulseIsPulse_A	10916984	64	0	0
StayInStableSt	10916984	47517	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	10916984	6429	0	0
gen_low_level_sva.LowLevelEvent_A	10916984	10234697	0	0
gen_not_sticky_sva.StableStDropOut_A	10916984	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	137	0	0
T2	136155	2	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	4	0	0
T27	0	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T42	0	2	0	0
T43	0	4	0	0
T44	0	4	0	0
T46	2675	0	0	0
T187	0	2	0	0
T198	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	79079	0	0
T2	136155	21089	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	120	0	0
T27	0	90	0	0
T38	0	20	0	0
T39	0	90	0	0
T42	0	43	0	0
T43	0	144	0	0
T44	0	143	0	0
T46	2675	0	0	0
T187	0	30	0	0
T198	0	90	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10232093	0	0
T1	15812	15381	0	0
T2	136155	134550	0	0
T3	23948	21508	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	15579	0	0
T13	2041	438	0	0
T14	502	101	0	0
T15	5417	5016	0	0
T16	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	3	0	0
T76	119982	1	0	0
T119	547	0	0	0
T149	0	1	0	0
T206	0	1	0	0
T208	498	0	0	0
T209	3267	0	0	0
T210	489	0	0	0
T211	705	0	0	0
T212	485	0	0	0
T213	1630	0	0	0
T214	65042	0	0	0
T215	855	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	47620	0	0
T2	136155	42701	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	161	0	0
T27	0	37	0	0
T38	0	27	0	0
T39	0	364	0	0
T42	0	96	0	0
T43	0	206	0	0
T44	0	163	0	0
T46	2675	0	0	0
T187	0	38	0	0
T198	0	216	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	64	0	0
T2	136155	1	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	2	0	0
T27	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T46	2675	0	0	0
T187	0	1	0	0
T198	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	9969659	0	0
T1	15812	15381	0	0
T2	136155	128	0	0
T3	23948	21508	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	15579	0	0
T13	2041	438	0	0
T14	502	101	0	0
T15	5417	5016	0	0
T16	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	9972048	0	0
T1	15812	15387	0	0
T2	136155	130	0	0
T3	23948	21518	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	70	0	0
T2	136155	1	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	2	0	0
T27	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T46	2675	0	0	0
T187	0	1	0	0
T198	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	67	0	0
T2	136155	1	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	2	0	0
T27	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T46	2675	0	0	0
T187	0	1	0	0
T198	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	64	0	0
T2	136155	1	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	2	0	0
T27	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T46	2675	0	0	0
T187	0	1	0	0
T198	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	64	0	0
T2	136155	1	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	2	0	0
T27	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T46	2675	0	0	0
T187	0	1	0	0
T198	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	47517	0	0
T2	136155	42700	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	158	0	0
T27	0	35	0	0
T38	0	26	0	0
T39	0	363	0	0
T42	0	94	0	0
T43	0	204	0	0
T44	0	159	0	0
T46	2675	0	0	0
T187	0	36	0	0
T198	0	214	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	6429	0	0
T1	15812	11	0	0
T2	136155	7	0	0
T3	23948	23	0	0
T4	3530	6	0	0
T5	422	1	0	0
T6	16014	9	0	0
T13	2041	9	0	0
T14	502	3	0	0
T15	5417	30	0	0
T16	505	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10234697	0	0
T1	15812	15387	0	0
T2	136155	134555	0	0
T3	23948	21518	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	23	0	0
T2	136155	1	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	1	0	0
T39	0	1	0	0
T43	0	2	0	0
T46	2675	0	0	0
T126	0	1	0	0
T143	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0
T152	0	1	0	0
T159	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T21,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T21,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T21,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T21
1	0	Covered	T4,T5,T1
1	1	Covered	T2,T21,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T21,T34
0	1	Covered	T179,T216,T136
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T21,T34
0	1	Covered	T2,T21,T34
1	0	Covered	T38,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T21,T34
1	-	Covered	T2,T21,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T21,T34
DetectSt	168	Covered	T2,T21,T34
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T21,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T21,T34
DebounceSt->IdleSt	163	Covered	T39,T118,T162
DetectSt->IdleSt	186	Covered	T179,T216,T136
DetectSt->StableSt	191	Covered	T2,T21,T34
IdleSt->DebounceSt	148	Covered	T2,T21,T34
StableSt->IdleSt	206	Covered	T2,T21,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T21,T34
0	1	Covered	T2,T21,T34
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T21,T34
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T21,T34
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T21,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T39,T118,T162
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T21,T34
DetectSt	-	-	-	-	1	-	-	Covered	T179,T216,T136
DetectSt	-	-	-	-	0	1	-	Covered	T2,T21,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T21,T34
StableSt	-	-	-	-	-	-	0	Covered	T2,T21,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10916984	170	0	0
CntIncr_A	10916984	46933	0	0
CntNoWrap_A	10916984	10232060	0	0
DetectStDropOut_A	10916984	4	0	0
DetectedOut_A	10916984	30886	0	0
DetectedPulseOut_A	10916984	78	0	0
DisabledIdleSt_A	10916984	10075496	0	0
DisabledNoDetection_A	10916984	10077893	0	0
EnterDebounceSt_A	10916984	88	0	0
EnterDetectSt_A	10916984	82	0	0
EnterStableSt_A	10916984	78	0	0
PulseIsPulse_A	10916984	78	0	0
StayInStableSt	10916984	30766	0	0
gen_high_level_sva.HighLevelEvent_A	10916984	10234697	0	0
gen_not_sticky_sva.StableStDropOut_A	10916984	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	170	0	0
T2	136155	4	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	8	0	0
T34	0	2	0	0
T37	0	2	0	0
T38	0	2	0	0
T39	0	3	0	0
T42	0	4	0	0
T43	0	4	0	0
T44	0	8	0	0
T46	2675	0	0	0
T110	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	46933	0	0
T2	136155	42178	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	205	0	0
T34	0	11	0	0
T37	0	77	0	0
T38	0	20	0	0
T39	0	180	0	0
T42	0	86	0	0
T43	0	144	0	0
T44	0	200	0	0
T46	2675	0	0	0
T110	0	71	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10232060	0	0
T1	15812	15381	0	0
T2	136155	134548	0	0
T3	23948	21508	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	15579	0	0
T13	2041	438	0	0
T14	502	101	0	0
T15	5417	5016	0	0
T16	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	4	0	0
T136	0	1	0	0
T179	523	1	0	0
T206	0	1	0	0
T216	0	1	0	0
T217	472	0	0	0
T218	502	0	0	0
T219	1048	0	0	0
T220	628	0	0	0
T221	2707	0	0	0
T222	640	0	0	0
T223	4408	0	0	0
T224	22134	0	0	0
T225	659	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	30886	0	0
T2	136155	24985	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	157	0	0
T34	0	9	0	0
T37	0	33	0	0
T38	0	25	0	0
T39	0	200	0	0
T42	0	97	0	0
T43	0	169	0	0
T44	0	171	0	0
T46	2675	0	0	0
T110	0	115	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	78	0	0
T2	136155	2	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	4	0	0
T34	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	0	2	0	0
T43	0	2	0	0
T44	0	4	0	0
T46	2675	0	0	0
T110	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10075496	0	0
T1	15812	15381	0	0
T2	136155	128	0	0
T3	23948	21508	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	15579	0	0
T13	2041	438	0	0
T14	502	101	0	0
T15	5417	5016	0	0
T16	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10077893	0	0
T1	15812	15387	0	0
T2	136155	130	0	0
T3	23948	21518	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	88	0	0
T2	136155	2	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	4	0	0
T34	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	2	0	0
T42	0	2	0	0
T43	0	2	0	0
T44	0	4	0	0
T46	2675	0	0	0
T110	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	82	0	0
T2	136155	2	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	4	0	0
T34	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	0	2	0	0
T43	0	2	0	0
T44	0	4	0	0
T46	2675	0	0	0
T110	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	78	0	0
T2	136155	2	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	4	0	0
T34	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	0	2	0	0
T43	0	2	0	0
T44	0	4	0	0
T46	2675	0	0	0
T110	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	78	0	0
T2	136155	2	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	4	0	0
T34	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	0	2	0	0
T43	0	2	0	0
T44	0	4	0	0
T46	2675	0	0	0
T110	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	30766	0	0
T2	136155	24982	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	151	0	0
T34	0	8	0	0
T37	0	32	0	0
T38	0	24	0	0
T39	0	198	0	0
T42	0	94	0	0
T43	0	167	0	0
T44	0	165	0	0
T46	2675	0	0	0
T110	0	113	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10234697	0	0
T1	15812	15387	0	0
T2	136155	134555	0	0
T3	23948	21518	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	34	0	0
T2	136155	1	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	2	0	0
T34	0	1	0	0
T37	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T46	2675	0	0	0
T80	0	1	0	0
T141	0	2	0	0
T198	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T21,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T21,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T21,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T40,T21
1	0	Covered	T4,T5,T1
1	1	Covered	T2,T21,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T21,T35
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T21,T35
0	1	Covered	T2,T21,T39
1	0	Covered	T38,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T21,T35
1	-	Covered	T2,T21,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T21,T35
DetectSt	168	Covered	T2,T21,T35
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T21,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T21,T35
DebounceSt->IdleSt	163	Covered	T44
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T2,T21,T35
IdleSt->DebounceSt	148	Covered	T2,T21,T35
StableSt->IdleSt	206	Covered	T2,T21,T27

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T21,T35
0	1	Covered	T2,T21,T35
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T21,T35
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T21,T35
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T21,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T44
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T21,T35
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T2,T21,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T21,T38
StableSt	-	-	-	-	-	-	0	Covered	T2,T21,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10916984	99	0	0
CntIncr_A	10916984	102150	0	0
CntNoWrap_A	10916984	10232131	0	0
DetectStDropOut_A	10916984	0	0	0
DetectedOut_A	10916984	69161	0	0
DetectedPulseOut_A	10916984	49	0	0
DisabledIdleSt_A	10916984	9646538	0	0
DisabledNoDetection_A	10916984	9648938	0	0
EnterDebounceSt_A	10916984	50	0	0
EnterDetectSt_A	10916984	49	0	0
EnterStableSt_A	10916984	49	0	0
PulseIsPulse_A	10916984	49	0	0
StayInStableSt	10916984	69091	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	10916984	6389	0	0
gen_low_level_sva.LowLevelEvent_A	10916984	10234697	0	0
gen_not_sticky_sva.StableStDropOut_A	10916984	26	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	99	0	0
T2	136155	2	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	4	0	0
T27	0	2	0	0
T35	0	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T41	0	2	0	0
T44	0	5	0	0
T46	2675	0	0	0
T126	0	4	0	0
T141	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	102150	0	0
T2	136155	21089	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	120	0	0
T27	0	90	0	0
T35	0	22	0	0
T38	0	20	0	0
T39	0	90	0	0
T41	0	69	0	0
T44	0	201	0	0
T46	2675	0	0	0
T126	0	74	0	0
T141	0	120	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10232131	0	0
T1	15812	15381	0	0
T2	136155	134550	0	0
T3	23948	21508	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	15579	0	0
T13	2041	438	0	0
T14	502	101	0	0
T15	5417	5016	0	0
T16	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	69161	0	0
T2	136155	40	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	159	0	0
T27	0	38	0	0
T35	0	92	0	0
T38	0	25	0	0
T39	0	352	0	0
T41	0	126	0	0
T44	0	305	0	0
T46	2675	0	0	0
T126	0	82	0	0
T141	0	88	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	49	0	0
T2	136155	1	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	2	0	0
T27	0	1	0	0
T35	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T44	0	2	0	0
T46	2675	0	0	0
T126	0	2	0	0
T141	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	9646538	0	0
T1	15812	15381	0	0
T2	136155	128	0	0
T3	23948	21508	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	15579	0	0
T13	2041	438	0	0
T14	502	101	0	0
T15	5417	5016	0	0
T16	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	9648938	0	0
T1	15812	15387	0	0
T2	136155	130	0	0
T3	23948	21518	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	50	0	0
T2	136155	1	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	2	0	0
T27	0	1	0	0
T35	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T44	0	3	0	0
T46	2675	0	0	0
T126	0	2	0	0
T141	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	49	0	0
T2	136155	1	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	2	0	0
T27	0	1	0	0
T35	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T44	0	2	0	0
T46	2675	0	0	0
T126	0	2	0	0
T141	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	49	0	0
T2	136155	1	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	2	0	0
T27	0	1	0	0
T35	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T44	0	2	0	0
T46	2675	0	0	0
T126	0	2	0	0
T141	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	49	0	0
T2	136155	1	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	2	0	0
T27	0	1	0	0
T35	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T44	0	2	0	0
T46	2675	0	0	0
T126	0	2	0	0
T141	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	69091	0	0
T2	136155	39	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	157	0	0
T27	0	36	0	0
T35	0	90	0	0
T38	0	24	0	0
T39	0	351	0	0
T41	0	124	0	0
T44	0	302	0	0
T46	2675	0	0	0
T126	0	79	0	0
T141	0	85	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	6389	0	0
T1	15812	10	0	0
T2	136155	6	0	0
T3	23948	25	0	0
T4	3530	7	0	0
T5	422	3	0	0
T6	16014	11	0	0
T13	2041	5	0	0
T14	502	3	0	0
T15	5417	23	0	0
T16	505	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10234697	0	0
T1	15812	15387	0	0
T2	136155	134555	0	0
T3	23948	21518	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	26	0	0
T2	136155	1	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	2	0	0
T39	0	1	0	0
T44	0	1	0	0
T46	2675	0	0	0
T76	0	1	0	0
T126	0	1	0	0
T141	0	1	0	0
T145	0	1	0	0
T185	0	1	0	0
T186	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T7,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T7,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T7,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T40
1	0	Covered	T4,T5,T1
1	1	Covered	T2,T7,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T40
0	1	Covered	T183,T181,T134
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T40
0	1	Covered	T2,T7,T21
1	0	Covered	T38,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T7,T40
1	-	Covered	T2,T7,T21

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T7,T40
DetectSt	168	Covered	T2,T7,T40
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T7,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T7,T40
DebounceSt->IdleSt	163	Covered	T27,T42,T183
DetectSt->IdleSt	186	Covered	T183,T181,T134
DetectSt->StableSt	191	Covered	T2,T7,T40
IdleSt->DebounceSt	148	Covered	T2,T7,T40
StableSt->IdleSt	206	Covered	T2,T7,T21

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T7,T40
0	1	Covered	T2,T7,T40
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T40
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T7,T40
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T7,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T27,T42,T183
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T7,T40
DetectSt	-	-	-	-	1	-	-	Covered	T183,T181,T134
DetectSt	-	-	-	-	0	1	-	Covered	T2,T7,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T7,T21
StableSt	-	-	-	-	-	-	0	Covered	T2,T7,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10916984	184	0	0
CntIncr_A	10916984	143940	0	0
CntNoWrap_A	10916984	10232046	0	0
DetectStDropOut_A	10916984	3	0	0
DetectedOut_A	10916984	74248	0	0
DetectedPulseOut_A	10916984	85	0	0
DisabledIdleSt_A	10916984	9812731	0	0
DisabledNoDetection_A	10916984	9815124	0	0
EnterDebounceSt_A	10916984	96	0	0
EnterDetectSt_A	10916984	88	0	0
EnterStableSt_A	10916984	85	0	0
PulseIsPulse_A	10916984	85	0	0
StayInStableSt	10916984	74122	0	0
gen_high_level_sva.HighLevelEvent_A	10916984	10234697	0	0
gen_not_sticky_sva.StableStDropOut_A	10916984	42	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	184	0	0
T2	136155	2	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	4	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	8	0	0
T27	0	3	0	0
T36	0	2	0	0
T37	0	2	0	0
T40	0	2	0	0
T42	0	3	0	0
T43	0	2	0	0
T46	2675	0	0	0
T187	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	143940	0	0
T2	136155	21089	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	192	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	205	0	0
T27	0	162	0	0
T36	0	44	0	0
T37	0	77	0	0
T40	0	45	0	0
T42	0	86	0	0
T43	0	72	0	0
T46	2675	0	0	0
T187	0	30	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10232046	0	0
T1	15812	15381	0	0
T2	136155	134550	0	0
T3	23948	21508	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	15579	0	0
T13	2041	438	0	0
T14	502	101	0	0
T15	5417	5016	0	0
T16	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	3	0	0
T120	2026	0	0	0
T134	0	1	0	0
T181	0	1	0	0
T183	2509	1	0	0
T226	709	0	0	0
T227	412	0	0	0
T228	667	0	0	0
T229	20180	0	0	0
T230	423	0	0	0
T231	734	0	0	0
T232	16786	0	0	0
T233	23798	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	74248	0	0
T2	136155	67203	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	102	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	156	0	0
T27	0	167	0	0
T36	0	45	0	0
T37	0	40	0	0
T40	0	43	0	0
T42	0	40	0	0
T43	0	52	0	0
T46	2675	0	0	0
T187	0	14	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	85	0	0
T2	136155	1	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	2	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	4	0	0
T27	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T46	2675	0	0	0
T187	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	9812731	0	0
T1	15812	15381	0	0
T2	136155	128	0	0
T3	23948	21508	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	15579	0	0
T13	2041	438	0	0
T14	502	101	0	0
T15	5417	5016	0	0
T16	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	9815124	0	0
T1	15812	15387	0	0
T2	136155	130	0	0
T3	23948	21518	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	96	0	0
T2	136155	1	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	2	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	4	0	0
T27	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T46	2675	0	0	0
T187	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	88	0	0
T2	136155	1	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	2	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	4	0	0
T27	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T46	2675	0	0	0
T187	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	85	0	0
T2	136155	1	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	2	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	4	0	0
T27	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T46	2675	0	0	0
T187	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	85	0	0
T2	136155	1	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	2	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	4	0	0
T27	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T46	2675	0	0	0
T187	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	74122	0	0
T2	136155	67202	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	99	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	150	0	0
T27	0	165	0	0
T36	0	43	0	0
T37	0	38	0	0
T40	0	41	0	0
T42	0	38	0	0
T43	0	51	0	0
T46	2675	0	0	0
T187	0	13	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10234697	0	0
T1	15812	15387	0	0
T2	136155	134555	0	0
T3	23948	21518	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	42	0	0
T2	136155	1	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	1	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	2	0	0
T39	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T46	2675	0	0	0
T76	0	1	0	0
T160	0	1	0	0
T187	0	1	0	0
T190	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T21,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T21,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T21,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T21
1	0	Covered	T4,T5,T1
1	1	Covered	T2,T21,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T21,T34
0	1	Covered	T44,T151
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T21,T34
0	1	Covered	T21,T44,T126
1	0	Covered	T38,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T21,T34
1	-	Covered	T21,T44,T126

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T21,T34
DetectSt	168	Covered	T2,T21,T34
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T21,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T21,T34
DebounceSt->IdleSt	163	Covered	T76
DetectSt->IdleSt	186	Covered	T44,T151
DetectSt->StableSt	191	Covered	T2,T21,T34
IdleSt->DebounceSt	148	Covered	T2,T21,T34
StableSt->IdleSt	206	Covered	T21,T34,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T21,T34
0	1	Covered	T2,T21,T34
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T21,T34
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T21,T34
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T21,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T76
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T21,T34
DetectSt	-	-	-	-	1	-	-	Covered	T44,T151
DetectSt	-	-	-	-	0	1	-	Covered	T2,T21,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T21,T38,T44
StableSt	-	-	-	-	-	-	0	Covered	T2,T21,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10916984	129	0	0
CntIncr_A	10916984	24615	0	0
CntNoWrap_A	10916984	10232101	0	0
DetectStDropOut_A	10916984	2	0	0
DetectedOut_A	10916984	4686	0	0
DetectedPulseOut_A	10916984	62	0	0
DisabledIdleSt_A	10916984	9968792	0	0
DisabledNoDetection_A	10916984	9971179	0	0
EnterDebounceSt_A	10916984	65	0	0
EnterDetectSt_A	10916984	64	0	0
EnterStableSt_A	10916984	62	0	0
PulseIsPulse_A	10916984	62	0	0
StayInStableSt	10916984	4592	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	10916984	7059	0	0
gen_low_level_sva.LowLevelEvent_A	10916984	10234697	0	0
gen_not_sticky_sva.StableStDropOut_A	10916984	28	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	129	0	0
T2	136155	2	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	4	0	0
T34	0	2	0	0
T38	0	2	0	0
T41	0	2	0	0
T43	0	2	0	0
T44	0	8	0	0
T46	2675	0	0	0
T126	0	2	0	0
T187	0	2	0	0
T198	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	24615	0	0
T2	136155	21089	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	120	0	0
T34	0	11	0	0
T38	0	20	0	0
T41	0	69	0	0
T43	0	72	0	0
T44	0	285	0	0
T46	2675	0	0	0
T126	0	37	0	0
T187	0	30	0	0
T198	0	90	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10232101	0	0
T1	15812	15381	0	0
T2	136155	134550	0	0
T3	23948	21508	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	15579	0	0
T13	2041	438	0	0
T14	502	101	0	0
T15	5417	5016	0	0
T16	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	2	0	0
T44	20919	1	0	0
T67	490	0	0	0
T68	498	0	0	0
T109	16782	0	0	0
T151	0	1	0	0
T234	502	0	0	0
T235	421	0	0	0
T236	404	0	0	0
T237	409	0	0	0
T238	29524	0	0	0
T239	415	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	4686	0	0
T2	136155	45	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	160	0	0
T34	0	40	0	0
T38	0	26	0	0
T41	0	125	0	0
T43	0	43	0	0
T44	0	98	0	0
T46	2675	0	0	0
T126	0	21	0	0
T187	0	39	0	0
T198	0	217	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	62	0	0
T2	136155	1	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	2	0	0
T34	0	1	0	0
T38	0	1	0	0
T41	0	1	0	0
T43	0	1	0	0
T44	0	3	0	0
T46	2675	0	0	0
T126	0	1	0	0
T187	0	1	0	0
T198	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	9968792	0	0
T1	15812	15381	0	0
T2	136155	128	0	0
T3	23948	21508	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	15579	0	0
T13	2041	438	0	0
T14	502	101	0	0
T15	5417	5016	0	0
T16	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	9971179	0	0
T1	15812	15387	0	0
T2	136155	130	0	0
T3	23948	21518	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	65	0	0
T2	136155	1	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	2	0	0
T34	0	1	0	0
T38	0	1	0	0
T41	0	1	0	0
T43	0	1	0	0
T44	0	4	0	0
T46	2675	0	0	0
T126	0	1	0	0
T187	0	1	0	0
T198	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	64	0	0
T2	136155	1	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	2	0	0
T34	0	1	0	0
T38	0	1	0	0
T41	0	1	0	0
T43	0	1	0	0
T44	0	4	0	0
T46	2675	0	0	0
T126	0	1	0	0
T187	0	1	0	0
T198	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	62	0	0
T2	136155	1	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	2	0	0
T34	0	1	0	0
T38	0	1	0	0
T41	0	1	0	0
T43	0	1	0	0
T44	0	3	0	0
T46	2675	0	0	0
T126	0	1	0	0
T187	0	1	0	0
T198	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	62	0	0
T2	136155	1	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	2	0	0
T34	0	1	0	0
T38	0	1	0	0
T41	0	1	0	0
T43	0	1	0	0
T44	0	3	0	0
T46	2675	0	0	0
T126	0	1	0	0
T187	0	1	0	0
T198	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	4592	0	0
T2	136155	43	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	158	0	0
T34	0	38	0	0
T38	0	25	0	0
T41	0	123	0	0
T43	0	41	0	0
T44	0	93	0	0
T46	2675	0	0	0
T126	0	20	0	0
T187	0	37	0	0
T198	0	215	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	7059	0	0
T1	15812	11	0	0
T2	136155	5	0	0
T3	23948	25	0	0
T4	3530	18	0	0
T5	422	1	0	0
T6	16014	13	0	0
T13	2041	12	0	0
T14	502	5	0	0
T15	5417	30	0	0
T16	505	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10234697	0	0
T1	15812	15387	0	0
T2	136155	134555	0	0
T3	23948	21518	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	28	0	0
T21	12771	2	0	0
T22	190347	0	0	0
T26	584	0	0	0
T31	17816	0	0	0
T34	2781	0	0	0
T35	625	0	0	0
T36	526	0	0	0
T44	0	1	0	0
T72	5667	0	0	0
T76	0	1	0	0
T112	406	0	0	0
T113	444	0	0	0
T126	0	1	0	0
T144	0	1	0	0
T146	0	2	0	0
T152	0	1	0	0
T177	0	1	0	0
T183	0	2	0	0
T194	0	1	0	0