Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T15,T28,T29
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T15,T28,T29

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T15,T28,T29

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T15,T28,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T28,T29
1	0	Covered	T28,T10,T12
1	1	Covered	T15,T28,T29

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T28,T29
0	1	Covered	T15,T29,T10
1	0	Covered	T10,T85,T240

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T12,T45
0	1	Covered	T28,T12,T45
1	0	Covered	T78

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T28,T12,T45
1	-	Covered	T28,T12,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T15,T28,T29
DetectSt	168	Covered	T15,T28,T29
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T28,T12,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T15,T28,T29
DebounceSt->IdleSt	163	Covered	T45,T38,T241
DetectSt->IdleSt	186	Covered	T15,T29,T10
DetectSt->StableSt	191	Covered	T28,T12,T45
IdleSt->DebounceSt	148	Covered	T15,T28,T29
StableSt->IdleSt	206	Covered	T28,T12,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T15,T28,T29
0	1	Covered	T15,T28,T29
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T28,T29
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T15,T28,T29
IdleSt	0	-	-	-	-	-	-	Covered	T15,T28,T29
DebounceSt	-	1	-	-	-	-	-	Covered	T38,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T28,T29
DebounceSt	-	0	1	0	-	-	-	Covered	T45,T38,T241
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T28,T29
DetectSt	-	-	-	-	1	-	-	Covered	T15,T29,T10
DetectSt	-	-	-	-	0	1	-	Covered	T28,T12,T45
DetectSt	-	-	-	-	0	0	-	Covered	T15,T28,T29
StableSt	-	-	-	-	-	-	1	Covered	T28,T12,T45
StableSt	-	-	-	-	-	-	0	Covered	T28,T12,T45
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10916984	3200	0	0
CntIncr_A	10916984	115973	0	0
CntNoWrap_A	10916984	10229030	0	0
DetectStDropOut_A	10916984	494	0	0
DetectedOut_A	10916984	70999	0	0
DetectedPulseOut_A	10916984	838	0	0
DisabledIdleSt_A	10916984	9778674	0	0
DisabledNoDetection_A	10916984	9780933	0	0
EnterDebounceSt_A	10916984	1633	0	0
EnterDetectSt_A	10916984	1571	0	0
EnterStableSt_A	10916984	838	0	0
PulseIsPulse_A	10916984	838	0	0
StayInStableSt	10916984	70046	0	0
gen_high_event_sva.HighLevelEvent_A	10916984	10234697	0	0
gen_high_level_sva.HighLevelEvent_A	10916984	10234697	0	0
gen_not_sticky_sva.StableStDropOut_A	10916984	720	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	3200	0	0
T6	16014	0	0	0
T7	907	0	0	0
T10	0	52	0	0
T12	0	50	0	0
T15	5417	52	0	0
T16	505	0	0	0
T17	502	0	0	0
T28	11763	28	0	0
T29	0	16	0	0
T32	0	36	0	0
T33	0	20	0	0
T45	0	18	0	0
T46	2675	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T72	0	40	0	0
T73	0	50	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	115973	0	0
T6	16014	0	0	0
T7	907	0	0	0
T10	0	1601	0	0
T12	0	1225	0	0
T15	5417	1459	0	0
T16	505	0	0	0
T17	502	0	0	0
T28	11763	812	0	0
T29	0	473	0	0
T32	0	1062	0	0
T33	0	800	0	0
T45	0	4236	0	0
T46	2675	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T72	0	1223	0	0
T73	0	1075	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10229030	0	0
T1	15812	15381	0	0
T2	136155	134552	0	0
T3	23948	21508	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	15579	0	0
T13	2041	438	0	0
T14	502	101	0	0
T15	5417	4964	0	0
T16	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	494	0	0
T6	16014	0	0	0
T7	907	0	0	0
T10	0	13	0	0
T15	5417	26	0	0
T16	505	0	0	0
T17	502	0	0	0
T28	11763	0	0	0
T29	0	8	0	0
T38	0	1	0	0
T46	2675	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T72	0	20	0	0
T84	0	13	0	0
T85	0	8	0	0
T86	0	17	0	0
T87	0	24	0	0
T89	0	7	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	70999	0	0
T8	12734	0	0	0
T12	0	3452	0	0
T23	490	0	0	0
T28	11763	2101	0	0
T29	5617	0	0	0
T32	0	1139	0	0
T33	0	134	0	0
T45	0	177	0	0
T47	443	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T56	524	0	0	0
T73	0	2184	0	0
T75	0	1366	0	0
T77	0	648	0	0
T78	0	815	0	0
T188	434	0	0	0
T242	0	67	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	838	0	0
T8	12734	0	0	0
T12	0	25	0	0
T23	490	0	0	0
T28	11763	14	0	0
T29	5617	0	0	0
T32	0	18	0	0
T33	0	10	0	0
T45	0	5	0	0
T47	443	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T56	524	0	0	0
T73	0	25	0	0
T75	0	13	0	0
T77	0	21	0	0
T78	0	8	0	0
T188	434	0	0	0
T242	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	9778674	0	0
T1	15812	15381	0	0
T2	136155	134552	0	0
T3	23948	21508	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	15579	0	0
T13	2041	438	0	0
T14	502	101	0	0
T15	5417	2014	0	0
T16	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	9780933	0	0
T1	15812	15387	0	0
T2	136155	134555	0	0
T3	23948	21518	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	2014	0	0
T16	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	1633	0	0
T6	16014	0	0	0
T7	907	0	0	0
T10	0	26	0	0
T12	0	25	0	0
T15	5417	26	0	0
T16	505	0	0	0
T17	502	0	0	0
T28	11763	14	0	0
T29	0	8	0	0
T32	0	18	0	0
T33	0	10	0	0
T45	0	14	0	0
T46	2675	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T72	0	20	0	0
T73	0	25	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	1571	0	0
T6	16014	0	0	0
T7	907	0	0	0
T10	0	26	0	0
T12	0	25	0	0
T15	5417	26	0	0
T16	505	0	0	0
T17	502	0	0	0
T28	11763	14	0	0
T29	0	8	0	0
T32	0	18	0	0
T33	0	10	0	0
T45	0	5	0	0
T46	2675	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T72	0	20	0	0
T73	0	25	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	838	0	0
T8	12734	0	0	0
T12	0	25	0	0
T23	490	0	0	0
T28	11763	14	0	0
T29	5617	0	0	0
T32	0	18	0	0
T33	0	10	0	0
T45	0	5	0	0
T47	443	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T56	524	0	0	0
T73	0	25	0	0
T75	0	13	0	0
T77	0	21	0	0
T78	0	8	0	0
T188	434	0	0	0
T242	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	838	0	0
T8	12734	0	0	0
T12	0	25	0	0
T23	490	0	0	0
T28	11763	14	0	0
T29	5617	0	0	0
T32	0	18	0	0
T33	0	10	0	0
T45	0	5	0	0
T47	443	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T56	524	0	0	0
T73	0	25	0	0
T75	0	13	0	0
T77	0	21	0	0
T78	0	8	0	0
T188	434	0	0	0
T242	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	70046	0	0
T8	12734	0	0	0
T12	0	3416	0	0
T23	490	0	0	0
T28	11763	2086	0	0
T29	5617	0	0	0
T32	0	1119	0	0
T33	0	124	0	0
T45	0	172	0	0
T47	443	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T56	524	0	0	0
T73	0	2153	0	0
T75	0	1353	0	0
T77	0	626	0	0
T78	0	807	0	0
T188	434	0	0	0
T242	0	64	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10234697	0	0
T1	15812	15387	0	0
T2	136155	134555	0	0
T3	23948	21518	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10234697	0	0
T1	15812	15387	0	0
T2	136155	134555	0	0
T3	23948	21518	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	720	0	0
T8	12734	0	0	0
T12	0	14	0	0
T23	490	0	0	0
T28	11763	13	0	0
T29	5617	0	0	0
T32	0	16	0	0
T33	0	10	0	0
T45	0	5	0	0
T47	443	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T56	524	0	0	0
T73	0	19	0	0
T75	0	13	0	0
T77	0	20	0	0
T78	0	5	0	0
T188	434	0	0	0
T242	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T15
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T3,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T3,T6

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T3,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T3,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T6
0	1	Covered	T1,T88,T90
1	0	Covered	T38,T58

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T28
0	1	Covered	T3,T6,T28
1	0	Covered	T75,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T6,T28
1	-	Covered	T3,T6,T28

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T6
DetectSt	168	Covered	T1,T3,T6
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T3,T6,T28

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T6
DebounceSt->IdleSt	163	Covered	T46,T47,T21
DetectSt->IdleSt	186	Covered	T1,T88,T38
DetectSt->StableSt	191	Covered	T3,T6,T28
IdleSt->DebounceSt	148	Covered	T1,T3,T6
StableSt->IdleSt	206	Covered	T3,T6,T28

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T6
0	1	Covered	T1,T3,T6
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T6
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T38,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T46,T47,T21
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T6
DetectSt	-	-	-	-	1	-	-	Covered	T1,T88,T38
DetectSt	-	-	-	-	0	1	-	Covered	T3,T6,T28
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T6
StableSt	-	-	-	-	-	-	1	Covered	T3,T6,T28
StableSt	-	-	-	-	-	-	0	Covered	T3,T6,T28
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10916984	865	0	0
CntIncr_A	10916984	42742	0	0
CntNoWrap_A	10916984	10231365	0	0
DetectStDropOut_A	10916984	31	0	0
DetectedOut_A	10916984	15904	0	0
DetectedPulseOut_A	10916984	361	0	0
DisabledIdleSt_A	10916984	9883161	0	0
DisabledNoDetection_A	10916984	9884899	0	0
EnterDebounceSt_A	10916984	471	0	0
EnterDetectSt_A	10916984	396	0	0
EnterStableSt_A	10916984	361	0	0
PulseIsPulse_A	10916984	361	0	0
StayInStableSt	10916984	15506	0	0
gen_high_level_sva.HighLevelEvent_A	10916984	10234697	0	0
gen_not_sticky_sva.StableStDropOut_A	10916984	320	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	865	0	0
T1	15812	4	0	0
T2	136155	0	0	0
T3	23948	14	0	0
T6	16014	4	0	0
T7	907	0	0	0
T8	0	8	0	0
T12	0	12	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	5	0	0
T28	0	2	0	0
T31	0	4	0	0
T46	0	2	0	0
T47	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	42742	0	0
T1	15812	241	0	0
T2	136155	0	0	0
T3	23948	539	0	0
T6	16014	216	0	0
T7	907	0	0	0
T8	0	252	0	0
T12	0	366	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	132	0	0
T28	0	58	0	0
T31	0	372	0	0
T46	0	40	0	0
T47	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10231365	0	0
T1	15812	15377	0	0
T2	136155	134552	0	0
T3	23948	21494	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	15575	0	0
T13	2041	438	0	0
T14	502	101	0	0
T15	5417	5016	0	0
T16	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	31	0	0
T1	15812	2	0	0
T2	136155	0	0	0
T3	23948	0	0	0
T6	16014	0	0	0
T7	907	0	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T88	0	4	0	0
T90	0	2	0	0
T92	0	5	0	0
T93	0	2	0	0
T94	0	1	0	0
T95	0	2	0	0
T96	0	4	0	0
T97	0	2	0	0
T98	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	15904	0	0
T3	23948	231	0	0
T6	16014	38	0	0
T7	907	0	0	0
T8	0	64	0	0
T12	0	411	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	12	0	0
T27	0	4	0	0
T28	11763	567	0	0
T31	0	38	0	0
T46	2675	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T73	0	404	0	0
T108	0	72	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	361	0	0
T3	23948	7	0	0
T6	16014	2	0	0
T7	907	0	0	0
T8	0	4	0	0
T12	0	6	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	2	0	0
T27	0	1	0	0
T28	11763	1	0	0
T31	0	2	0	0
T46	2675	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T73	0	6	0	0
T108	0	10	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	9883161	0	0
T1	15812	12088	0	0
T2	136155	134552	0	0
T3	23948	14803	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	12087	0	0
T13	2041	438	0	0
T14	502	101	0	0
T15	5417	5016	0	0
T16	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	9884899	0	0
T1	15812	12088	0	0
T2	136155	134555	0	0
T3	23948	14806	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	12087	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	471	0	0
T1	15812	2	0	0
T2	136155	0	0	0
T3	23948	7	0	0
T6	16014	2	0	0
T7	907	0	0	0
T8	0	4	0	0
T12	0	6	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	3	0	0
T28	0	1	0	0
T31	0	2	0	0
T46	0	2	0	0
T47	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	396	0	0
T1	15812	2	0	0
T2	136155	0	0	0
T3	23948	7	0	0
T6	16014	2	0	0
T7	907	0	0	0
T8	0	4	0	0
T12	0	6	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	2	0	0
T27	0	1	0	0
T28	0	1	0	0
T31	0	2	0	0
T73	0	6	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	361	0	0
T3	23948	7	0	0
T6	16014	2	0	0
T7	907	0	0	0
T8	0	4	0	0
T12	0	6	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	2	0	0
T27	0	1	0	0
T28	11763	1	0	0
T31	0	2	0	0
T46	2675	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T73	0	6	0	0
T108	0	10	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	361	0	0
T3	23948	7	0	0
T6	16014	2	0	0
T7	907	0	0	0
T8	0	4	0	0
T12	0	6	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	2	0	0
T27	0	1	0	0
T28	11763	1	0	0
T31	0	2	0	0
T46	2675	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T73	0	6	0	0
T108	0	10	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	15506	0	0
T3	23948	224	0	0
T6	16014	36	0	0
T7	907	0	0	0
T8	0	60	0	0
T12	0	405	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	10	0	0
T27	0	3	0	0
T28	11763	566	0	0
T31	0	36	0	0
T46	2675	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T73	0	392	0	0
T108	0	61	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10234697	0	0
T1	15812	15387	0	0
T2	136155	134555	0	0
T3	23948	21518	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	320	0	0
T3	23948	7	0	0
T6	16014	2	0	0
T7	907	0	0	0
T8	0	4	0	0
T12	0	6	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	2	0	0
T27	0	1	0	0
T28	11763	1	0	0
T31	0	2	0	0
T46	2675	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T108	0	9	0	0
T115	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T15,T28,T29
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T15,T28,T29

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T15,T28,T29

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T15,T28,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T28,T29
1	0	Covered	T28,T10,T12
1	1	Covered	T15,T28,T29

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T28,T29
0	1	Covered	T15,T29,T10
1	0	Covered	T10,T75,T38

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T12,T45
0	1	Covered	T28,T12,T45
1	0	Covered	T38

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T28,T12,T45
1	-	Covered	T28,T12,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T15,T28,T29
DetectSt	168	Covered	T15,T28,T29
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T28,T12,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T15,T28,T29
DebounceSt->IdleSt	163	Covered	T45,T38,T241
DetectSt->IdleSt	186	Covered	T15,T29,T10
DetectSt->StableSt	191	Covered	T28,T12,T45
IdleSt->DebounceSt	148	Covered	T15,T28,T29
StableSt->IdleSt	206	Covered	T28,T12,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T15,T28,T29
0	1	Covered	T15,T28,T29
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T28,T29
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T15,T28,T29
IdleSt	0	-	-	-	-	-	-	Covered	T15,T28,T29
DebounceSt	-	1	-	-	-	-	-	Covered	T38,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T28,T29
DebounceSt	-	0	1	0	-	-	-	Covered	T45,T38,T241
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T28,T29
DetectSt	-	-	-	-	1	-	-	Covered	T15,T29,T10
DetectSt	-	-	-	-	0	1	-	Covered	T28,T12,T45
DetectSt	-	-	-	-	0	0	-	Covered	T15,T28,T29
StableSt	-	-	-	-	-	-	1	Covered	T28,T12,T45
StableSt	-	-	-	-	-	-	0	Covered	T28,T12,T45
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10916984	3111	0	0
CntIncr_A	10916984	112206	0	0
CntNoWrap_A	10916984	10229119	0	0
DetectStDropOut_A	10916984	441	0	0
DetectedOut_A	10916984	94516	0	0
DetectedPulseOut_A	10916984	927	0	0
DisabledIdleSt_A	10916984	9758768	0	0
DisabledNoDetection_A	10916984	9760998	0	0
EnterDebounceSt_A	10916984	1591	0	0
EnterDetectSt_A	10916984	1523	0	0
EnterStableSt_A	10916984	927	0	0
PulseIsPulse_A	10916984	927	0	0
StayInStableSt	10916984	93444	0	0
gen_high_event_sva.HighLevelEvent_A	10916984	10234697	0	0
gen_high_level_sva.HighLevelEvent_A	10916984	10234697	0	0
gen_not_sticky_sva.StableStDropOut_A	10916984	781	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	3111	0	0
T6	16014	0	0	0
T7	907	0	0	0
T10	0	18	0	0
T12	0	22	0	0
T15	5417	16	0	0
T16	505	0	0	0
T17	502	0	0	0
T28	11763	20	0	0
T29	0	26	0	0
T32	0	46	0	0
T33	0	16	0	0
T45	0	20	0	0
T46	2675	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T72	0	18	0	0
T73	0	18	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	112206	0	0
T6	16014	0	0	0
T7	907	0	0	0
T10	0	550	0	0
T12	0	550	0	0
T15	5417	442	0	0
T16	505	0	0	0
T17	502	0	0	0
T28	11763	510	0	0
T29	0	772	0	0
T32	0	1472	0	0
T33	0	616	0	0
T45	0	3736	0	0
T46	2675	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T72	0	542	0	0
T73	0	261	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10229119	0	0
T1	15812	15381	0	0
T2	136155	134552	0	0
T3	23948	21508	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	15579	0	0
T13	2041	438	0	0
T14	502	101	0	0
T15	5417	5000	0	0
T16	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	441	0	0
T6	16014	0	0	0
T7	907	0	0	0
T10	0	4	0	0
T15	5417	8	0	0
T16	505	0	0	0
T17	502	0	0	0
T28	11763	0	0	0
T29	0	13	0	0
T38	0	1	0	0
T46	2675	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T72	0	9	0	0
T75	0	8	0	0
T84	0	18	0	0
T86	0	30	0	0
T87	0	23	0	0
T89	0	7	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	94516	0	0
T8	12734	0	0	0
T12	0	869	0	0
T23	490	0	0	0
T28	11763	539	0	0
T29	5617	0	0	0
T32	0	1594	0	0
T33	0	128	0	0
T45	0	493	0	0
T47	443	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T56	524	0	0	0
T73	0	273	0	0
T77	0	2054	0	0
T78	0	6313	0	0
T85	0	350	0	0
T188	434	0	0	0
T242	0	1241	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	927	0	0
T8	12734	0	0	0
T12	0	11	0	0
T23	490	0	0	0
T28	11763	10	0	0
T29	5617	0	0	0
T32	0	23	0	0
T33	0	8	0	0
T45	0	8	0	0
T47	443	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T56	524	0	0	0
T73	0	9	0	0
T77	0	31	0	0
T78	0	22	0	0
T85	0	7	0	0
T188	434	0	0	0
T242	0	23	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	9758768	0	0
T1	15812	15381	0	0
T2	136155	134552	0	0
T3	23948	21508	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	15579	0	0
T13	2041	438	0	0
T14	502	101	0	0
T15	5417	2014	0	0
T16	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	9760998	0	0
T1	15812	15387	0	0
T2	136155	134555	0	0
T3	23948	21518	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	2014	0	0
T16	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	1591	0	0
T6	16014	0	0	0
T7	907	0	0	0
T10	0	9	0	0
T12	0	11	0	0
T15	5417	8	0	0
T16	505	0	0	0
T17	502	0	0	0
T28	11763	10	0	0
T29	0	13	0	0
T32	0	23	0	0
T33	0	8	0	0
T45	0	12	0	0
T46	2675	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T72	0	9	0	0
T73	0	9	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	1523	0	0
T6	16014	0	0	0
T7	907	0	0	0
T10	0	9	0	0
T12	0	11	0	0
T15	5417	8	0	0
T16	505	0	0	0
T17	502	0	0	0
T28	11763	10	0	0
T29	0	13	0	0
T32	0	23	0	0
T33	0	8	0	0
T45	0	8	0	0
T46	2675	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T72	0	9	0	0
T73	0	9	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	927	0	0
T8	12734	0	0	0
T12	0	11	0	0
T23	490	0	0	0
T28	11763	10	0	0
T29	5617	0	0	0
T32	0	23	0	0
T33	0	8	0	0
T45	0	8	0	0
T47	443	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T56	524	0	0	0
T73	0	9	0	0
T77	0	31	0	0
T78	0	22	0	0
T85	0	7	0	0
T188	434	0	0	0
T242	0	23	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	927	0	0
T8	12734	0	0	0
T12	0	11	0	0
T23	490	0	0	0
T28	11763	10	0	0
T29	5617	0	0	0
T32	0	23	0	0
T33	0	8	0	0
T45	0	8	0	0
T47	443	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T56	524	0	0	0
T73	0	9	0	0
T77	0	31	0	0
T78	0	22	0	0
T85	0	7	0	0
T188	434	0	0	0
T242	0	23	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	93444	0	0
T8	12734	0	0	0
T12	0	855	0	0
T23	490	0	0	0
T28	11763	528	0	0
T29	5617	0	0	0
T32	0	1568	0	0
T33	0	120	0	0
T45	0	485	0	0
T47	443	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T56	524	0	0	0
T73	0	264	0	0
T77	0	2016	0	0
T78	0	6286	0	0
T85	0	343	0	0
T188	434	0	0	0
T242	0	1216	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10234697	0	0
T1	15812	15387	0	0
T2	136155	134555	0	0
T3	23948	21518	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10234697	0	0
T1	15812	15387	0	0
T2	136155	134555	0	0
T3	23948	21518	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	781	0	0
T8	12734	0	0	0
T12	0	8	0	0
T23	490	0	0	0
T28	11763	9	0	0
T29	5617	0	0	0
T32	0	20	0	0
T33	0	8	0	0
T45	0	8	0	0
T47	443	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T56	524	0	0	0
T73	0	9	0	0
T77	0	24	0	0
T78	0	17	0	0
T85	0	7	0	0
T188	434	0	0	0
T242	0	21	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T15
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T3,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T3,T6

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T3,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T3,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T6
0	1	Covered	T3,T21,T108
1	0	Covered	T38,T58

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T6
0	1	Covered	T1,T3,T6
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T6
1	-	Covered	T1,T3,T6

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T6
DetectSt	168	Covered	T1,T3,T6
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T3,T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T6
DebounceSt->IdleSt	163	Covered	T31,T108,T115
DetectSt->IdleSt	186	Covered	T3,T21,T108
DetectSt->StableSt	191	Covered	T1,T3,T6
IdleSt->DebounceSt	148	Covered	T1,T3,T6
StableSt->IdleSt	206	Covered	T1,T3,T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T6
0	1	Covered	T1,T3,T6
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T6
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T38,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T31,T108,T115
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T6
DetectSt	-	-	-	-	1	-	-	Covered	T3,T21,T108
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T6
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T6
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T6
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T6
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10916984	993	0	0
CntIncr_A	10916984	53890	0	0
CntNoWrap_A	10916984	10231237	0	0
DetectStDropOut_A	10916984	90	0	0
DetectedOut_A	10916984	19391	0	0
DetectedPulseOut_A	10916984	379	0	0
DisabledIdleSt_A	10916984	9862853	0	0
DisabledNoDetection_A	10916984	9864635	0	0
EnterDebounceSt_A	10916984	521	0	0
EnterDetectSt_A	10916984	472	0	0
EnterStableSt_A	10916984	379	0	0
PulseIsPulse_A	10916984	379	0	0
StayInStableSt	10916984	18954	0	0
gen_high_level_sva.HighLevelEvent_A	10916984	10234697	0	0
gen_not_sticky_sva.StableStDropOut_A	10916984	320	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	993	0	0
T1	15812	2	0	0
T2	136155	0	0	0
T3	23948	16	0	0
T6	16014	10	0	0
T7	907	0	0	0
T8	0	4	0	0
T12	0	6	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	4	0	0
T28	0	2	0	0
T31	0	13	0	0
T32	0	4	0	0
T108	0	13	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	53890	0	0
T1	15812	70	0	0
T2	136155	0	0	0
T3	23948	818	0	0
T6	16014	435	0	0
T7	907	0	0	0
T8	0	122	0	0
T12	0	180	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	151	0	0
T28	0	60	0	0
T31	0	1080	0	0
T32	0	160	0	0
T108	0	934	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10231237	0	0
T1	15812	15379	0	0
T2	136155	134552	0	0
T3	23948	21492	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	15569	0	0
T13	2041	438	0	0
T14	502	101	0	0
T15	5417	5016	0	0
T16	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	90	0	0
T3	23948	5	0	0
T6	16014	0	0	0
T7	907	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	2	0	0
T28	11763	0	0	0
T38	0	1	0	0
T46	2675	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T88	0	10	0	0
T108	0	6	0	0
T243	0	14	0	0
T244	0	2	0	0
T245	0	12	0	0
T246	0	12	0	0
T247	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	19391	0	0
T1	15812	49	0	0
T2	136155	0	0	0
T3	23948	12	0	0
T6	16014	203	0	0
T7	907	0	0	0
T8	0	37	0	0
T12	0	209	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T28	0	251	0	0
T31	0	246	0	0
T32	0	91	0	0
T77	0	241	0	0
T115	0	149	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	379	0	0
T1	15812	1	0	0
T2	136155	0	0	0
T3	23948	3	0	0
T6	16014	5	0	0
T7	907	0	0	0
T8	0	2	0	0
T12	0	3	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T28	0	1	0	0
T31	0	6	0	0
T32	0	2	0	0
T77	0	7	0	0
T115	0	9	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	9862853	0	0
T1	15812	12088	0	0
T2	136155	134552	0	0
T3	23948	14803	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	12087	0	0
T13	2041	438	0	0
T14	502	101	0	0
T15	5417	5016	0	0
T16	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	9864635	0	0
T1	15812	12088	0	0
T2	136155	134555	0	0
T3	23948	14806	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	12087	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	521	0	0
T1	15812	1	0	0
T2	136155	0	0	0
T3	23948	8	0	0
T6	16014	5	0	0
T7	907	0	0	0
T8	0	2	0	0
T12	0	3	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	2	0	0
T28	0	1	0	0
T31	0	7	0	0
T32	0	2	0	0
T108	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	472	0	0
T1	15812	1	0	0
T2	136155	0	0	0
T3	23948	8	0	0
T6	16014	5	0	0
T7	907	0	0	0
T8	0	2	0	0
T12	0	3	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	2	0	0
T28	0	1	0	0
T31	0	6	0	0
T32	0	2	0	0
T108	0	6	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	379	0	0
T1	15812	1	0	0
T2	136155	0	0	0
T3	23948	3	0	0
T6	16014	5	0	0
T7	907	0	0	0
T8	0	2	0	0
T12	0	3	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T28	0	1	0	0
T31	0	6	0	0
T32	0	2	0	0
T77	0	7	0	0
T115	0	9	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	379	0	0
T1	15812	1	0	0
T2	136155	0	0	0
T3	23948	3	0	0
T6	16014	5	0	0
T7	907	0	0	0
T8	0	2	0	0
T12	0	3	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T28	0	1	0	0
T31	0	6	0	0
T32	0	2	0	0
T77	0	7	0	0
T115	0	9	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	18954	0	0
T1	15812	48	0	0
T2	136155	0	0	0
T3	23948	9	0	0
T6	16014	198	0	0
T7	907	0	0	0
T8	0	35	0	0
T12	0	206	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T28	0	249	0	0
T31	0	240	0	0
T32	0	89	0	0
T77	0	227	0	0
T115	0	140	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10234697	0	0
T1	15812	15387	0	0
T2	136155	134555	0	0
T3	23948	21518	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	320	0	0
T1	15812	1	0	0
T2	136155	0	0	0
T3	23948	3	0	0
T6	16014	5	0	0
T7	907	0	0	0
T8	0	2	0	0
T12	0	3	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T31	0	6	0	0
T32	0	2	0	0
T78	0	4	0	0
T115	0	9	0	0
T248	0	12	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T15,T28,T29
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T15,T28,T29

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T15,T28,T29

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T15,T28,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T28,T29
1	0	Covered	T28,T10,T12
1	1	Covered	T15,T28,T29

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T28,T29
0	1	Covered	T15,T29,T72
1	0	Covered	T77,T75,T38

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T10,T12
0	1	Covered	T28,T10,T12
1	0	Covered	T79,T249

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T28,T10,T12
1	-	Covered	T28,T10,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T15,T28,T29
DetectSt	168	Covered	T15,T28,T29
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T28,T10,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T15,T28,T29
DebounceSt->IdleSt	163	Covered	T45,T38,T241
DetectSt->IdleSt	186	Covered	T15,T29,T72
DetectSt->StableSt	191	Covered	T28,T10,T12
IdleSt->DebounceSt	148	Covered	T15,T28,T29
StableSt->IdleSt	206	Covered	T28,T10,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T15,T28,T29
0	1	Covered	T15,T28,T29
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T28,T29
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T15,T28,T29
IdleSt	0	-	-	-	-	-	-	Covered	T15,T28,T29
DebounceSt	-	1	-	-	-	-	-	Covered	T38,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T28,T29
DebounceSt	-	0	1	0	-	-	-	Covered	T45,T38,T241
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T28,T29
DetectSt	-	-	-	-	1	-	-	Covered	T15,T29,T72
DetectSt	-	-	-	-	0	1	-	Covered	T28,T10,T12
DetectSt	-	-	-	-	0	0	-	Covered	T15,T28,T29
StableSt	-	-	-	-	-	-	1	Covered	T28,T10,T12
StableSt	-	-	-	-	-	-	0	Covered	T28,T10,T12
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10916984	3191	0	0
CntIncr_A	10916984	111153	0	0
CntNoWrap_A	10916984	10229039	0	0
DetectStDropOut_A	10916984	466	0	0
DetectedOut_A	10916984	79842	0	0
DetectedPulseOut_A	10916984	882	0	0
DisabledIdleSt_A	10916984	9770366	0	0
DisabledNoDetection_A	10916984	9772609	0	0
EnterDebounceSt_A	10916984	1618	0	0
EnterDetectSt_A	10916984	1576	0	0
EnterStableSt_A	10916984	882	0	0
PulseIsPulse_A	10916984	882	0	0
StayInStableSt	10916984	78831	0	0
gen_high_event_sva.HighLevelEvent_A	10916984	10234697	0	0
gen_high_level_sva.HighLevelEvent_A	10916984	10234697	0	0
gen_not_sticky_sva.StableStDropOut_A	10916984	744	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	3191	0	0
T6	16014	0	0	0
T7	907	0	0	0
T10	0	26	0	0
T12	0	50	0	0
T15	5417	24	0	0
T16	505	0	0	0
T17	502	0	0	0
T28	11763	46	0	0
T29	0	20	0	0
T32	0	46	0	0
T33	0	24	0	0
T45	0	3	0	0
T46	2675	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T72	0	54	0	0
T73	0	20	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	111153	0	0
T6	16014	0	0	0
T7	907	0	0	0
T10	0	793	0	0
T12	0	1175	0	0
T15	5417	668	0	0
T16	505	0	0	0
T17	502	0	0	0
T28	11763	1426	0	0
T29	0	591	0	0
T32	0	1886	0	0
T33	0	924	0	0
T45	0	894	0	0
T46	2675	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T72	0	1652	0	0
T73	0	510	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10229039	0	0
T1	15812	15381	0	0
T2	136155	134552	0	0
T3	23948	21508	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	15579	0	0
T13	2041	438	0	0
T14	502	101	0	0
T15	5417	4992	0	0
T16	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	466	0	0
T6	16014	0	0	0
T7	907	0	0	0
T15	5417	12	0	0
T16	505	0	0	0
T17	502	0	0	0
T28	11763	0	0	0
T29	0	10	0	0
T38	0	1	0	0
T46	2675	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T72	0	27	0	0
T75	0	6	0	0
T84	0	14	0	0
T86	0	30	0	0
T87	0	21	0	0
T89	0	22	0	0
T250	0	18	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	79842	0	0
T8	12734	0	0	0
T10	0	1847	0	0
T12	0	3502	0	0
T23	490	0	0	0
T28	11763	591	0	0
T29	5617	0	0	0
T32	0	1180	0	0
T33	0	201	0	0
T47	443	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T56	524	0	0	0
T73	0	416	0	0
T78	0	6335	0	0
T85	0	1373	0	0
T188	434	0	0	0
T240	0	177	0	0
T242	0	1321	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	882	0	0
T8	12734	0	0	0
T10	0	13	0	0
T12	0	25	0	0
T23	490	0	0	0
T28	11763	23	0	0
T29	5617	0	0	0
T32	0	23	0	0
T33	0	12	0	0
T47	443	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T56	524	0	0	0
T73	0	10	0	0
T78	0	22	0	0
T85	0	20	0	0
T188	434	0	0	0
T240	0	7	0	0
T242	0	19	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	9770366	0	0
T1	15812	15381	0	0
T2	136155	134552	0	0
T3	23948	21508	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	15579	0	0
T13	2041	438	0	0
T14	502	101	0	0
T15	5417	2014	0	0
T16	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	9772609	0	0
T1	15812	15387	0	0
T2	136155	134555	0	0
T3	23948	21518	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	2014	0	0
T16	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	1618	0	0
T6	16014	0	0	0
T7	907	0	0	0
T10	0	13	0	0
T12	0	25	0	0
T15	5417	12	0	0
T16	505	0	0	0
T17	502	0	0	0
T28	11763	23	0	0
T29	0	10	0	0
T32	0	23	0	0
T33	0	12	0	0
T45	0	3	0	0
T46	2675	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T72	0	27	0	0
T73	0	10	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	1576	0	0
T6	16014	0	0	0
T7	907	0	0	0
T10	0	13	0	0
T12	0	25	0	0
T15	5417	12	0	0
T16	505	0	0	0
T17	502	0	0	0
T28	11763	23	0	0
T29	0	10	0	0
T32	0	23	0	0
T33	0	12	0	0
T46	2675	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T72	0	27	0	0
T73	0	10	0	0
T84	0	14	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	882	0	0
T8	12734	0	0	0
T10	0	13	0	0
T12	0	25	0	0
T23	490	0	0	0
T28	11763	23	0	0
T29	5617	0	0	0
T32	0	23	0	0
T33	0	12	0	0
T47	443	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T56	524	0	0	0
T73	0	10	0	0
T78	0	22	0	0
T85	0	20	0	0
T188	434	0	0	0
T240	0	7	0	0
T242	0	19	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	882	0	0
T8	12734	0	0	0
T10	0	13	0	0
T12	0	25	0	0
T23	490	0	0	0
T28	11763	23	0	0
T29	5617	0	0	0
T32	0	23	0	0
T33	0	12	0	0
T47	443	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T56	524	0	0	0
T73	0	10	0	0
T78	0	22	0	0
T85	0	20	0	0
T188	434	0	0	0
T240	0	7	0	0
T242	0	19	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	78831	0	0
T8	12734	0	0	0
T10	0	1830	0	0
T12	0	3466	0	0
T23	490	0	0	0
T28	11763	567	0	0
T29	5617	0	0	0
T32	0	1154	0	0
T33	0	189	0	0
T47	443	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T56	524	0	0	0
T73	0	405	0	0
T78	0	6308	0	0
T85	0	1352	0	0
T188	434	0	0	0
T240	0	170	0	0
T242	0	1302	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10234697	0	0
T1	15812	15387	0	0
T2	136155	134555	0	0
T3	23948	21518	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10234697	0	0
T1	15812	15387	0	0
T2	136155	134555	0	0
T3	23948	21518	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	744	0	0
T8	12734	0	0	0
T10	0	9	0	0
T12	0	14	0	0
T23	490	0	0	0
T28	11763	22	0	0
T29	5617	0	0	0
T32	0	20	0	0
T33	0	12	0	0
T47	443	0	0	0
T53	424	0	0	0
T54	751	0	0	0
T55	402	0	0	0
T56	524	0	0	0
T73	0	9	0	0
T78	0	17	0	0
T85	0	19	0	0
T188	434	0	0	0
T240	0	7	0	0
T242	0	19	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T15
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T3,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T3,T6

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T3,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T3,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T6
0	1	Covered	T8,T21,T108
1	0	Covered	T38,T58

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T6
0	1	Covered	T1,T3,T6
1	0	Covered	T38,T58

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T6
1	-	Covered	T1,T3,T6

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T6
DetectSt	168	Covered	T1,T3,T6
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T3,T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T6
DebounceSt->IdleSt	163	Covered	T21,T108,T248
DetectSt->IdleSt	186	Covered	T8,T21,T108
DetectSt->StableSt	191	Covered	T1,T3,T6
IdleSt->DebounceSt	148	Covered	T1,T3,T6
StableSt->IdleSt	206	Covered	T1,T3,T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T6
0	1	Covered	T1,T3,T6
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T6
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T38,T58
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T21,T108,T248
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T6
DetectSt	-	-	-	-	1	-	-	Covered	T8,T21,T108
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T6
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T6
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T6
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T6
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	10916984	852	0	0
CntIncr_A	10916984	45300	0	0
CntNoWrap_A	10916984	10231378	0	0
DetectStDropOut_A	10916984	36	0	0
DetectedOut_A	10916984	17188	0	0
DetectedPulseOut_A	10916984	367	0	0
DisabledIdleSt_A	10916984	9872788	0	0
DisabledNoDetection_A	10916984	9874577	0	0
EnterDebounceSt_A	10916984	445	0	0
EnterDetectSt_A	10916984	407	0	0
EnterStableSt_A	10916984	367	0	0
PulseIsPulse_A	10916984	367	0	0
StayInStableSt	10916984	16782	0	0
gen_high_level_sva.HighLevelEvent_A	10916984	10234697	0	0
gen_not_sticky_sva.StableStDropOut_A	10916984	324	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	852	0	0
T1	15812	8	0	0
T2	136155	0	0	0
T3	23948	6	0	0
T6	16014	2	0	0
T7	907	0	0	0
T8	0	4	0	0
T10	0	8	0	0
T12	0	14	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	3	0	0
T31	0	4	0	0
T32	0	2	0	0
T108	0	12	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	45300	0	0
T1	15812	440	0	0
T2	136155	0	0	0
T3	23948	228	0	0
T6	16014	65	0	0
T7	907	0	0	0
T8	0	159	0	0
T10	0	164	0	0
T12	0	294	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	116	0	0
T31	0	240	0	0
T32	0	73	0	0
T108	0	878	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10231378	0	0
T1	15812	15373	0	0
T2	136155	134552	0	0
T3	23948	21502	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	15577	0	0
T13	2041	438	0	0
T14	502	101	0	0
T15	5417	5016	0	0
T16	505	104	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	36	0	0
T8	12734	2	0	0
T9	123429	0	0	0
T10	15620	0	0	0
T21	0	1	0	0
T23	490	0	0	0
T24	498	0	0	0
T29	5617	0	0	0
T47	443	0	0	0
T56	524	0	0	0
T57	452	0	0	0
T108	0	5	0	0
T152	0	4	0	0
T184	0	2	0	0
T188	434	0	0	0
T251	0	5	0	0
T252	0	6	0	0
T253	0	3	0	0
T254	0	1	0	0
T255	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	17188	0	0
T1	15812	40	0	0
T2	136155	0	0	0
T3	23948	117	0	0
T6	16014	62	0	0
T7	907	0	0	0
T10	0	333	0	0
T12	0	609	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T31	0	171	0	0
T32	0	53	0	0
T78	0	172	0	0
T85	0	64	0	0
T115	0	80	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	367	0	0
T1	15812	4	0	0
T2	136155	0	0	0
T3	23948	3	0	0
T6	16014	1	0	0
T7	907	0	0	0
T10	0	4	0	0
T12	0	7	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T31	0	2	0	0
T32	0	1	0	0
T78	0	5	0	0
T85	0	1	0	0
T115	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	9872788	0	0
T1	15812	12088	0	0
T2	136155	134552	0	0
T3	23948	14803	0	0
T4	3530	1526	0	0
T5	422	21	0	0
T6	16014	12087	0	0
T13	2041	438	0	0
T14	502	101	0	0
T15	5417	5016	0	0
T16	505	104	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	9874577	0	0
T1	15812	12088	0	0
T2	136155	134555	0	0
T3	23948	14806	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	12087	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	445	0	0
T1	15812	4	0	0
T2	136155	0	0	0
T3	23948	3	0	0
T6	16014	1	0	0
T7	907	0	0	0
T8	0	2	0	0
T10	0	4	0	0
T12	0	7	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	2	0	0
T31	0	2	0	0
T32	0	1	0	0
T108	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	407	0	0
T1	15812	4	0	0
T2	136155	0	0	0
T3	23948	3	0	0
T6	16014	1	0	0
T7	907	0	0	0
T8	0	2	0	0
T10	0	4	0	0
T12	0	7	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T21	0	1	0	0
T31	0	2	0	0
T32	0	1	0	0
T108	0	5	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	367	0	0
T1	15812	4	0	0
T2	136155	0	0	0
T3	23948	3	0	0
T6	16014	1	0	0
T7	907	0	0	0
T10	0	4	0	0
T12	0	7	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T31	0	2	0	0
T32	0	1	0	0
T78	0	5	0	0
T85	0	1	0	0
T115	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	367	0	0
T1	15812	4	0	0
T2	136155	0	0	0
T3	23948	3	0	0
T6	16014	1	0	0
T7	907	0	0	0
T10	0	4	0	0
T12	0	7	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T31	0	2	0	0
T32	0	1	0	0
T78	0	5	0	0
T85	0	1	0	0
T115	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	16782	0	0
T1	15812	36	0	0
T2	136155	0	0	0
T3	23948	114	0	0
T6	16014	61	0	0
T7	907	0	0	0
T10	0	329	0	0
T12	0	598	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T31	0	169	0	0
T32	0	52	0	0
T78	0	167	0	0
T85	0	62	0	0
T115	0	79	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	10234697	0	0
T1	15812	15387	0	0
T2	136155	134555	0	0
T3	23948	21518	0	0
T4	3530	1530	0	0
T5	422	22	0	0
T6	16014	15585	0	0
T13	2041	441	0	0
T14	502	102	0	0
T15	5417	5017	0	0
T16	505	105	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10916984	324	0	0
T1	15812	3	0	0
T2	136155	0	0	0
T3	23948	3	0	0
T6	16014	1	0	0
T7	907	0	0	0
T10	0	4	0	0
T12	0	3	0	0
T13	2041	0	0	0
T14	502	0	0	0
T15	5417	0	0	0
T16	505	0	0	0
T17	502	0	0	0
T31	0	2	0	0
T32	0	1	0	0
T78	0	5	0	0
T115	0	1	0	0
T248	0	9	0	0