Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre
| Line No. | Total | Covered | Percent |
TOTAL | | 43 | 43 | 100.00 |
CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
ALWAYS | 104 | 3 | 3 | 100.00 |
ALWAYS | 125 | 32 | 32 | 100.00 |
ALWAYS | 219 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
60 |
1 |
1 |
79 |
1 |
1 |
92 |
1 |
1 |
99 |
1 |
1 |
101 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
107 |
1 |
1 |
125 |
1 |
1 |
128 |
1 |
1 |
129 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
138 |
1 |
1 |
140 |
1 |
1 |
147 |
1 |
1 |
148 |
1 |
1 |
149 |
1 |
1 |
|
|
|
MISSING_ELSE |
160 |
1 |
1 |
162 |
1 |
1 |
163 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
168 |
1 |
1 |
170 |
1 |
1 |
|
|
|
MISSING_ELSE |
181 |
1 |
1 |
182 |
1 |
1 |
185 |
1 |
1 |
186 |
1 |
1 |
187 |
1 |
1 |
190 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
|
|
|
MISSING_ELSE |
205 |
1 |
1 |
206 |
1 |
1 |
209 |
1 |
1 |
219 |
1 |
1 |
220 |
1 |
1 |
222 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre
| Total | Covered | Percent |
Conditions | 19 | 18 | 94.74 |
Logical | 19 | 18 | 94.74 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
-1- | Status | Tests |
0 | Covered | T15,T28,T29 |
1 | Covered | T4,T5,T1 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
-1- | Status | Tests |
0 | Covered | T4,T5,T1 |
1 | Covered | T15,T28,T29 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
-1- | Status | Tests |
0 | Covered | T4,T5,T1 |
1 | Covered | T15,T28,T29 |
LINE 99
EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
-----1----
-1- | Status | Tests |
0 | Covered | T4,T5,T1 |
1 | Covered | T15,T28,T29 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T15,T28,T29 |
1 | 0 | Covered | T28,T10,T12 |
1 | 1 | Covered | T15,T28,T29 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T15,T28,T29 |
0 | 1 | Covered | T15,T29,T10 |
1 | 0 | Covered | T10,T73,T75 |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T28,T12,T33 |
0 | 1 | Covered | T28,T12,T33 |
1 | 0 | Not Covered | |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
-1- | -2- | Status | Tests |
0 | - | Covered | T28,T12,T33 |
1 | - | Covered | T28,T12,T33 |
FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
4 |
4 |
100.00 |
(Not included in score) |
Transitions |
6 |
6 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
DebounceSt |
148 |
Covered |
T15,T28,T29 |
DetectSt |
168 |
Covered |
T15,T28,T29 |
IdleSt |
163 |
Covered |
T4,T5,T1 |
StableSt |
191 |
Covered |
T28,T12,T33 |
transitions | Line No. | Covered | Tests |
DebounceSt->DetectSt |
168 |
Covered |
T15,T28,T29 |
DebounceSt->IdleSt |
163 |
Covered |
T45,T38,T241 |
DetectSt->IdleSt |
186 |
Covered |
T15,T29,T10 |
DetectSt->StableSt |
191 |
Covered |
T28,T12,T33 |
IdleSt->DebounceSt |
148 |
Covered |
T15,T28,T29 |
StableSt->IdleSt |
206 |
Covered |
T28,T12,T33 |
Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre
| Line No. | Total | Covered | Percent |
Branches |
|
21 |
20 |
95.24 |
TERNARY |
92 |
3 |
3 |
100.00 |
TERNARY |
99 |
2 |
2 |
100.00 |
IF |
104 |
2 |
2 |
100.00 |
CASE |
140 |
12 |
11 |
91.67 |
IF |
219 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 92 (cnt_clr) ?
-2-: 92 (cnt_en) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T15,T28,T29 |
0 |
1 |
Covered |
T15,T28,T29 |
0 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 99 (thresh_sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T15,T28,T29 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 104 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 140 case (state_q)
-2-: 147 if ((trigger_event && cfg_enable_i))
-3-: 162 if ((!cfg_enable_i))
-4-: 165 if (cnt_done)
-5-: 167 if (trigger_active)
-6-: 185 if (((!cfg_enable_i) || (!trigger_active)))
-7-: 190 if (cnt_done)
-8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests |
IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T15,T28,T29 |
IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T15,T28,T29 |
DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T38,T58 |
DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T15,T28,T29 |
DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T45,T38,T241 |
DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T15,T28,T29 |
DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T15,T29,T10 |
DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T28,T12,T33 |
DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T15,T28,T29 |
StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T28,T12,T33 |
StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T28,T12,T33 |
default |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
LineNo. Expression
-1-: 219 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre
Assertion Details
CntClr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10916984 |
2908 |
0 |
0 |
T6 |
16014 |
0 |
0 |
0 |
T7 |
907 |
0 |
0 |
0 |
T10 |
0 |
32 |
0 |
0 |
T12 |
0 |
10 |
0 |
0 |
T15 |
5417 |
52 |
0 |
0 |
T16 |
505 |
0 |
0 |
0 |
T17 |
502 |
0 |
0 |
0 |
T28 |
11763 |
42 |
0 |
0 |
T29 |
0 |
34 |
0 |
0 |
T32 |
0 |
48 |
0 |
0 |
T33 |
0 |
38 |
0 |
0 |
T45 |
0 |
7 |
0 |
0 |
T46 |
2675 |
0 |
0 |
0 |
T53 |
424 |
0 |
0 |
0 |
T54 |
751 |
0 |
0 |
0 |
T55 |
402 |
0 |
0 |
0 |
T72 |
0 |
20 |
0 |
0 |
T73 |
0 |
46 |
0 |
0 |
CntIncr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10916984 |
98532 |
0 |
0 |
T6 |
16014 |
0 |
0 |
0 |
T7 |
907 |
0 |
0 |
0 |
T10 |
0 |
983 |
0 |
0 |
T12 |
0 |
335 |
0 |
0 |
T15 |
5417 |
1459 |
0 |
0 |
T16 |
505 |
0 |
0 |
0 |
T17 |
502 |
0 |
0 |
0 |
T28 |
11763 |
819 |
0 |
0 |
T29 |
0 |
1011 |
0 |
0 |
T32 |
0 |
1992 |
0 |
0 |
T33 |
0 |
1330 |
0 |
0 |
T45 |
0 |
2086 |
0 |
0 |
T46 |
2675 |
0 |
0 |
0 |
T53 |
424 |
0 |
0 |
0 |
T54 |
751 |
0 |
0 |
0 |
T55 |
402 |
0 |
0 |
0 |
T72 |
0 |
605 |
0 |
0 |
T73 |
0 |
1328 |
0 |
0 |
CntNoWrap_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10916984 |
10229322 |
0 |
0 |
T1 |
15812 |
15381 |
0 |
0 |
T2 |
136155 |
134552 |
0 |
0 |
T3 |
23948 |
21508 |
0 |
0 |
T4 |
3530 |
1526 |
0 |
0 |
T5 |
422 |
21 |
0 |
0 |
T6 |
16014 |
15579 |
0 |
0 |
T13 |
2041 |
438 |
0 |
0 |
T14 |
502 |
101 |
0 |
0 |
T15 |
5417 |
4964 |
0 |
0 |
T16 |
505 |
104 |
0 |
0 |
DetectStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10916984 |
429 |
0 |
0 |
T6 |
16014 |
0 |
0 |
0 |
T7 |
907 |
0 |
0 |
0 |
T10 |
0 |
11 |
0 |
0 |
T15 |
5417 |
26 |
0 |
0 |
T16 |
505 |
0 |
0 |
0 |
T17 |
502 |
0 |
0 |
0 |
T28 |
11763 |
0 |
0 |
0 |
T29 |
0 |
17 |
0 |
0 |
T38 |
0 |
1 |
0 |
0 |
T46 |
2675 |
0 |
0 |
0 |
T53 |
424 |
0 |
0 |
0 |
T54 |
751 |
0 |
0 |
0 |
T55 |
402 |
0 |
0 |
0 |
T72 |
0 |
10 |
0 |
0 |
T73 |
0 |
7 |
0 |
0 |
T75 |
0 |
9 |
0 |
0 |
T84 |
0 |
18 |
0 |
0 |
T86 |
0 |
30 |
0 |
0 |
T87 |
0 |
21 |
0 |
0 |
DetectedOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10916984 |
63900 |
0 |
0 |
T8 |
12734 |
0 |
0 |
0 |
T12 |
0 |
483 |
0 |
0 |
T23 |
490 |
0 |
0 |
0 |
T28 |
11763 |
4192 |
0 |
0 |
T29 |
5617 |
0 |
0 |
0 |
T32 |
0 |
2183 |
0 |
0 |
T33 |
0 |
2113 |
0 |
0 |
T38 |
0 |
496 |
0 |
0 |
T47 |
443 |
0 |
0 |
0 |
T53 |
424 |
0 |
0 |
0 |
T54 |
751 |
0 |
0 |
0 |
T55 |
402 |
0 |
0 |
0 |
T56 |
524 |
0 |
0 |
0 |
T77 |
0 |
289 |
0 |
0 |
T78 |
0 |
1568 |
0 |
0 |
T188 |
434 |
0 |
0 |
0 |
T238 |
0 |
1365 |
0 |
0 |
T240 |
0 |
600 |
0 |
0 |
T242 |
0 |
941 |
0 |
0 |
DetectedPulseOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10916984 |
739 |
0 |
0 |
T8 |
12734 |
0 |
0 |
0 |
T12 |
0 |
5 |
0 |
0 |
T23 |
490 |
0 |
0 |
0 |
T28 |
11763 |
21 |
0 |
0 |
T29 |
5617 |
0 |
0 |
0 |
T32 |
0 |
24 |
0 |
0 |
T33 |
0 |
19 |
0 |
0 |
T38 |
0 |
5 |
0 |
0 |
T47 |
443 |
0 |
0 |
0 |
T53 |
424 |
0 |
0 |
0 |
T54 |
751 |
0 |
0 |
0 |
T55 |
402 |
0 |
0 |
0 |
T56 |
524 |
0 |
0 |
0 |
T77 |
0 |
8 |
0 |
0 |
T78 |
0 |
8 |
0 |
0 |
T188 |
434 |
0 |
0 |
0 |
T238 |
0 |
14 |
0 |
0 |
T240 |
0 |
9 |
0 |
0 |
T242 |
0 |
13 |
0 |
0 |
DisabledIdleSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10916984 |
9784553 |
0 |
0 |
T1 |
15812 |
15381 |
0 |
0 |
T2 |
136155 |
134552 |
0 |
0 |
T3 |
23948 |
21508 |
0 |
0 |
T4 |
3530 |
1526 |
0 |
0 |
T5 |
422 |
21 |
0 |
0 |
T6 |
16014 |
15579 |
0 |
0 |
T13 |
2041 |
438 |
0 |
0 |
T14 |
502 |
101 |
0 |
0 |
T15 |
5417 |
2014 |
0 |
0 |
T16 |
505 |
104 |
0 |
0 |
DisabledNoDetection_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10916984 |
9786816 |
0 |
0 |
T1 |
15812 |
15387 |
0 |
0 |
T2 |
136155 |
134555 |
0 |
0 |
T3 |
23948 |
21518 |
0 |
0 |
T4 |
3530 |
1530 |
0 |
0 |
T5 |
422 |
22 |
0 |
0 |
T6 |
16014 |
15585 |
0 |
0 |
T13 |
2041 |
441 |
0 |
0 |
T14 |
502 |
102 |
0 |
0 |
T15 |
5417 |
2014 |
0 |
0 |
T16 |
505 |
105 |
0 |
0 |
EnterDebounceSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10916984 |
1486 |
0 |
0 |
T6 |
16014 |
0 |
0 |
0 |
T7 |
907 |
0 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T12 |
0 |
5 |
0 |
0 |
T15 |
5417 |
26 |
0 |
0 |
T16 |
505 |
0 |
0 |
0 |
T17 |
502 |
0 |
0 |
0 |
T28 |
11763 |
21 |
0 |
0 |
T29 |
0 |
17 |
0 |
0 |
T32 |
0 |
24 |
0 |
0 |
T33 |
0 |
19 |
0 |
0 |
T45 |
0 |
7 |
0 |
0 |
T46 |
2675 |
0 |
0 |
0 |
T53 |
424 |
0 |
0 |
0 |
T54 |
751 |
0 |
0 |
0 |
T55 |
402 |
0 |
0 |
0 |
T72 |
0 |
10 |
0 |
0 |
T73 |
0 |
23 |
0 |
0 |
EnterDetectSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10916984 |
1425 |
0 |
0 |
T6 |
16014 |
0 |
0 |
0 |
T7 |
907 |
0 |
0 |
0 |
T10 |
0 |
16 |
0 |
0 |
T12 |
0 |
5 |
0 |
0 |
T15 |
5417 |
26 |
0 |
0 |
T16 |
505 |
0 |
0 |
0 |
T17 |
502 |
0 |
0 |
0 |
T28 |
11763 |
21 |
0 |
0 |
T29 |
0 |
17 |
0 |
0 |
T32 |
0 |
24 |
0 |
0 |
T33 |
0 |
19 |
0 |
0 |
T46 |
2675 |
0 |
0 |
0 |
T53 |
424 |
0 |
0 |
0 |
T54 |
751 |
0 |
0 |
0 |
T55 |
402 |
0 |
0 |
0 |
T72 |
0 |
10 |
0 |
0 |
T73 |
0 |
23 |
0 |
0 |
T84 |
0 |
18 |
0 |
0 |
EnterStableSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10916984 |
739 |
0 |
0 |
T8 |
12734 |
0 |
0 |
0 |
T12 |
0 |
5 |
0 |
0 |
T23 |
490 |
0 |
0 |
0 |
T28 |
11763 |
21 |
0 |
0 |
T29 |
5617 |
0 |
0 |
0 |
T32 |
0 |
24 |
0 |
0 |
T33 |
0 |
19 |
0 |
0 |
T38 |
0 |
5 |
0 |
0 |
T47 |
443 |
0 |
0 |
0 |
T53 |
424 |
0 |
0 |
0 |
T54 |
751 |
0 |
0 |
0 |
T55 |
402 |
0 |
0 |
0 |
T56 |
524 |
0 |
0 |
0 |
T77 |
0 |
8 |
0 |
0 |
T78 |
0 |
8 |
0 |
0 |
T188 |
434 |
0 |
0 |
0 |
T238 |
0 |
14 |
0 |
0 |
T240 |
0 |
9 |
0 |
0 |
T242 |
0 |
13 |
0 |
0 |
PulseIsPulse_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10916984 |
739 |
0 |
0 |
T8 |
12734 |
0 |
0 |
0 |
T12 |
0 |
5 |
0 |
0 |
T23 |
490 |
0 |
0 |
0 |
T28 |
11763 |
21 |
0 |
0 |
T29 |
5617 |
0 |
0 |
0 |
T32 |
0 |
24 |
0 |
0 |
T33 |
0 |
19 |
0 |
0 |
T38 |
0 |
5 |
0 |
0 |
T47 |
443 |
0 |
0 |
0 |
T53 |
424 |
0 |
0 |
0 |
T54 |
751 |
0 |
0 |
0 |
T55 |
402 |
0 |
0 |
0 |
T56 |
524 |
0 |
0 |
0 |
T77 |
0 |
8 |
0 |
0 |
T78 |
0 |
8 |
0 |
0 |
T188 |
434 |
0 |
0 |
0 |
T238 |
0 |
14 |
0 |
0 |
T240 |
0 |
9 |
0 |
0 |
T242 |
0 |
13 |
0 |
0 |
StayInStableSt
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10916984 |
63052 |
0 |
0 |
T8 |
12734 |
0 |
0 |
0 |
T12 |
0 |
476 |
0 |
0 |
T23 |
490 |
0 |
0 |
0 |
T28 |
11763 |
4170 |
0 |
0 |
T29 |
5617 |
0 |
0 |
0 |
T32 |
0 |
2154 |
0 |
0 |
T33 |
0 |
2093 |
0 |
0 |
T38 |
0 |
491 |
0 |
0 |
T47 |
443 |
0 |
0 |
0 |
T53 |
424 |
0 |
0 |
0 |
T54 |
751 |
0 |
0 |
0 |
T55 |
402 |
0 |
0 |
0 |
T56 |
524 |
0 |
0 |
0 |
T77 |
0 |
279 |
0 |
0 |
T78 |
0 |
1559 |
0 |
0 |
T188 |
434 |
0 |
0 |
0 |
T238 |
0 |
1347 |
0 |
0 |
T240 |
0 |
591 |
0 |
0 |
T242 |
0 |
926 |
0 |
0 |
gen_high_event_sva.HighLevelEvent_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10916984 |
10234697 |
0 |
0 |
T1 |
15812 |
15387 |
0 |
0 |
T2 |
136155 |
134555 |
0 |
0 |
T3 |
23948 |
21518 |
0 |
0 |
T4 |
3530 |
1530 |
0 |
0 |
T5 |
422 |
22 |
0 |
0 |
T6 |
16014 |
15585 |
0 |
0 |
T13 |
2041 |
441 |
0 |
0 |
T14 |
502 |
102 |
0 |
0 |
T15 |
5417 |
5017 |
0 |
0 |
T16 |
505 |
105 |
0 |
0 |
gen_high_level_sva.HighLevelEvent_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10916984 |
10234697 |
0 |
0 |
T1 |
15812 |
15387 |
0 |
0 |
T2 |
136155 |
134555 |
0 |
0 |
T3 |
23948 |
21518 |
0 |
0 |
T4 |
3530 |
1530 |
0 |
0 |
T5 |
422 |
22 |
0 |
0 |
T6 |
16014 |
15585 |
0 |
0 |
T13 |
2041 |
441 |
0 |
0 |
T14 |
502 |
102 |
0 |
0 |
T15 |
5417 |
5017 |
0 |
0 |
T16 |
505 |
105 |
0 |
0 |
gen_not_sticky_sva.StableStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10916984 |
630 |
0 |
0 |
T8 |
12734 |
0 |
0 |
0 |
T12 |
0 |
3 |
0 |
0 |
T23 |
490 |
0 |
0 |
0 |
T28 |
11763 |
20 |
0 |
0 |
T29 |
5617 |
0 |
0 |
0 |
T32 |
0 |
19 |
0 |
0 |
T33 |
0 |
18 |
0 |
0 |
T38 |
0 |
5 |
0 |
0 |
T47 |
443 |
0 |
0 |
0 |
T53 |
424 |
0 |
0 |
0 |
T54 |
751 |
0 |
0 |
0 |
T55 |
402 |
0 |
0 |
0 |
T56 |
524 |
0 |
0 |
0 |
T77 |
0 |
6 |
0 |
0 |
T78 |
0 |
7 |
0 |
0 |
T188 |
434 |
0 |
0 |
0 |
T238 |
0 |
10 |
0 |
0 |
T240 |
0 |
9 |
0 |
0 |
T242 |
0 |
11 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect
| Line No. | Total | Covered | Percent |
TOTAL | | 46 | 46 | 100.00 |
CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
ALWAYS | 69 | 3 | 3 | 100.00 |
CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
ALWAYS | 104 | 3 | 3 | 100.00 |
ALWAYS | 125 | 32 | 32 | 100.00 |
ALWAYS | 219 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
60 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
72 |
1 |
1 |
76 |
1 |
1 |
92 |
1 |
1 |
99 |
1 |
1 |
101 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
107 |
1 |
1 |
125 |
1 |
1 |
128 |
1 |
1 |
129 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
138 |
1 |
1 |
140 |
1 |
1 |
147 |
1 |
1 |
148 |
1 |
1 |
149 |
1 |
1 |
|
|
|
MISSING_ELSE |
160 |
1 |
1 |
162 |
1 |
1 |
163 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
168 |
1 |
1 |
170 |
1 |
1 |
|
|
|
MISSING_ELSE |
181 |
1 |
1 |
182 |
1 |
1 |
185 |
1 |
1 |
186 |
1 |
1 |
187 |
1 |
1 |
190 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
|
|
|
MISSING_ELSE |
205 |
1 |
1 |
206 |
1 |
1 |
209 |
1 |
1 |
|
|
|
Exclude Annotation: VC_COV_UNR |
219 |
1 |
1 |
220 |
1 |
1 |
222 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect
| Total | Covered | Percent |
Conditions | 21 | 21 | 100.00 |
Logical | 21 | 21 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
-1- | Status | Tests |
0 | Covered | T1,T3,T15 |
1 | Covered | T4,T5,T1 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T15 |
1 | 0 | Covered | T4,T5,T1 |
1 | 1 | Covered | T4,T5,T1 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
-1- | Status | Tests |
0 | Covered | T4,T5,T1 |
1 | Covered | T1,T3,T6 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
-1- | Status | Tests | Exclude Annotation |
0 | Excluded | T4,T5,T1 |
VC_COV_UNR |
1 | Covered | T1,T3,T6 |
LINE 99
EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
-----1----
-1- | Status | Tests |
0 | Covered | T4,T5,T1 |
1 | Covered | T1,T3,T6 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T4,T1,T2 |
1 | 1 | Covered | T1,T3,T6 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T6 |
0 | 1 | Covered | T3,T6,T8 |
1 | 0 | Covered | T38,T58 |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T28,T12 |
0 | 1 | Covered | T1,T12,T31 |
1 | 0 | Covered | T38 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
-1- | -2- | Status | Tests |
0 | - | Covered | T1,T28,T12 |
1 | - | Covered | T1,T12,T31 |
FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
4 |
4 |
100.00 |
(Not included in score) |
Transitions |
6 |
6 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
DebounceSt |
148 |
Covered |
T1,T3,T6 |
DetectSt |
168 |
Covered |
T1,T3,T6 |
IdleSt |
163 |
Covered |
T4,T5,T1 |
StableSt |
191 |
Covered |
T1,T28,T12 |
transitions | Line No. | Covered | Tests |
DebounceSt->DetectSt |
168 |
Covered |
T1,T3,T6 |
DebounceSt->IdleSt |
163 |
Covered |
T3,T8,T31 |
DetectSt->IdleSt |
186 |
Covered |
T3,T6,T8 |
DetectSt->StableSt |
191 |
Covered |
T1,T28,T12 |
IdleSt->DebounceSt |
148 |
Covered |
T1,T3,T6 |
StableSt->IdleSt |
206 |
Covered |
T1,T28,T12 |
Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect
| Line No. | Total | Covered | Percent |
Branches |
|
21 |
21 |
100.00 |
TERNARY |
92 |
2 |
2 |
100.00 |
TERNARY |
99 |
2 |
2 |
100.00 |
IF |
104 |
2 |
2 |
100.00 |
CASE |
140 |
11 |
11 |
100.00 |
IF |
219 |
2 |
2 |
100.00 |
IF |
69 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 92 (cnt_clr) ?
-2-: 92 (cnt_en) ?
Branches:
-1- | -2- | Status | Tests | Exclude Annotation |
1 |
- |
Covered |
T1,T3,T6 |
|
0 |
1 |
Covered |
T1,T3,T6 |
|
0 |
0 |
Excluded |
T4,T5,T1 |
VC_COV_UNR |
LineNo. Expression
-1-: 99 (thresh_sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T6 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 104 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 140 case (state_q)
-2-: 147 if ((trigger_event && cfg_enable_i))
-3-: 162 if ((!cfg_enable_i))
-4-: 165 if (cnt_done)
-5-: 167 if (trigger_active)
-6-: 185 if (((!cfg_enable_i) || (!trigger_active)))
-7-: 190 if (cnt_done)
-8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests | Exclude Annotation |
IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T3,T6 |
|
IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T4,T5,T1 |
|
DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T38,T58 |
|
DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T1,T3,T6 |
|
DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T3,T8,T31 |
|
DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T1,T3,T6 |
|
DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T3,T6,T8 |
|
DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T1,T28,T12 |
|
DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T1,T3,T6 |
|
StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T1,T12,T31 |
|
StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T1,T28,T12 |
|
default |
- |
- |
- |
- |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
LineNo. Expression
-1-: 219 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T1 |
0 |
Covered |
T4,T5,T1 |
Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect
Assertion Details
CntClr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10916984 |
731 |
0 |
0 |
T1 |
15812 |
2 |
0 |
0 |
T2 |
136155 |
0 |
0 |
0 |
T3 |
23948 |
19 |
0 |
0 |
T6 |
16014 |
8 |
0 |
0 |
T7 |
907 |
0 |
0 |
0 |
T8 |
0 |
11 |
0 |
0 |
T12 |
0 |
4 |
0 |
0 |
T13 |
2041 |
0 |
0 |
0 |
T14 |
502 |
0 |
0 |
0 |
T15 |
5417 |
0 |
0 |
0 |
T16 |
505 |
0 |
0 |
0 |
T17 |
502 |
0 |
0 |
0 |
T21 |
0 |
2 |
0 |
0 |
T28 |
0 |
2 |
0 |
0 |
T31 |
0 |
9 |
0 |
0 |
T32 |
0 |
8 |
0 |
0 |
T33 |
0 |
2 |
0 |
0 |
CntIncr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10916984 |
38289 |
0 |
0 |
T1 |
15812 |
87 |
0 |
0 |
T2 |
136155 |
0 |
0 |
0 |
T3 |
23948 |
1064 |
0 |
0 |
T6 |
16014 |
508 |
0 |
0 |
T7 |
907 |
0 |
0 |
0 |
T8 |
0 |
418 |
0 |
0 |
T12 |
0 |
152 |
0 |
0 |
T13 |
2041 |
0 |
0 |
0 |
T14 |
502 |
0 |
0 |
0 |
T15 |
5417 |
0 |
0 |
0 |
T16 |
505 |
0 |
0 |
0 |
T17 |
502 |
0 |
0 |
0 |
T21 |
0 |
75 |
0 |
0 |
T28 |
0 |
56 |
0 |
0 |
T31 |
0 |
678 |
0 |
0 |
T32 |
0 |
312 |
0 |
0 |
T33 |
0 |
85 |
0 |
0 |
CntNoWrap_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10916984 |
10231499 |
0 |
0 |
T1 |
15812 |
15379 |
0 |
0 |
T2 |
136155 |
134552 |
0 |
0 |
T3 |
23948 |
21489 |
0 |
0 |
T4 |
3530 |
1526 |
0 |
0 |
T5 |
422 |
21 |
0 |
0 |
T6 |
16014 |
15571 |
0 |
0 |
T13 |
2041 |
438 |
0 |
0 |
T14 |
502 |
101 |
0 |
0 |
T15 |
5417 |
5016 |
0 |
0 |
T16 |
505 |
104 |
0 |
0 |
DetectStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10916984 |
59 |
0 |
0 |
T3 |
23948 |
9 |
0 |
0 |
T6 |
16014 |
4 |
0 |
0 |
T7 |
907 |
0 |
0 |
0 |
T8 |
0 |
5 |
0 |
0 |
T15 |
5417 |
0 |
0 |
0 |
T16 |
505 |
0 |
0 |
0 |
T17 |
502 |
0 |
0 |
0 |
T21 |
0 |
1 |
0 |
0 |
T28 |
11763 |
0 |
0 |
0 |
T46 |
2675 |
0 |
0 |
0 |
T53 |
424 |
0 |
0 |
0 |
T54 |
751 |
0 |
0 |
0 |
T88 |
0 |
3 |
0 |
0 |
T245 |
0 |
7 |
0 |
0 |
T247 |
0 |
2 |
0 |
0 |
T256 |
0 |
2 |
0 |
0 |
T257 |
0 |
6 |
0 |
0 |
T258 |
0 |
1 |
0 |
0 |
DetectedOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10916984 |
11302 |
0 |
0 |
T1 |
15812 |
32 |
0 |
0 |
T2 |
136155 |
0 |
0 |
0 |
T3 |
23948 |
0 |
0 |
0 |
T6 |
16014 |
0 |
0 |
0 |
T7 |
907 |
0 |
0 |
0 |
T12 |
0 |
110 |
0 |
0 |
T13 |
2041 |
0 |
0 |
0 |
T14 |
502 |
0 |
0 |
0 |
T15 |
5417 |
0 |
0 |
0 |
T16 |
505 |
0 |
0 |
0 |
T17 |
502 |
0 |
0 |
0 |
T28 |
0 |
255 |
0 |
0 |
T31 |
0 |
234 |
0 |
0 |
T32 |
0 |
187 |
0 |
0 |
T33 |
0 |
62 |
0 |
0 |
T77 |
0 |
77 |
0 |
0 |
T78 |
0 |
51 |
0 |
0 |
T108 |
0 |
190 |
0 |
0 |
T115 |
0 |
74 |
0 |
0 |
DetectedPulseOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10916984 |
288 |
0 |
0 |
T1 |
15812 |
1 |
0 |
0 |
T2 |
136155 |
0 |
0 |
0 |
T3 |
23948 |
0 |
0 |
0 |
T6 |
16014 |
0 |
0 |
0 |
T7 |
907 |
0 |
0 |
0 |
T12 |
0 |
2 |
0 |
0 |
T13 |
2041 |
0 |
0 |
0 |
T14 |
502 |
0 |
0 |
0 |
T15 |
5417 |
0 |
0 |
0 |
T16 |
505 |
0 |
0 |
0 |
T17 |
502 |
0 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T31 |
0 |
4 |
0 |
0 |
T32 |
0 |
4 |
0 |
0 |
T33 |
0 |
1 |
0 |
0 |
T77 |
0 |
2 |
0 |
0 |
T78 |
0 |
1 |
0 |
0 |
T108 |
0 |
6 |
0 |
0 |
T115 |
0 |
1 |
0 |
0 |
DisabledIdleSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10916984 |
9894332 |
0 |
0 |
T1 |
15812 |
12088 |
0 |
0 |
T2 |
136155 |
134552 |
0 |
0 |
T3 |
23948 |
14803 |
0 |
0 |
T4 |
3530 |
1526 |
0 |
0 |
T5 |
422 |
21 |
0 |
0 |
T6 |
16014 |
12087 |
0 |
0 |
T13 |
2041 |
438 |
0 |
0 |
T14 |
502 |
101 |
0 |
0 |
T15 |
5417 |
5016 |
0 |
0 |
T16 |
505 |
104 |
0 |
0 |
DisabledNoDetection_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10916984 |
9896148 |
0 |
0 |
T1 |
15812 |
12088 |
0 |
0 |
T2 |
136155 |
134555 |
0 |
0 |
T3 |
23948 |
14806 |
0 |
0 |
T4 |
3530 |
1530 |
0 |
0 |
T5 |
422 |
22 |
0 |
0 |
T6 |
16014 |
12087 |
0 |
0 |
T13 |
2041 |
441 |
0 |
0 |
T14 |
502 |
102 |
0 |
0 |
T15 |
5417 |
5017 |
0 |
0 |
T16 |
505 |
105 |
0 |
0 |
EnterDebounceSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10916984 |
381 |
0 |
0 |
T1 |
15812 |
1 |
0 |
0 |
T2 |
136155 |
0 |
0 |
0 |
T3 |
23948 |
10 |
0 |
0 |
T6 |
16014 |
4 |
0 |
0 |
T7 |
907 |
0 |
0 |
0 |
T8 |
0 |
6 |
0 |
0 |
T12 |
0 |
2 |
0 |
0 |
T13 |
2041 |
0 |
0 |
0 |
T14 |
502 |
0 |
0 |
0 |
T15 |
5417 |
0 |
0 |
0 |
T16 |
505 |
0 |
0 |
0 |
T17 |
502 |
0 |
0 |
0 |
T21 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T31 |
0 |
5 |
0 |
0 |
T32 |
0 |
4 |
0 |
0 |
T33 |
0 |
1 |
0 |
0 |
EnterDetectSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10916984 |
351 |
0 |
0 |
T1 |
15812 |
1 |
0 |
0 |
T2 |
136155 |
0 |
0 |
0 |
T3 |
23948 |
9 |
0 |
0 |
T6 |
16014 |
4 |
0 |
0 |
T7 |
907 |
0 |
0 |
0 |
T8 |
0 |
5 |
0 |
0 |
T12 |
0 |
2 |
0 |
0 |
T13 |
2041 |
0 |
0 |
0 |
T14 |
502 |
0 |
0 |
0 |
T15 |
5417 |
0 |
0 |
0 |
T16 |
505 |
0 |
0 |
0 |
T17 |
502 |
0 |
0 |
0 |
T21 |
0 |
1 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T31 |
0 |
4 |
0 |
0 |
T32 |
0 |
4 |
0 |
0 |
T33 |
0 |
1 |
0 |
0 |
EnterStableSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10916984 |
288 |
0 |
0 |
T1 |
15812 |
1 |
0 |
0 |
T2 |
136155 |
0 |
0 |
0 |
T3 |
23948 |
0 |
0 |
0 |
T6 |
16014 |
0 |
0 |
0 |
T7 |
907 |
0 |
0 |
0 |
T12 |
0 |
2 |
0 |
0 |
T13 |
2041 |
0 |
0 |
0 |
T14 |
502 |
0 |
0 |
0 |
T15 |
5417 |
0 |
0 |
0 |
T16 |
505 |
0 |
0 |
0 |
T17 |
502 |
0 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T31 |
0 |
4 |
0 |
0 |
T32 |
0 |
4 |
0 |
0 |
T33 |
0 |
1 |
0 |
0 |
T77 |
0 |
2 |
0 |
0 |
T78 |
0 |
1 |
0 |
0 |
T108 |
0 |
6 |
0 |
0 |
T115 |
0 |
1 |
0 |
0 |
PulseIsPulse_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10916984 |
288 |
0 |
0 |
T1 |
15812 |
1 |
0 |
0 |
T2 |
136155 |
0 |
0 |
0 |
T3 |
23948 |
0 |
0 |
0 |
T6 |
16014 |
0 |
0 |
0 |
T7 |
907 |
0 |
0 |
0 |
T12 |
0 |
2 |
0 |
0 |
T13 |
2041 |
0 |
0 |
0 |
T14 |
502 |
0 |
0 |
0 |
T15 |
5417 |
0 |
0 |
0 |
T16 |
505 |
0 |
0 |
0 |
T17 |
502 |
0 |
0 |
0 |
T28 |
0 |
1 |
0 |
0 |
T31 |
0 |
4 |
0 |
0 |
T32 |
0 |
4 |
0 |
0 |
T33 |
0 |
1 |
0 |
0 |
T77 |
0 |
2 |
0 |
0 |
T78 |
0 |
1 |
0 |
0 |
T108 |
0 |
6 |
0 |
0 |
T115 |
0 |
1 |
0 |
0 |
StayInStableSt
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10916984 |
10968 |
0 |
0 |
T1 |
15812 |
31 |
0 |
0 |
T2 |
136155 |
0 |
0 |
0 |
T3 |
23948 |
0 |
0 |
0 |
T6 |
16014 |
0 |
0 |
0 |
T7 |
907 |
0 |
0 |
0 |
T12 |
0 |
108 |
0 |
0 |
T13 |
2041 |
0 |
0 |
0 |
T14 |
502 |
0 |
0 |
0 |
T15 |
5417 |
0 |
0 |
0 |
T16 |
505 |
0 |
0 |
0 |
T17 |
502 |
0 |
0 |
0 |
T28 |
0 |
253 |
0 |
0 |
T31 |
0 |
230 |
0 |
0 |
T32 |
0 |
181 |
0 |
0 |
T33 |
0 |
61 |
0 |
0 |
T77 |
0 |
73 |
0 |
0 |
T78 |
0 |
50 |
0 |
0 |
T108 |
0 |
184 |
0 |
0 |
T115 |
0 |
73 |
0 |
0 |
gen_high_level_sva.HighLevelEvent_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10916984 |
10234697 |
0 |
0 |
T1 |
15812 |
15387 |
0 |
0 |
T2 |
136155 |
134555 |
0 |
0 |
T3 |
23948 |
21518 |
0 |
0 |
T4 |
3530 |
1530 |
0 |
0 |
T5 |
422 |
22 |
0 |
0 |
T6 |
16014 |
15585 |
0 |
0 |
T13 |
2041 |
441 |
0 |
0 |
T14 |
502 |
102 |
0 |
0 |
T15 |
5417 |
5017 |
0 |
0 |
T16 |
505 |
105 |
0 |
0 |
gen_not_sticky_sva.StableStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10916984 |
240 |
0 |
0 |
T1 |
15812 |
1 |
0 |
0 |
T2 |
136155 |
0 |
0 |
0 |
T3 |
23948 |
0 |
0 |
0 |
T6 |
16014 |
0 |
0 |
0 |
T7 |
907 |
0 |
0 |
0 |
T12 |
0 |
2 |
0 |
0 |
T13 |
2041 |
0 |
0 |
0 |
T14 |
502 |
0 |
0 |
0 |
T15 |
5417 |
0 |
0 |
0 |
T16 |
505 |
0 |
0 |
0 |
T17 |
502 |
0 |
0 |
0 |
T31 |
0 |
4 |
0 |
0 |
T32 |
0 |
2 |
0 |
0 |
T33 |
0 |
1 |
0 |
0 |
T78 |
0 |
1 |
0 |
0 |
T108 |
0 |
6 |
0 |
0 |
T115 |
0 |
1 |
0 |
0 |
T166 |
0 |
4 |
0 |
0 |
T248 |
0 |
6 |
0 |
0 |