Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.00 98.81 96.76 100.00 95.51 98.26 99.52 90.11


Total test records in report: 911
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T787 /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.3916116727 Mar 24 12:43:06 PM PDT 24 Mar 24 12:43:11 PM PDT 24 2010442394 ps
T788 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.4188145518 Mar 24 12:42:51 PM PDT 24 Mar 24 12:42:56 PM PDT 24 2008890272 ps
T789 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.3393258700 Mar 24 12:42:55 PM PDT 24 Mar 24 12:42:57 PM PDT 24 2028128949 ps
T19 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.3078586306 Mar 24 12:42:43 PM PDT 24 Mar 24 12:43:05 PM PDT 24 4788129769 ps
T260 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.2380315868 Mar 24 12:42:43 PM PDT 24 Mar 24 12:42:47 PM PDT 24 2176464069 ps
T790 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.2976623153 Mar 24 12:42:52 PM PDT 24 Mar 24 12:42:58 PM PDT 24 2017133550 ps
T30 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.4030996332 Mar 24 12:42:47 PM PDT 24 Mar 24 12:43:16 PM PDT 24 22211763288 ps
T267 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.383473297 Mar 24 12:42:50 PM PDT 24 Mar 24 12:42:53 PM PDT 24 2330631082 ps
T263 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.4260850469 Mar 24 12:42:52 PM PDT 24 Mar 24 12:43:11 PM PDT 24 22409368689 ps
T264 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.1563855796 Mar 24 12:42:43 PM PDT 24 Mar 24 12:43:44 PM PDT 24 22225813023 ps
T313 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.577189698 Mar 24 12:42:48 PM PDT 24 Mar 24 12:42:56 PM PDT 24 2201910597 ps
T791 /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.628230417 Mar 24 12:42:38 PM PDT 24 Mar 24 12:42:44 PM PDT 24 2015237861 ps
T265 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.1699070974 Mar 24 12:42:45 PM PDT 24 Mar 24 12:42:52 PM PDT 24 2133327409 ps
T314 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.1433260306 Mar 24 12:42:33 PM PDT 24 Mar 24 12:42:44 PM PDT 24 2932712574 ps
T315 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.1983680420 Mar 24 12:42:49 PM PDT 24 Mar 24 12:42:53 PM PDT 24 2077844056 ps
T792 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.2704083356 Mar 24 12:42:40 PM PDT 24 Mar 24 12:42:44 PM PDT 24 2019037935 ps
T324 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.4081416683 Mar 24 12:42:53 PM PDT 24 Mar 24 12:42:56 PM PDT 24 2082224704 ps
T20 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.1803153035 Mar 24 12:42:56 PM PDT 24 Mar 24 12:43:14 PM PDT 24 4491046889 ps
T351 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.1803921766 Mar 24 12:42:48 PM PDT 24 Mar 24 12:43:49 PM PDT 24 22254599290 ps
T325 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.2283806488 Mar 24 12:43:07 PM PDT 24 Mar 24 12:43:12 PM PDT 24 7238851176 ps
T793 /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.2347006773 Mar 24 12:43:04 PM PDT 24 Mar 24 12:43:09 PM PDT 24 2014609516 ps
T326 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.3340887463 Mar 24 12:42:45 PM PDT 24 Mar 24 12:42:46 PM PDT 24 2155909843 ps
T352 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.3976330274 Mar 24 12:43:00 PM PDT 24 Mar 24 12:43:29 PM PDT 24 43495880135 ps
T316 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.1947055145 Mar 24 12:42:32 PM PDT 24 Mar 24 12:42:45 PM PDT 24 7728088920 ps
T268 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.4264585747 Mar 24 12:42:49 PM PDT 24 Mar 24 12:43:06 PM PDT 24 22249785900 ps
T794 /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.2859775741 Mar 24 12:43:19 PM PDT 24 Mar 24 12:43:22 PM PDT 24 2042225537 ps
T270 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.2113596578 Mar 24 12:42:40 PM PDT 24 Mar 24 12:42:48 PM PDT 24 2084663950 ps
T379 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.523242013 Mar 24 12:43:03 PM PDT 24 Mar 24 12:43:10 PM PDT 24 2115679810 ps
T327 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.3219602181 Mar 24 12:42:57 PM PDT 24 Mar 24 12:42:59 PM PDT 24 2087231394 ps
T795 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.492266635 Mar 24 12:42:43 PM PDT 24 Mar 24 12:42:52 PM PDT 24 6114960347 ps
T353 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.3823648853 Mar 24 12:43:12 PM PDT 24 Mar 24 12:45:08 PM PDT 24 42447428716 ps
T317 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.2591287826 Mar 24 12:43:02 PM PDT 24 Mar 24 12:45:47 PM PDT 24 37172599608 ps
T796 /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.2701880606 Mar 24 12:42:44 PM PDT 24 Mar 24 12:42:46 PM PDT 24 2028947648 ps
T328 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.1085911018 Mar 24 12:42:59 PM PDT 24 Mar 24 12:43:22 PM PDT 24 5359178391 ps
T797 /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.42711066 Mar 24 12:42:44 PM PDT 24 Mar 24 12:42:46 PM PDT 24 2026766419 ps
T329 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.2314038753 Mar 24 12:42:37 PM PDT 24 Mar 24 12:42:42 PM PDT 24 5195767410 ps
T798 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.718939559 Mar 24 12:42:38 PM PDT 24 Mar 24 12:42:39 PM PDT 24 2112543268 ps
T799 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.2416815408 Mar 24 12:43:03 PM PDT 24 Mar 24 12:43:04 PM PDT 24 2612464200 ps
T800 /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.3657120747 Mar 24 12:42:55 PM PDT 24 Mar 24 12:42:58 PM PDT 24 2016311110 ps
T801 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.3226480212 Mar 24 12:42:41 PM PDT 24 Mar 24 12:43:02 PM PDT 24 7742677382 ps
T318 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.3965689331 Mar 24 12:42:46 PM PDT 24 Mar 24 12:44:18 PM PDT 24 39008717397 ps
T802 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.2407977104 Mar 24 12:42:36 PM PDT 24 Mar 24 12:42:42 PM PDT 24 2012965669 ps
T319 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.1604325156 Mar 24 12:42:49 PM PDT 24 Mar 24 12:42:55 PM PDT 24 4023750662 ps
T266 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.1137124920 Mar 24 12:42:50 PM PDT 24 Mar 24 12:42:57 PM PDT 24 2027809824 ps
T803 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.1639563195 Mar 24 12:42:45 PM PDT 24 Mar 24 12:42:48 PM PDT 24 2044781891 ps
T804 /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.2105978483 Mar 24 12:43:01 PM PDT 24 Mar 24 12:43:03 PM PDT 24 2052058915 ps
T320 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.938695193 Mar 24 12:42:47 PM PDT 24 Mar 24 12:47:41 PM PDT 24 59309660879 ps
T354 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.3034202331 Mar 24 12:42:50 PM PDT 24 Mar 24 12:43:50 PM PDT 24 22215029306 ps
T805 /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.874835131 Mar 24 12:43:01 PM PDT 24 Mar 24 12:43:08 PM PDT 24 2011686176 ps
T321 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.3889325295 Mar 24 12:42:40 PM PDT 24 Mar 24 12:42:45 PM PDT 24 2033511988 ps
T806 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.4006205149 Mar 24 12:42:44 PM PDT 24 Mar 24 12:42:48 PM PDT 24 2020626635 ps
T807 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.2616164396 Mar 24 12:42:35 PM PDT 24 Mar 24 12:42:41 PM PDT 24 2704765241 ps
T808 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.76926355 Mar 24 12:42:40 PM PDT 24 Mar 24 12:43:04 PM PDT 24 9252883898 ps
T355 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.2122727402 Mar 24 12:42:54 PM PDT 24 Mar 24 12:44:47 PM PDT 24 42362088277 ps
T809 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.2118101088 Mar 24 12:42:39 PM PDT 24 Mar 24 12:42:41 PM PDT 24 2160827469 ps
T322 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.3590028196 Mar 24 12:42:35 PM PDT 24 Mar 24 12:42:41 PM PDT 24 2058713000 ps
T810 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.1141168134 Mar 24 12:42:48 PM PDT 24 Mar 24 12:42:50 PM PDT 24 2035556924 ps
T269 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.1579862445 Mar 24 12:42:42 PM PDT 24 Mar 24 12:42:51 PM PDT 24 2187201223 ps
T811 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.2831752360 Mar 24 12:42:42 PM PDT 24 Mar 24 12:44:37 PM PDT 24 42435715347 ps
T812 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.1553412716 Mar 24 12:42:47 PM PDT 24 Mar 24 12:42:49 PM PDT 24 2140359779 ps
T813 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.1288967340 Mar 24 12:42:39 PM PDT 24 Mar 24 12:42:41 PM PDT 24 2218274393 ps
T814 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.1148457431 Mar 24 12:42:51 PM PDT 24 Mar 24 12:42:57 PM PDT 24 2009107878 ps
T815 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.2871426946 Mar 24 12:42:57 PM PDT 24 Mar 24 12:43:02 PM PDT 24 4511618315 ps
T816 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.1225622267 Mar 24 12:42:35 PM PDT 24 Mar 24 12:42:50 PM PDT 24 22499368640 ps
T817 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.278985546 Mar 24 12:42:36 PM PDT 24 Mar 24 12:42:40 PM PDT 24 2157759312 ps
T323 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.2790707331 Mar 24 12:42:48 PM PDT 24 Mar 24 12:42:53 PM PDT 24 2218477392 ps
T818 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.4205671963 Mar 24 12:42:33 PM PDT 24 Mar 24 12:42:40 PM PDT 24 4040275509 ps
T819 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.2246036516 Mar 24 12:42:28 PM PDT 24 Mar 24 12:42:33 PM PDT 24 6046898456 ps
T820 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2109177601 Mar 24 12:42:40 PM PDT 24 Mar 24 12:42:43 PM PDT 24 2198939424 ps
T356 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.3334312215 Mar 24 12:42:56 PM PDT 24 Mar 24 12:44:48 PM PDT 24 42485554064 ps
T821 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.2472011611 Mar 24 12:43:03 PM PDT 24 Mar 24 12:43:10 PM PDT 24 2059684974 ps
T822 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.2890484467 Mar 24 12:43:00 PM PDT 24 Mar 24 12:43:03 PM PDT 24 2128260800 ps
T823 /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.2218539048 Mar 24 12:43:01 PM PDT 24 Mar 24 12:43:03 PM PDT 24 2040800220 ps
T824 /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.563846810 Mar 24 12:43:16 PM PDT 24 Mar 24 12:43:22 PM PDT 24 2014223943 ps
T825 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.3400826834 Mar 24 12:42:45 PM PDT 24 Mar 24 12:42:51 PM PDT 24 2015826714 ps
T826 /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.1099240865 Mar 24 12:43:02 PM PDT 24 Mar 24 12:43:04 PM PDT 24 2047298540 ps
T827 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.2499671161 Mar 24 12:42:46 PM PDT 24 Mar 24 12:43:38 PM PDT 24 22231549641 ps
T828 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.361535963 Mar 24 12:42:42 PM PDT 24 Mar 24 12:42:45 PM PDT 24 2104945332 ps
T829 /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.1071953980 Mar 24 12:43:01 PM PDT 24 Mar 24 12:43:02 PM PDT 24 2102752216 ps
T830 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.290143511 Mar 24 12:42:42 PM PDT 24 Mar 24 12:43:45 PM PDT 24 22232624201 ps
T831 /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.430745719 Mar 24 12:42:58 PM PDT 24 Mar 24 12:43:00 PM PDT 24 2052915470 ps
T832 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.4074522472 Mar 24 12:42:34 PM PDT 24 Mar 24 12:45:48 PM PDT 24 75604039814 ps
T833 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.3345497262 Mar 24 12:42:46 PM PDT 24 Mar 24 12:42:48 PM PDT 24 2039321469 ps
T834 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.3373750605 Mar 24 12:42:44 PM PDT 24 Mar 24 12:42:46 PM PDT 24 2149289566 ps
T835 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.112511537 Mar 24 12:43:00 PM PDT 24 Mar 24 12:43:04 PM PDT 24 2156235362 ps
T836 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.1072994913 Mar 24 12:43:00 PM PDT 24 Mar 24 12:43:04 PM PDT 24 2600972186 ps
T837 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.1580456724 Mar 24 12:42:41 PM PDT 24 Mar 24 12:42:43 PM PDT 24 2046169758 ps
T838 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.3162825844 Mar 24 12:42:59 PM PDT 24 Mar 24 12:43:01 PM PDT 24 2084766561 ps
T839 /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.4292776621 Mar 24 12:43:00 PM PDT 24 Mar 24 12:43:06 PM PDT 24 2013246680 ps
T840 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.3197673641 Mar 24 12:42:48 PM PDT 24 Mar 24 12:42:50 PM PDT 24 2107255846 ps
T841 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.1328700825 Mar 24 12:43:03 PM PDT 24 Mar 24 12:43:06 PM PDT 24 2067216654 ps
T842 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.3198811020 Mar 24 12:43:13 PM PDT 24 Mar 24 12:43:15 PM PDT 24 2051728038 ps
T843 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.2085096969 Mar 24 12:42:57 PM PDT 24 Mar 24 12:43:00 PM PDT 24 4491799380 ps
T844 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.266913446 Mar 24 12:42:47 PM PDT 24 Mar 24 12:42:54 PM PDT 24 2040102637 ps
T845 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.3132416808 Mar 24 12:42:51 PM PDT 24 Mar 24 12:42:57 PM PDT 24 2085201069 ps
T846 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.1766871125 Mar 24 12:42:56 PM PDT 24 Mar 24 12:43:03 PM PDT 24 4579318102 ps
T847 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.346987744 Mar 24 12:42:35 PM PDT 24 Mar 24 12:42:41 PM PDT 24 2100156419 ps
T848 /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.694529394 Mar 24 12:42:56 PM PDT 24 Mar 24 12:42:58 PM PDT 24 2033631383 ps
T849 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.2381800395 Mar 24 12:42:45 PM PDT 24 Mar 24 12:42:51 PM PDT 24 10595230911 ps
T850 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.2206019190 Mar 24 12:42:58 PM PDT 24 Mar 24 12:43:06 PM PDT 24 5665318815 ps
T851 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.1865265746 Mar 24 12:42:47 PM PDT 24 Mar 24 12:42:54 PM PDT 24 2111798921 ps
T852 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.2802597080 Mar 24 12:42:37 PM PDT 24 Mar 24 12:42:56 PM PDT 24 5229519843 ps
T853 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.1575317858 Mar 24 12:42:41 PM PDT 24 Mar 24 12:42:47 PM PDT 24 2015960537 ps
T854 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.3791192781 Mar 24 12:42:41 PM PDT 24 Mar 24 12:42:49 PM PDT 24 2051781940 ps
T855 /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.3096862948 Mar 24 12:42:58 PM PDT 24 Mar 24 12:43:03 PM PDT 24 2017068719 ps
T856 /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.617586765 Mar 24 12:42:41 PM PDT 24 Mar 24 12:42:45 PM PDT 24 2023476463 ps
T857 /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.1174871941 Mar 24 12:42:48 PM PDT 24 Mar 24 12:42:54 PM PDT 24 2012159438 ps
T858 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.3443094188 Mar 24 12:42:42 PM PDT 24 Mar 24 12:42:48 PM PDT 24 6791932821 ps
T859 /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.2783398439 Mar 24 12:42:51 PM PDT 24 Mar 24 12:42:57 PM PDT 24 2014724195 ps
T860 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.1910442116 Mar 24 12:42:37 PM PDT 24 Mar 24 12:42:40 PM PDT 24 2679322341 ps
T861 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.1399184527 Mar 24 12:42:46 PM PDT 24 Mar 24 12:42:47 PM PDT 24 2122592258 ps
T862 /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.1706046880 Mar 24 12:42:48 PM PDT 24 Mar 24 12:42:54 PM PDT 24 2009330754 ps
T863 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.3001958761 Mar 24 12:42:49 PM PDT 24 Mar 24 12:42:52 PM PDT 24 2048086969 ps
T864 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.3652964145 Mar 24 12:42:45 PM PDT 24 Mar 24 12:42:49 PM PDT 24 2120142249 ps
T865 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.1148510584 Mar 24 12:42:52 PM PDT 24 Mar 24 12:42:58 PM PDT 24 10145321750 ps
T866 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.1540094046 Mar 24 12:42:56 PM PDT 24 Mar 24 12:43:02 PM PDT 24 2038849408 ps
T867 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.4010958812 Mar 24 12:42:55 PM PDT 24 Mar 24 12:43:01 PM PDT 24 2027024712 ps
T868 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.2151203944 Mar 24 12:42:58 PM PDT 24 Mar 24 12:43:01 PM PDT 24 2139678616 ps
T869 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.1274774553 Mar 24 12:43:02 PM PDT 24 Mar 24 12:43:04 PM PDT 24 2061826736 ps
T870 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.2549871910 Mar 24 12:42:44 PM PDT 24 Mar 24 12:43:43 PM PDT 24 42550129393 ps
T871 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.2713879100 Mar 24 12:42:56 PM PDT 24 Mar 24 12:43:00 PM PDT 24 4525255232 ps
T872 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.398528158 Mar 24 12:42:47 PM PDT 24 Mar 24 12:42:53 PM PDT 24 2010078732 ps
T873 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.2060300680 Mar 24 12:42:54 PM PDT 24 Mar 24 12:43:01 PM PDT 24 2068642314 ps
T874 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.2083212856 Mar 24 12:42:44 PM PDT 24 Mar 24 12:43:12 PM PDT 24 9839671320 ps
T875 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.1185432256 Mar 24 12:42:50 PM PDT 24 Mar 24 12:42:58 PM PDT 24 2027543761 ps
T876 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.487296718 Mar 24 12:42:47 PM PDT 24 Mar 24 12:42:50 PM PDT 24 3373921592 ps
T877 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.740673726 Mar 24 12:42:46 PM PDT 24 Mar 24 12:42:54 PM PDT 24 2048053233 ps
T878 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.2175574014 Mar 24 12:42:33 PM PDT 24 Mar 24 12:42:37 PM PDT 24 2061478641 ps
T879 /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.1060578730 Mar 24 12:43:00 PM PDT 24 Mar 24 12:43:03 PM PDT 24 2017647222 ps
T880 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.3099587882 Mar 24 12:42:36 PM PDT 24 Mar 24 12:42:39 PM PDT 24 2019485169 ps
T881 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.3874362428 Mar 24 12:42:43 PM PDT 24 Mar 24 12:42:44 PM PDT 24 2066590446 ps
T882 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.238786424 Mar 24 12:42:50 PM PDT 24 Mar 24 12:42:53 PM PDT 24 2018122288 ps
T883 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.4231091606 Mar 24 12:42:47 PM PDT 24 Mar 24 12:42:54 PM PDT 24 2127934671 ps
T884 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.3271978258 Mar 24 12:42:52 PM PDT 24 Mar 24 12:42:54 PM PDT 24 2288536828 ps
T885 /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.1498420270 Mar 24 12:42:50 PM PDT 24 Mar 24 12:42:52 PM PDT 24 2023513599 ps
T886 /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.2504970992 Mar 24 12:42:57 PM PDT 24 Mar 24 12:42:59 PM PDT 24 2038776809 ps
T887 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.679407644 Mar 24 12:42:41 PM PDT 24 Mar 24 12:42:43 PM PDT 24 2124174569 ps
T888 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.949763415 Mar 24 12:42:52 PM PDT 24 Mar 24 12:43:09 PM PDT 24 22384042040 ps
T889 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.1601714583 Mar 24 12:42:32 PM PDT 24 Mar 24 12:42:44 PM PDT 24 4009987758 ps
T890 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.2438484904 Mar 24 12:42:46 PM PDT 24 Mar 24 12:42:47 PM PDT 24 2050871422 ps
T891 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.3630227459 Mar 24 12:42:47 PM PDT 24 Mar 24 12:43:17 PM PDT 24 22266128856 ps
T892 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.786736373 Mar 24 12:43:05 PM PDT 24 Mar 24 12:43:07 PM PDT 24 2040419271 ps
T893 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.2921295709 Mar 24 12:42:48 PM PDT 24 Mar 24 12:43:18 PM PDT 24 22198965214 ps
T894 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.663493045 Mar 24 12:43:03 PM PDT 24 Mar 24 12:43:07 PM PDT 24 2630140284 ps
T895 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.2606437394 Mar 24 12:42:56 PM PDT 24 Mar 24 12:42:59 PM PDT 24 2018972759 ps
T896 /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.2688534096 Mar 24 12:42:47 PM PDT 24 Mar 24 12:42:53 PM PDT 24 2008628469 ps
T897 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.975176281 Mar 24 12:43:07 PM PDT 24 Mar 24 12:43:14 PM PDT 24 2149125503 ps
T898 /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.2111064797 Mar 24 12:42:49 PM PDT 24 Mar 24 12:42:52 PM PDT 24 2017679305 ps
T899 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.150348308 Mar 24 12:42:47 PM PDT 24 Mar 24 12:42:53 PM PDT 24 2037772634 ps
T900 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.4247926299 Mar 24 12:43:01 PM PDT 24 Mar 24 12:43:21 PM PDT 24 9685077517 ps
T901 /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.965763457 Mar 24 12:42:55 PM PDT 24 Mar 24 12:43:01 PM PDT 24 2009065169 ps
T902 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.1519102440 Mar 24 12:42:46 PM PDT 24 Mar 24 12:42:49 PM PDT 24 2367603190 ps
T903 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.277025765 Mar 24 12:42:52 PM PDT 24 Mar 24 12:42:55 PM PDT 24 2107248206 ps
T904 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.2777394658 Mar 24 12:42:59 PM PDT 24 Mar 24 12:43:21 PM PDT 24 42606341574 ps
T905 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.828511510 Mar 24 12:42:39 PM PDT 24 Mar 24 12:42:48 PM PDT 24 2105636728 ps
T906 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.2610950318 Mar 24 12:42:47 PM PDT 24 Mar 24 12:42:53 PM PDT 24 2033592156 ps
T907 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.1815220887 Mar 24 12:42:59 PM PDT 24 Mar 24 12:43:05 PM PDT 24 23222395536 ps
T908 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.359055299 Mar 24 12:42:51 PM PDT 24 Mar 24 12:43:11 PM PDT 24 7726067220 ps
T909 /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.568507217 Mar 24 12:43:06 PM PDT 24 Mar 24 12:43:08 PM PDT 24 2025167483 ps
T910 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.2696218066 Mar 24 12:42:42 PM PDT 24 Mar 24 12:42:45 PM PDT 24 2248904433 ps
T911 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.2187382051 Mar 24 12:42:46 PM PDT 24 Mar 24 12:42:49 PM PDT 24 2144340312 ps

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.344859466
Short name T15
Test name
Test status
Simulation time 27086143028 ps
CPU time 36.03 seconds
Started Mar 24 01:15:33 PM PDT 24
Finished Mar 24 01:16:09 PM PDT 24
Peak memory 202348 kb
Host smart-4708b0af-8b07-49e9-accb-fb9442270471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344859466 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect_wi
th_pre_cond.344859466
Directory /workspace/20.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.3850693755
Short name T21
Test name
Test status
Simulation time 63856660745 ps
CPU time 33.98 seconds
Started Mar 24 01:16:20 PM PDT 24
Finished Mar 24 01:16:54 PM PDT 24
Peak memory 210656 kb
Host smart-b0ba843c-72da-46a4-8ee8-3e62111b94e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850693755 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_stress_all_with_rand_reset.3850693755
Directory /workspace/36.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.504947064
Short name T44
Test name
Test status
Simulation time 104595799279 ps
CPU time 65.72 seconds
Started Mar 24 01:15:30 PM PDT 24
Finished Mar 24 01:16:36 PM PDT 24
Peak memory 210704 kb
Host smart-3787267b-f04e-4992-a755-25146a14c18e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504947064 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_stress_all_with_rand_reset.504947064
Directory /workspace/16.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.4107451547
Short name T12
Test name
Test status
Simulation time 169084509490 ps
CPU time 110.13 seconds
Started Mar 24 01:15:11 PM PDT 24
Finished Mar 24 01:17:01 PM PDT 24
Peak memory 202300 kb
Host smart-abc488c6-d8ef-4797-9228-f5bd47f2cbe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107451547 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect_w
ith_pre_cond.4107451547
Directory /workspace/10.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all.2046071209
Short name T13
Test name
Test status
Simulation time 10203782491 ps
CPU time 7.81 seconds
Started Mar 24 01:15:40 PM PDT 24
Finished Mar 24 01:15:49 PM PDT 24
Peak memory 202136 kb
Host smart-53adc4d5-d259-4697-9d22-4a23fa359e01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046071209 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_s
tress_all.2046071209
Directory /workspace/23.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_feature_disable.3379482541
Short name T38
Test name
Test status
Simulation time 41613282589 ps
CPU time 54.15 seconds
Started Mar 24 01:14:45 PM PDT 24
Finished Mar 24 01:15:39 PM PDT 24
Peak memory 202052 kb
Host smart-c3912c1c-80d2-42bd-a45d-8e2bb59a1e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379482541 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_feature_disable.3379482541
Directory /workspace/0.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.3976330274
Short name T352
Test name
Test status
Simulation time 43495880135 ps
CPU time 29.05 seconds
Started Mar 24 12:43:00 PM PDT 24
Finished Mar 24 12:43:29 PM PDT 24
Peak memory 201416 kb
Host smart-d7d9191c-4b7b-4d3d-9c4a-7da299c5ecbd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976330274 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_tl_intg_err.3976330274
Directory /workspace/12.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.2754054844
Short name T76
Test name
Test status
Simulation time 599910891759 ps
CPU time 40.49 seconds
Started Mar 24 01:15:52 PM PDT 24
Finished Mar 24 01:16:33 PM PDT 24
Peak memory 218680 kb
Host smart-32f97835-f800-4ad0-9956-aece2fb54aa2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754054844 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_stress_all_with_rand_reset.2754054844
Directory /workspace/30.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.3985541483
Short name T136
Test name
Test status
Simulation time 179939202706 ps
CPU time 85.67 seconds
Started Mar 24 01:15:26 PM PDT 24
Finished Mar 24 01:16:52 PM PDT 24
Peak memory 210764 kb
Host smart-22d67f9b-60b2-49d1-9510-1c20f300e4a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985541483 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_stress_all_with_rand_reset.3985541483
Directory /workspace/14.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all.1126337468
Short name T3
Test name
Test status
Simulation time 119741583827 ps
CPU time 153.55 seconds
Started Mar 24 01:16:18 PM PDT 24
Finished Mar 24 01:18:52 PM PDT 24
Peak memory 202220 kb
Host smart-f2211046-3857-4fbc-872e-cbdb64f5cb52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126337468 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_s
tress_all.1126337468
Directory /workspace/40.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.1259500639
Short name T387
Test name
Test status
Simulation time 116653425809 ps
CPU time 71.13 seconds
Started Mar 24 01:16:36 PM PDT 24
Finished Mar 24 01:17:47 PM PDT 24
Peak memory 218772 kb
Host smart-ab1024a4-a6a0-4e6b-b341-5ac5a7ca330f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259500639 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_stress_all_with_rand_reset.1259500639
Directory /workspace/47.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.2501312685
Short name T244
Test name
Test status
Simulation time 106174173801 ps
CPU time 59.01 seconds
Started Mar 24 01:15:35 PM PDT 24
Finished Mar 24 01:16:34 PM PDT 24
Peak memory 210668 kb
Host smart-d65d3992-fa98-4126-b657-8261dfe1103f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501312685 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_stress_all_with_rand_reset.2501312685
Directory /workspace/21.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.3864325736
Short name T259
Test name
Test status
Simulation time 2528860119 ps
CPU time 3.87 seconds
Started Mar 24 12:43:05 PM PDT 24
Finished Mar 24 12:43:09 PM PDT 24
Peak memory 201368 kb
Host smart-a2c4795e-408f-4aff-8bf9-d3e2a9b52d1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864325736 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_erro
rs.3864325736
Directory /workspace/17.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.577914773
Short name T149
Test name
Test status
Simulation time 111023676582 ps
CPU time 70.77 seconds
Started Mar 24 01:14:57 PM PDT 24
Finished Mar 24 01:16:08 PM PDT 24
Peak memory 214452 kb
Host smart-7da6bf8a-9c11-498e-9af9-a1517ce5f5cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577914773 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_stress_all_with_rand_reset.577914773
Directory /workspace/4.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.2724798526
Short name T146
Test name
Test status
Simulation time 158860884527 ps
CPU time 179.09 seconds
Started Mar 24 01:16:03 PM PDT 24
Finished Mar 24 01:19:02 PM PDT 24
Peak memory 218832 kb
Host smart-21b641b4-5171-4b39-9e02-75b71452782f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724798526 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_stress_all_with_rand_reset.2724798526
Directory /workspace/33.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_alert_test.4113490705
Short name T112
Test name
Test status
Simulation time 2034652665 ps
CPU time 1.92 seconds
Started Mar 24 01:14:47 PM PDT 24
Finished Mar 24 01:14:49 PM PDT 24
Peak memory 202112 kb
Host smart-dfc861eb-3816-4480-b761-aa997809745d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113490705 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_alert_tes
t.4113490705
Directory /workspace/2.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.986770929
Short name T28
Test name
Test status
Simulation time 58820865964 ps
CPU time 149.99 seconds
Started Mar 24 01:16:33 PM PDT 24
Finished Mar 24 01:19:03 PM PDT 24
Peak memory 202252 kb
Host smart-2501876f-255b-4d43-bb23-a532be7db738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986770929 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.sysrst_ctrl_combo_detect_wi
th_pre_cond.986770929
Directory /workspace/66.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect.1551963034
Short name T115
Test name
Test status
Simulation time 129645537172 ps
CPU time 70.88 seconds
Started Mar 24 01:14:46 PM PDT 24
Finished Mar 24 01:15:57 PM PDT 24
Peak memory 202236 kb
Host smart-71d997b3-cb8f-4cd5-aa5f-0eb9687e48db
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551963034 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ct
rl_combo_detect.1551963034
Directory /workspace/3.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.1983680420
Short name T315
Test name
Test status
Simulation time 2077844056 ps
CPU time 3.7 seconds
Started Mar 24 12:42:49 PM PDT 24
Finished Mar 24 12:42:53 PM PDT 24
Peak memory 201208 kb
Host smart-8bf16bf0-9f44-4b94-b625-2fa8a348734f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983680420 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_r
w.1983680420
Directory /workspace/0.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.2580670377
Short name T81
Test name
Test status
Simulation time 6666085032 ps
CPU time 2.57 seconds
Started Mar 24 01:15:55 PM PDT 24
Finished Mar 24 01:15:58 PM PDT 24
Peak memory 201964 kb
Host smart-ec3c237b-a7cd-4e9d-8a25-3d52d28e16d0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580670377 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_
ctrl_ultra_low_pwr.2580670377
Directory /workspace/31.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.586984882
Short name T27
Test name
Test status
Simulation time 38571613674 ps
CPU time 107.57 seconds
Started Mar 24 01:16:20 PM PDT 24
Finished Mar 24 01:18:08 PM PDT 24
Peak memory 210600 kb
Host smart-d1fddba6-0b96-40dc-98a2-b4370a32743b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586984882 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_stress_all_with_rand_reset.586984882
Directory /workspace/39.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.3890281809
Short name T91
Test name
Test status
Simulation time 43079062829 ps
CPU time 16.42 seconds
Started Mar 24 01:15:13 PM PDT 24
Finished Mar 24 01:15:30 PM PDT 24
Peak memory 210636 kb
Host smart-f756336e-113f-458b-aad3-cf845c4f01b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890281809 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_stress_all_with_rand_reset.3890281809
Directory /workspace/8.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.4228396134
Short name T145
Test name
Test status
Simulation time 48587203763 ps
CPU time 136.95 seconds
Started Mar 24 01:16:15 PM PDT 24
Finished Mar 24 01:18:32 PM PDT 24
Peak memory 210672 kb
Host smart-5e0bfb8b-70bb-409b-ad0c-cd03fa50036e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228396134 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_stress_all_with_rand_reset.4228396134
Directory /workspace/35.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all.763230019
Short name T152
Test name
Test status
Simulation time 125406472505 ps
CPU time 92.45 seconds
Started Mar 24 01:15:25 PM PDT 24
Finished Mar 24 01:16:58 PM PDT 24
Peak memory 202296 kb
Host smart-e65bf84c-5a0f-4c01-9efb-817d4c418c25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763230019 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_st
ress_all.763230019
Directory /workspace/12.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all.1314074863
Short name T183
Test name
Test status
Simulation time 12543580157 ps
CPU time 6.27 seconds
Started Mar 24 01:15:26 PM PDT 24
Finished Mar 24 01:15:33 PM PDT 24
Peak memory 202124 kb
Host smart-f6a8b8f3-a83e-4f6e-9a48-d7ac22302fc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314074863 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_s
tress_all.1314074863
Directory /workspace/11.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect.528055597
Short name T90
Test name
Test status
Simulation time 139627018582 ps
CPU time 87.32 seconds
Started Mar 24 01:15:28 PM PDT 24
Finished Mar 24 01:16:56 PM PDT 24
Peak memory 202228 kb
Host smart-65482b53-7740-45d7-be27-b1f230dd90a3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528055597 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ct
rl_combo_detect.528055597
Directory /workspace/16.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.3384403886
Short name T207
Test name
Test status
Simulation time 85843606888 ps
CPU time 53.47 seconds
Started Mar 24 01:15:43 PM PDT 24
Finished Mar 24 01:16:37 PM PDT 24
Peak memory 210704 kb
Host smart-17dafa83-1db1-436c-998c-d7b4663e5dfc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384403886 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_stress_all_with_rand_reset.3384403886
Directory /workspace/27.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.1307164759
Short name T331
Test name
Test status
Simulation time 107930172984 ps
CPU time 56.98 seconds
Started Mar 24 01:16:34 PM PDT 24
Finished Mar 24 01:17:31 PM PDT 24
Peak memory 202208 kb
Host smart-c4d0a6bf-2cf2-42bc-af3f-66fa3c91966b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307164759 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.sysrst_ctrl_combo_detect_w
ith_pre_cond.1307164759
Directory /workspace/86.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_sec_cm.3316508049
Short name T272
Test name
Test status
Simulation time 22009461094 ps
CPU time 54.56 seconds
Started Mar 24 01:14:45 PM PDT 24
Finished Mar 24 01:15:40 PM PDT 24
Peak memory 221780 kb
Host smart-5a0f08e7-acb7-4734-aefe-2fdf6aa9cf6d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316508049 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_sec_cm.3316508049
Directory /workspace/0.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.1609310657
Short name T125
Test name
Test status
Simulation time 67473023256 ps
CPU time 46.83 seconds
Started Mar 24 01:16:43 PM PDT 24
Finished Mar 24 01:17:30 PM PDT 24
Peak memory 202288 kb
Host smart-cc963605-9642-4c7d-8dc7-153b04c3ac90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609310657 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.sysrst_ctrl_combo_detect_w
ith_pre_cond.1609310657
Directory /workspace/73.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all.868770904
Short name T333
Test name
Test status
Simulation time 200743874675 ps
CPU time 130.78 seconds
Started Mar 24 01:14:50 PM PDT 24
Finished Mar 24 01:17:01 PM PDT 24
Peak memory 202204 kb
Host smart-72ecf7bb-0451-4087-9061-6bc5bf91adce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868770904 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_str
ess_all.868770904
Directory /workspace/1.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.3590028196
Short name T322
Test name
Test status
Simulation time 2058713000 ps
CPU time 5.91 seconds
Started Mar 24 12:42:35 PM PDT 24
Finished Mar 24 12:42:41 PM PDT 24
Peak memory 201208 kb
Host smart-2ad4f218-fc4e-4ca1-a2af-07afa0864fea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590028196 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_r
w.3590028196
Directory /workspace/5.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.495765025
Short name T348
Test name
Test status
Simulation time 103165833938 ps
CPU time 133.89 seconds
Started Mar 24 01:15:29 PM PDT 24
Finished Mar 24 01:17:43 PM PDT 24
Peak memory 202284 kb
Host smart-fdea03c6-975f-442f-9022-1bbb2267f88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495765025 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect_wi
th_pre_cond.495765025
Directory /workspace/16.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.2752397963
Short name T349
Test name
Test status
Simulation time 119420457037 ps
CPU time 331.4 seconds
Started Mar 24 01:16:33 PM PDT 24
Finished Mar 24 01:22:05 PM PDT 24
Peak memory 202304 kb
Host smart-c10f1cf0-b61c-4251-b584-63307b0c77f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752397963 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.sysrst_ctrl_combo_detect_w
ith_pre_cond.2752397963
Directory /workspace/61.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.2031486106
Short name T359
Test name
Test status
Simulation time 188310214145 ps
CPU time 488.22 seconds
Started Mar 24 01:16:41 PM PDT 24
Finished Mar 24 01:24:50 PM PDT 24
Peak memory 202284 kb
Host smart-582893d8-7583-4c22-a6d9-335596b53fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031486106 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.sysrst_ctrl_combo_detect_w
ith_pre_cond.2031486106
Directory /workspace/78.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.3823648853
Short name T353
Test name
Test status
Simulation time 42447428716 ps
CPU time 110.99 seconds
Started Mar 24 12:43:12 PM PDT 24
Finished Mar 24 12:45:08 PM PDT 24
Peak memory 201448 kb
Host smart-ee0b7ba4-ed78-46c1-8dd0-633f1c2ff9af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823648853 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_tl_intg_err.3823648853
Directory /workspace/18.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.3783775244
Short name T48
Test name
Test status
Simulation time 22593664904 ps
CPU time 50.59 seconds
Started Mar 24 01:16:19 PM PDT 24
Finished Mar 24 01:17:09 PM PDT 24
Peak memory 210616 kb
Host smart-35d45097-7d45-47c7-9fb8-979c6126d7c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783775244 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_stress_all_with_rand_reset.3783775244
Directory /workspace/42.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.4055735866
Short name T382
Test name
Test status
Simulation time 66445444687 ps
CPU time 110.17 seconds
Started Mar 24 01:15:15 PM PDT 24
Finished Mar 24 01:17:05 PM PDT 24
Peak memory 202296 kb
Host smart-d447f003-8a77-4bfc-bb4f-a47a545ead05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055735866 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect_w
ith_pre_cond.4055735866
Directory /workspace/11.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect.4050387938
Short name T767
Test name
Test status
Simulation time 36978073647 ps
CPU time 94.71 seconds
Started Mar 24 01:15:25 PM PDT 24
Finished Mar 24 01:16:59 PM PDT 24
Peak memory 202220 kb
Host smart-45f10875-9e56-4fec-a36c-31c431ad631f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050387938 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_c
trl_combo_detect.4050387938
Directory /workspace/14.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect.3469520423
Short name T339
Test name
Test status
Simulation time 78635364009 ps
CPU time 97.04 seconds
Started Mar 24 01:16:13 PM PDT 24
Finished Mar 24 01:17:50 PM PDT 24
Peak memory 202276 kb
Host smart-8d9c72fb-1b8f-4c6a-a25b-79f90c65bbcd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469520423 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_c
trl_combo_detect.3469520423
Directory /workspace/39.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.1844794226
Short name T347
Test name
Test status
Simulation time 118336406267 ps
CPU time 289.67 seconds
Started Mar 24 01:16:30 PM PDT 24
Finished Mar 24 01:21:20 PM PDT 24
Peak memory 202144 kb
Host smart-f55a04a2-8c6b-42d6-9b64-2582da64ccea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844794226 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.sysrst_ctrl_combo_detect_w
ith_pre_cond.1844794226
Directory /workspace/62.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.3132191096
Short name T184
Test name
Test status
Simulation time 1511169631723 ps
CPU time 67.71 seconds
Started Mar 24 01:15:07 PM PDT 24
Finished Mar 24 01:16:15 PM PDT 24
Peak memory 215012 kb
Host smart-4c15a3da-8530-49f3-a127-8382daa66074
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132191096 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_stress_all_with_rand_reset.3132191096
Directory /workspace/6.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.993922698
Short name T78
Test name
Test status
Simulation time 162335058594 ps
CPU time 413.21 seconds
Started Mar 24 01:16:36 PM PDT 24
Finished Mar 24 01:23:29 PM PDT 24
Peak memory 202240 kb
Host smart-8fe8a4b3-965e-49c7-919c-3fe227404744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993922698 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.sysrst_ctrl_combo_detect_wi
th_pre_cond.993922698
Directory /workspace/69.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.1816967596
Short name T370
Test name
Test status
Simulation time 97708203415 ps
CPU time 69.79 seconds
Started Mar 24 01:16:26 PM PDT 24
Finished Mar 24 01:17:37 PM PDT 24
Peak memory 202288 kb
Host smart-fd0185d3-8bd0-4925-b3b3-40391ce30c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816967596 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect_w
ith_pre_cond.1816967596
Directory /workspace/39.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.560579703
Short name T147
Test name
Test status
Simulation time 64358068912 ps
CPU time 39.93 seconds
Started Mar 24 01:14:49 PM PDT 24
Finished Mar 24 01:15:29 PM PDT 24
Peak memory 210720 kb
Host smart-c9437507-70dc-4861-b6fb-84b0641d2170
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560579703 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_stress_all_with_rand_reset.560579703
Directory /workspace/1.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect.466154353
Short name T753
Test name
Test status
Simulation time 92472259176 ps
CPU time 60.79 seconds
Started Mar 24 01:15:39 PM PDT 24
Finished Mar 24 01:16:40 PM PDT 24
Peak memory 202276 kb
Host smart-9ef253da-0bf2-4c60-b351-c1ec4bf4d698
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466154353 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ct
rl_combo_detect.466154353
Directory /workspace/23.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.2802597080
Short name T852
Test name
Test status
Simulation time 5229519843 ps
CPU time 15.48 seconds
Started Mar 24 12:42:37 PM PDT 24
Finished Mar 24 12:42:56 PM PDT 24
Peak memory 201412 kb
Host smart-e19a26aa-04b1-4f3e-8eda-b3d0efffd51e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802597080 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.sysrst_ctrl_same_csr_outstanding.2802597080
Directory /workspace/0.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.2380315868
Short name T260
Test name
Test status
Simulation time 2176464069 ps
CPU time 4.02 seconds
Started Mar 24 12:42:43 PM PDT 24
Finished Mar 24 12:42:47 PM PDT 24
Peak memory 201496 kb
Host smart-dd167657-c02c-4088-943b-4b04bb80ede8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380315868 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_error
s.2380315868
Directory /workspace/1.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_feature_disable.2341709612
Short name T58
Test name
Test status
Simulation time 41034749705 ps
CPU time 26.88 seconds
Started Mar 24 01:14:56 PM PDT 24
Finished Mar 24 01:15:23 PM PDT 24
Peak memory 202044 kb
Host smart-200183e6-b353-4733-97c0-fc3792da0a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341709612 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_feature_disable.2341709612
Directory /workspace/1.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.3334312215
Short name T356
Test name
Test status
Simulation time 42485554064 ps
CPU time 112.37 seconds
Started Mar 24 12:42:56 PM PDT 24
Finished Mar 24 12:44:48 PM PDT 24
Peak memory 201416 kb
Host smart-9363b72d-6da6-4ed7-969f-2e3f1646b9b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334312215 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_tl_intg_err.3334312215
Directory /workspace/10.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect.2457469297
Short name T95
Test name
Test status
Simulation time 147622217774 ps
CPU time 26.44 seconds
Started Mar 24 01:15:14 PM PDT 24
Finished Mar 24 01:15:41 PM PDT 24
Peak memory 202288 kb
Host smart-1843d552-ae54-4004-b422-b7001e97bebe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457469297 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_c
trl_combo_detect.2457469297
Directory /workspace/11.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect.1473390373
Short name T246
Test name
Test status
Simulation time 129836172248 ps
CPU time 174.04 seconds
Started Mar 24 01:15:26 PM PDT 24
Finished Mar 24 01:18:21 PM PDT 24
Peak memory 202236 kb
Host smart-81e75a6f-2c1b-4565-ae3f-2ce66f233ea2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473390373 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_c
trl_combo_detect.1473390373
Directory /workspace/12.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.3567074570
Short name T358
Test name
Test status
Simulation time 116269516187 ps
CPU time 153.69 seconds
Started Mar 24 01:15:28 PM PDT 24
Finished Mar 24 01:18:02 PM PDT 24
Peak memory 202316 kb
Host smart-4821ef92-d71d-4113-aa77-066efeb667bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567074570 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect_w
ith_pre_cond.3567074570
Directory /workspace/13.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.1615960533
Short name T680
Test name
Test status
Simulation time 4260633295213 ps
CPU time 129.35 seconds
Started Mar 24 01:15:22 PM PDT 24
Finished Mar 24 01:17:32 PM PDT 24
Peak memory 202052 kb
Host smart-9d36ac3e-2012-40ba-97e4-538c23d4c4f9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615960533 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_ultra_low_pwr.1615960533
Directory /workspace/13.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect.3343865288
Short name T607
Test name
Test status
Simulation time 171956635173 ps
CPU time 131.41 seconds
Started Mar 24 01:14:46 PM PDT 24
Finished Mar 24 01:16:58 PM PDT 24
Peak memory 202320 kb
Host smart-8ea29805-6eae-4c11-a601-12e0d9b69e80
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343865288 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ct
rl_combo_detect.3343865288
Directory /workspace/2.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.2948265261
Short name T346
Test name
Test status
Simulation time 66632587342 ps
CPU time 165.99 seconds
Started Mar 24 01:14:46 PM PDT 24
Finished Mar 24 01:17:32 PM PDT 24
Peak memory 202292 kb
Host smart-04ae9f6d-3a6e-4b84-9e3a-b5587c0d5940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948265261 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_wi
th_pre_cond.2948265261
Directory /workspace/2.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.1603481403
Short name T385
Test name
Test status
Simulation time 60260583179 ps
CPU time 161.7 seconds
Started Mar 24 01:15:33 PM PDT 24
Finished Mar 24 01:18:15 PM PDT 24
Peak memory 202316 kb
Host smart-aa346b77-d0cf-4d39-bc19-045eeb6eecd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603481403 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_combo_detect_w
ith_pre_cond.1603481403
Directory /workspace/22.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.2880526173
Short name T363
Test name
Test status
Simulation time 328522320158 ps
CPU time 850.96 seconds
Started Mar 24 01:15:42 PM PDT 24
Finished Mar 24 01:29:53 PM PDT 24
Peak memory 202224 kb
Host smart-22a38ec5-9b9f-4da4-977f-eb93680cf8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880526173 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_combo_detect_w
ith_pre_cond.2880526173
Directory /workspace/25.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.1418813131
Short name T371
Test name
Test status
Simulation time 117478412501 ps
CPU time 128.36 seconds
Started Mar 24 01:16:33 PM PDT 24
Finished Mar 24 01:18:42 PM PDT 24
Peak memory 202316 kb
Host smart-8dc4d365-de60-476d-a6ec-5b76fd968c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418813131 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect_w
ith_pre_cond.1418813131
Directory /workspace/41.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.3900030160
Short name T345
Test name
Test status
Simulation time 48698094418 ps
CPU time 23.49 seconds
Started Mar 24 01:16:26 PM PDT 24
Finished Mar 24 01:16:51 PM PDT 24
Peak memory 202176 kb
Host smart-1fb31318-2fbd-44ef-857a-29e916f7decf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900030160 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect_w
ith_pre_cond.3900030160
Directory /workspace/42.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.366720348
Short name T73
Test name
Test status
Simulation time 97448751766 ps
CPU time 66.61 seconds
Started Mar 24 01:15:06 PM PDT 24
Finished Mar 24 01:16:13 PM PDT 24
Peak memory 202220 kb
Host smart-5cb53b09-89dc-4618-8887-e27b4890859c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366720348 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect_wit
h_pre_cond.366720348
Directory /workspace/7.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.280060616
Short name T343
Test name
Test status
Simulation time 131559578928 ps
CPU time 88.71 seconds
Started Mar 24 01:16:34 PM PDT 24
Finished Mar 24 01:18:02 PM PDT 24
Peak memory 202232 kb
Host smart-aeaf4d48-9a97-4513-93a2-a9a30475383f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280060616 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.sysrst_ctrl_combo_detect_wi
th_pre_cond.280060616
Directory /workspace/71.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.1952154039
Short name T77
Test name
Test status
Simulation time 108494665462 ps
CPU time 274.61 seconds
Started Mar 24 01:16:34 PM PDT 24
Finished Mar 24 01:21:09 PM PDT 24
Peak memory 202260 kb
Host smart-40c9093a-86ad-4f38-91eb-c5de9be396f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952154039 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.sysrst_ctrl_combo_detect_w
ith_pre_cond.1952154039
Directory /workspace/77.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.979168138
Short name T369
Test name
Test status
Simulation time 55959831678 ps
CPU time 20.25 seconds
Started Mar 24 01:16:35 PM PDT 24
Finished Mar 24 01:16:56 PM PDT 24
Peak memory 202272 kb
Host smart-744c713b-fbae-4517-b800-439b00f48ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979168138 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.sysrst_ctrl_combo_detect_wi
th_pre_cond.979168138
Directory /workspace/79.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.3302905718
Short name T373
Test name
Test status
Simulation time 84498699455 ps
CPU time 35.73 seconds
Started Mar 24 01:16:42 PM PDT 24
Finished Mar 24 01:17:17 PM PDT 24
Peak memory 202236 kb
Host smart-56696ccc-beca-4025-9211-ed26025c1df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302905718 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.sysrst_ctrl_combo_detect_w
ith_pre_cond.3302905718
Directory /workspace/91.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.2808907450
Short name T249
Test name
Test status
Simulation time 93744508619 ps
CPU time 125.79 seconds
Started Mar 24 01:16:30 PM PDT 24
Finished Mar 24 01:18:35 PM PDT 24
Peak memory 202308 kb
Host smart-d74c6d2f-7ca2-49f5-b999-b16490789004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808907450 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.sysrst_ctrl_combo_detect_w
ith_pre_cond.2808907450
Directory /workspace/59.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.1433260306
Short name T314
Test name
Test status
Simulation time 2932712574 ps
CPU time 9.74 seconds
Started Mar 24 12:42:33 PM PDT 24
Finished Mar 24 12:42:44 PM PDT 24
Peak memory 201464 kb
Host smart-eaaf64de-d813-4429-9ccb-bd817daf5aba
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433260306 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_aliasing.1433260306
Directory /workspace/0.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.4074522472
Short name T832
Test name
Test status
Simulation time 75604039814 ps
CPU time 193.01 seconds
Started Mar 24 12:42:34 PM PDT 24
Finished Mar 24 12:45:48 PM PDT 24
Peak memory 201476 kb
Host smart-c4af8008-ce33-4582-9e9f-22f5d04b91eb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074522472 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_bit_bash.4074522472
Directory /workspace/0.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.2246036516
Short name T819
Test name
Test status
Simulation time 6046898456 ps
CPU time 4.47 seconds
Started Mar 24 12:42:28 PM PDT 24
Finished Mar 24 12:42:33 PM PDT 24
Peak memory 201292 kb
Host smart-9897d363-7790-4c9f-b289-3b364da4a9f0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246036516 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_hw_reset.2246036516
Directory /workspace/0.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.346987744
Short name T847
Test name
Test status
Simulation time 2100156419 ps
CPU time 5.92 seconds
Started Mar 24 12:42:35 PM PDT 24
Finished Mar 24 12:42:41 PM PDT 24
Peak memory 201296 kb
Host smart-49187878-86fe-44d0-8472-343a0b009cbc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346987744 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_mem_rw_with_rand_reset.346987744
Directory /workspace/0.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.3099587882
Short name T880
Test name
Test status
Simulation time 2019485169 ps
CPU time 2.93 seconds
Started Mar 24 12:42:36 PM PDT 24
Finished Mar 24 12:42:39 PM PDT 24
Peak memory 200672 kb
Host smart-ee39051f-a4da-40ed-b146-b893fc09cfac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099587882 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_intr_tes
t.3099587882
Directory /workspace/0.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.1519102440
Short name T902
Test name
Test status
Simulation time 2367603190 ps
CPU time 2.82 seconds
Started Mar 24 12:42:46 PM PDT 24
Finished Mar 24 12:42:49 PM PDT 24
Peak memory 201468 kb
Host smart-daddd9bc-ddff-448b-b665-7bbeab5e57cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519102440 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_error
s.1519102440
Directory /workspace/0.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.1225622267
Short name T816
Test name
Test status
Simulation time 22499368640 ps
CPU time 14.78 seconds
Started Mar 24 12:42:35 PM PDT 24
Finished Mar 24 12:42:50 PM PDT 24
Peak memory 201504 kb
Host smart-883a9781-6290-48fb-a7a9-81ec64145812
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225622267 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_tl_intg_err.1225622267
Directory /workspace/0.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.1910442116
Short name T860
Test name
Test status
Simulation time 2679322341 ps
CPU time 3.42 seconds
Started Mar 24 12:42:37 PM PDT 24
Finished Mar 24 12:42:40 PM PDT 24
Peak memory 201396 kb
Host smart-aed93ec0-feb1-4dbc-8e8a-d1440eb44dfa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910442116 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_aliasing.1910442116
Directory /workspace/1.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.938695193
Short name T320
Test name
Test status
Simulation time 59309660879 ps
CPU time 294.75 seconds
Started Mar 24 12:42:47 PM PDT 24
Finished Mar 24 12:47:41 PM PDT 24
Peak memory 201400 kb
Host smart-c17ce8f3-0631-4027-8a22-91142caf723f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938695193 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_
csr_bit_bash.938695193
Directory /workspace/1.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.1604325156
Short name T319
Test name
Test status
Simulation time 4023750662 ps
CPU time 5.85 seconds
Started Mar 24 12:42:49 PM PDT 24
Finished Mar 24 12:42:55 PM PDT 24
Peak memory 201172 kb
Host smart-f8d035e1-6bef-41c6-8c8b-d5750c7961b3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604325156 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_hw_reset.1604325156
Directory /workspace/1.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.828511510
Short name T905
Test name
Test status
Simulation time 2105636728 ps
CPU time 7 seconds
Started Mar 24 12:42:39 PM PDT 24
Finished Mar 24 12:42:48 PM PDT 24
Peak memory 201216 kb
Host smart-bb7115b5-1d3a-4d81-8580-0bbe48e8db0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828511510 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_mem_rw_with_rand_reset.828511510
Directory /workspace/1.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.3340887463
Short name T326
Test name
Test status
Simulation time 2155909843 ps
CPU time 1.22 seconds
Started Mar 24 12:42:45 PM PDT 24
Finished Mar 24 12:42:46 PM PDT 24
Peak memory 201204 kb
Host smart-eb53695c-a307-4bdf-9bfd-7a9a41f623a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340887463 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_r
w.3340887463
Directory /workspace/1.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.786736373
Short name T892
Test name
Test status
Simulation time 2040419271 ps
CPU time 1.85 seconds
Started Mar 24 12:43:05 PM PDT 24
Finished Mar 24 12:43:07 PM PDT 24
Peak memory 200628 kb
Host smart-36a0327d-6411-449d-a2e1-d887153b43c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786736373 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_intr_test
.786736373
Directory /workspace/1.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.3443094188
Short name T858
Test name
Test status
Simulation time 6791932821 ps
CPU time 6.89 seconds
Started Mar 24 12:42:42 PM PDT 24
Finished Mar 24 12:42:48 PM PDT 24
Peak memory 201404 kb
Host smart-528e8c55-c316-4303-b7a3-a81f0036c06c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443094188 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.sysrst_ctrl_same_csr_outstanding.3443094188
Directory /workspace/1.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.2921295709
Short name T893
Test name
Test status
Simulation time 22198965214 ps
CPU time 29.56 seconds
Started Mar 24 12:42:48 PM PDT 24
Finished Mar 24 12:43:18 PM PDT 24
Peak memory 201468 kb
Host smart-4e1bfc3e-a71a-44af-b872-ebb3a4a7863c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921295709 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_tl_intg_err.2921295709
Directory /workspace/1.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.523242013
Short name T379
Test name
Test status
Simulation time 2115679810 ps
CPU time 6.76 seconds
Started Mar 24 12:43:03 PM PDT 24
Finished Mar 24 12:43:10 PM PDT 24
Peak memory 201272 kb
Host smart-9d9faf1a-824b-4c83-b98c-b204baffc191
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523242013 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_mem_rw_with_rand_reset.523242013
Directory /workspace/10.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.1328700825
Short name T841
Test name
Test status
Simulation time 2067216654 ps
CPU time 2.26 seconds
Started Mar 24 12:43:03 PM PDT 24
Finished Mar 24 12:43:06 PM PDT 24
Peak memory 201088 kb
Host smart-1f65effc-13f5-46cb-9a5f-1e18407fc4ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328700825 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_
rw.1328700825
Directory /workspace/10.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.3198811020
Short name T842
Test name
Test status
Simulation time 2051728038 ps
CPU time 1.93 seconds
Started Mar 24 12:43:13 PM PDT 24
Finished Mar 24 12:43:15 PM PDT 24
Peak memory 200748 kb
Host smart-2ce66a4e-c69c-4bd1-83da-f66e6b022464
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198811020 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_intr_te
st.3198811020
Directory /workspace/10.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.2085096969
Short name T843
Test name
Test status
Simulation time 4491799380 ps
CPU time 2.61 seconds
Started Mar 24 12:42:57 PM PDT 24
Finished Mar 24 12:43:00 PM PDT 24
Peak memory 201300 kb
Host smart-3cc8916d-e169-478c-b69f-15a0a477ffb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085096969 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
0.sysrst_ctrl_same_csr_outstanding.2085096969
Directory /workspace/10.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.1137124920
Short name T266
Test name
Test status
Simulation time 2027809824 ps
CPU time 6.46 seconds
Started Mar 24 12:42:50 PM PDT 24
Finished Mar 24 12:42:57 PM PDT 24
Peak memory 201408 kb
Host smart-419aef64-b338-4538-8531-8e152aab25c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137124920 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_erro
rs.1137124920
Directory /workspace/10.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.3271978258
Short name T884
Test name
Test status
Simulation time 2288536828 ps
CPU time 1.42 seconds
Started Mar 24 12:42:52 PM PDT 24
Finished Mar 24 12:42:54 PM PDT 24
Peak memory 201348 kb
Host smart-b77930d6-e3f7-4df7-8032-837b099759af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271978258 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_mem_rw_with_rand_reset.3271978258
Directory /workspace/11.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.4010958812
Short name T867
Test name
Test status
Simulation time 2027024712 ps
CPU time 5.71 seconds
Started Mar 24 12:42:55 PM PDT 24
Finished Mar 24 12:43:01 PM PDT 24
Peak memory 201204 kb
Host smart-6fa1f89d-d34f-415a-be09-df8841f84525
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010958812 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_
rw.4010958812
Directory /workspace/11.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.398528158
Short name T872
Test name
Test status
Simulation time 2010078732 ps
CPU time 5.92 seconds
Started Mar 24 12:42:47 PM PDT 24
Finished Mar 24 12:42:53 PM PDT 24
Peak memory 200604 kb
Host smart-c456c07a-2cf6-4a35-b194-e27aa07c5016
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398528158 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_intr_tes
t.398528158
Directory /workspace/11.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.2871426946
Short name T815
Test name
Test status
Simulation time 4511618315 ps
CPU time 4.23 seconds
Started Mar 24 12:42:57 PM PDT 24
Finished Mar 24 12:43:02 PM PDT 24
Peak memory 201296 kb
Host smart-ebb1cd76-ebed-4e6c-af95-3b93d44c207b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871426946 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
1.sysrst_ctrl_same_csr_outstanding.2871426946
Directory /workspace/11.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.2113596578
Short name T270
Test name
Test status
Simulation time 2084663950 ps
CPU time 2.67 seconds
Started Mar 24 12:42:40 PM PDT 24
Finished Mar 24 12:42:48 PM PDT 24
Peak memory 201360 kb
Host smart-ec3e4a45-885c-4ca2-814a-1b1ca9634b0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113596578 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_erro
rs.2113596578
Directory /workspace/11.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.4030996332
Short name T30
Test name
Test status
Simulation time 22211763288 ps
CPU time 29.16 seconds
Started Mar 24 12:42:47 PM PDT 24
Finished Mar 24 12:43:16 PM PDT 24
Peak memory 201456 kb
Host smart-41f94941-8010-45a5-bca3-1ee56426e5bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030996332 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_tl_intg_err.4030996332
Directory /workspace/11.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.679407644
Short name T887
Test name
Test status
Simulation time 2124174569 ps
CPU time 2.23 seconds
Started Mar 24 12:42:41 PM PDT 24
Finished Mar 24 12:42:43 PM PDT 24
Peak memory 201292 kb
Host smart-e27ece68-0da3-4b96-b756-370abd1f3627
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679407644 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_mem_rw_with_rand_reset.679407644
Directory /workspace/12.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.3001958761
Short name T863
Test name
Test status
Simulation time 2048086969 ps
CPU time 2.12 seconds
Started Mar 24 12:42:49 PM PDT 24
Finished Mar 24 12:42:52 PM PDT 24
Peak memory 201248 kb
Host smart-82dbdaf0-9dd5-4fb1-9fbe-bc2a3c868122
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001958761 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_
rw.3001958761
Directory /workspace/12.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.3874362428
Short name T881
Test name
Test status
Simulation time 2066590446 ps
CPU time 1.36 seconds
Started Mar 24 12:42:43 PM PDT 24
Finished Mar 24 12:42:44 PM PDT 24
Peak memory 200684 kb
Host smart-df86471e-352e-49f0-9f00-9963fc33d9d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874362428 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_intr_te
st.3874362428
Directory /workspace/12.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.3078586306
Short name T19
Test name
Test status
Simulation time 4788129769 ps
CPU time 22.17 seconds
Started Mar 24 12:42:43 PM PDT 24
Finished Mar 24 12:43:05 PM PDT 24
Peak memory 201464 kb
Host smart-ee42a425-82b9-49c9-9fbe-08e9d95e9a1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078586306 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
2.sysrst_ctrl_same_csr_outstanding.3078586306
Directory /workspace/12.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.1699070974
Short name T265
Test name
Test status
Simulation time 2133327409 ps
CPU time 7.57 seconds
Started Mar 24 12:42:45 PM PDT 24
Finished Mar 24 12:42:52 PM PDT 24
Peak memory 201352 kb
Host smart-e54f2f73-532f-4e5c-8780-bca055b5f194
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699070974 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_erro
rs.1699070974
Directory /workspace/12.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.2187382051
Short name T911
Test name
Test status
Simulation time 2144340312 ps
CPU time 3.5 seconds
Started Mar 24 12:42:46 PM PDT 24
Finished Mar 24 12:42:49 PM PDT 24
Peak memory 201276 kb
Host smart-7a300e4b-a181-41ce-a9cd-5888cd21a55e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187382051 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_mem_rw_with_rand_reset.2187382051
Directory /workspace/13.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.2610950318
Short name T906
Test name
Test status
Simulation time 2033592156 ps
CPU time 5.78 seconds
Started Mar 24 12:42:47 PM PDT 24
Finished Mar 24 12:42:53 PM PDT 24
Peak memory 201088 kb
Host smart-a80df551-e1f8-47fa-9b4b-fb7ec44c73cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610950318 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_
rw.2610950318
Directory /workspace/13.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.2976623153
Short name T790
Test name
Test status
Simulation time 2017133550 ps
CPU time 5.66 seconds
Started Mar 24 12:42:52 PM PDT 24
Finished Mar 24 12:42:58 PM PDT 24
Peak memory 200688 kb
Host smart-5c21524c-7501-4985-bcd4-45af3892c7c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976623153 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_intr_te
st.2976623153
Directory /workspace/13.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.2713879100
Short name T871
Test name
Test status
Simulation time 4525255232 ps
CPU time 3.77 seconds
Started Mar 24 12:42:56 PM PDT 24
Finished Mar 24 12:43:00 PM PDT 24
Peak memory 201196 kb
Host smart-00eef319-0cde-4e57-8895-97fa4544a935
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713879100 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
3.sysrst_ctrl_same_csr_outstanding.2713879100
Directory /workspace/13.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.112511537
Short name T835
Test name
Test status
Simulation time 2156235362 ps
CPU time 4.44 seconds
Started Mar 24 12:43:00 PM PDT 24
Finished Mar 24 12:43:04 PM PDT 24
Peak memory 201504 kb
Host smart-10dbba8b-dbb2-4c70-9ad9-a658ec137e4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112511537 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_error
s.112511537
Directory /workspace/13.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.1815220887
Short name T907
Test name
Test status
Simulation time 23222395536 ps
CPU time 5.98 seconds
Started Mar 24 12:42:59 PM PDT 24
Finished Mar 24 12:43:05 PM PDT 24
Peak memory 201432 kb
Host smart-0b989466-5533-4c6c-9620-8183d0996b87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815220887 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_tl_intg_err.1815220887
Directory /workspace/13.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.2890484467
Short name T822
Test name
Test status
Simulation time 2128260800 ps
CPU time 2.48 seconds
Started Mar 24 12:43:00 PM PDT 24
Finished Mar 24 12:43:03 PM PDT 24
Peak memory 201368 kb
Host smart-0d51752e-fa12-4364-9530-5f359e53e9a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890484467 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_mem_rw_with_rand_reset.2890484467
Directory /workspace/14.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.1639563195
Short name T803
Test name
Test status
Simulation time 2044781891 ps
CPU time 2.66 seconds
Started Mar 24 12:42:45 PM PDT 24
Finished Mar 24 12:42:48 PM PDT 24
Peak memory 201100 kb
Host smart-ca0f2682-905e-48c0-b716-205a46acd871
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639563195 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_
rw.1639563195
Directory /workspace/14.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.1575317858
Short name T853
Test name
Test status
Simulation time 2015960537 ps
CPU time 5.41 seconds
Started Mar 24 12:42:41 PM PDT 24
Finished Mar 24 12:42:47 PM PDT 24
Peak memory 200556 kb
Host smart-f7184d6b-c147-4921-b3b8-6cb2f445886d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575317858 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_intr_te
st.1575317858
Directory /workspace/14.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.1085911018
Short name T328
Test name
Test status
Simulation time 5359178391 ps
CPU time 21.97 seconds
Started Mar 24 12:42:59 PM PDT 24
Finished Mar 24 12:43:22 PM PDT 24
Peak memory 201464 kb
Host smart-167c02e6-cb21-43c8-8f14-72119ad8d1ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085911018 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
4.sysrst_ctrl_same_csr_outstanding.1085911018
Directory /workspace/14.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.1185432256
Short name T875
Test name
Test status
Simulation time 2027543761 ps
CPU time 7.01 seconds
Started Mar 24 12:42:50 PM PDT 24
Finished Mar 24 12:42:58 PM PDT 24
Peak memory 201416 kb
Host smart-76212df3-fa3e-467e-9910-ceb48af6bafa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185432256 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_erro
rs.1185432256
Directory /workspace/14.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.2777394658
Short name T904
Test name
Test status
Simulation time 42606341574 ps
CPU time 22.23 seconds
Started Mar 24 12:42:59 PM PDT 24
Finished Mar 24 12:43:21 PM PDT 24
Peak memory 201480 kb
Host smart-60b44cd5-2f73-4963-b42c-9eeb3017b0bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777394658 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_tl_intg_err.2777394658
Directory /workspace/14.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.2060300680
Short name T873
Test name
Test status
Simulation time 2068642314 ps
CPU time 6.43 seconds
Started Mar 24 12:42:54 PM PDT 24
Finished Mar 24 12:43:01 PM PDT 24
Peak memory 201296 kb
Host smart-e3cabe0b-6260-44ed-a04b-2bc21fbcb7b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060300680 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_mem_rw_with_rand_reset.2060300680
Directory /workspace/15.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.1540094046
Short name T866
Test name
Test status
Simulation time 2038849408 ps
CPU time 5.68 seconds
Started Mar 24 12:42:56 PM PDT 24
Finished Mar 24 12:43:02 PM PDT 24
Peak memory 201240 kb
Host smart-f15fac6b-4972-4b68-91ef-82d3a51d22f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540094046 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_
rw.1540094046
Directory /workspace/15.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.3400826834
Short name T825
Test name
Test status
Simulation time 2015826714 ps
CPU time 6.07 seconds
Started Mar 24 12:42:45 PM PDT 24
Finished Mar 24 12:42:51 PM PDT 24
Peak memory 200620 kb
Host smart-2a5f6cdc-1768-45c6-84fa-150fe1e81ab5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400826834 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_intr_te
st.3400826834
Directory /workspace/15.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.2381800395
Short name T849
Test name
Test status
Simulation time 10595230911 ps
CPU time 6.39 seconds
Started Mar 24 12:42:45 PM PDT 24
Finished Mar 24 12:42:51 PM PDT 24
Peak memory 201460 kb
Host smart-96df7eff-9e49-43ba-a80f-38ae9a869d22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381800395 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
5.sysrst_ctrl_same_csr_outstanding.2381800395
Directory /workspace/15.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.3652964145
Short name T864
Test name
Test status
Simulation time 2120142249 ps
CPU time 4.25 seconds
Started Mar 24 12:42:45 PM PDT 24
Finished Mar 24 12:42:49 PM PDT 24
Peak memory 201364 kb
Host smart-54949e61-b1fe-4858-8258-690fc0e8e42b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652964145 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_erro
rs.3652964145
Directory /workspace/15.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.1803921766
Short name T351
Test name
Test status
Simulation time 22254599290 ps
CPU time 61.45 seconds
Started Mar 24 12:42:48 PM PDT 24
Finished Mar 24 12:43:49 PM PDT 24
Peak memory 201440 kb
Host smart-786b4216-336b-432e-914e-3be7e91f1207
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803921766 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_tl_intg_err.1803921766
Directory /workspace/15.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.2472011611
Short name T821
Test name
Test status
Simulation time 2059684974 ps
CPU time 6.63 seconds
Started Mar 24 12:43:03 PM PDT 24
Finished Mar 24 12:43:10 PM PDT 24
Peak memory 201284 kb
Host smart-79bbe1a8-dc67-490a-8dc4-4874cb41eb3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472011611 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_mem_rw_with_rand_reset.2472011611
Directory /workspace/16.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.150348308
Short name T899
Test name
Test status
Simulation time 2037772634 ps
CPU time 6.28 seconds
Started Mar 24 12:42:47 PM PDT 24
Finished Mar 24 12:42:53 PM PDT 24
Peak memory 201204 kb
Host smart-4c3105a2-3ca0-45b4-b83e-0fc78c37f621
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150348308 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_r
w.150348308
Directory /workspace/16.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.3345497262
Short name T833
Test name
Test status
Simulation time 2039321469 ps
CPU time 1.93 seconds
Started Mar 24 12:42:46 PM PDT 24
Finished Mar 24 12:42:48 PM PDT 24
Peak memory 200720 kb
Host smart-4d17a4aa-9bd9-4abf-9a1c-397e8840c6c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345497262 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_intr_te
st.3345497262
Directory /workspace/16.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.1148510584
Short name T865
Test name
Test status
Simulation time 10145321750 ps
CPU time 6.2 seconds
Started Mar 24 12:42:52 PM PDT 24
Finished Mar 24 12:42:58 PM PDT 24
Peak memory 201432 kb
Host smart-2eb294c2-4913-4399-aaf5-e722942c5c6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148510584 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
6.sysrst_ctrl_same_csr_outstanding.1148510584
Directory /workspace/16.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.383473297
Short name T267
Test name
Test status
Simulation time 2330631082 ps
CPU time 3.2 seconds
Started Mar 24 12:42:50 PM PDT 24
Finished Mar 24 12:42:53 PM PDT 24
Peak memory 201428 kb
Host smart-073d3e07-6439-4c20-a1dd-aff708ba8534
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383473297 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_error
s.383473297
Directory /workspace/16.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.4264585747
Short name T268
Test name
Test status
Simulation time 22249785900 ps
CPU time 17.01 seconds
Started Mar 24 12:42:49 PM PDT 24
Finished Mar 24 12:43:06 PM PDT 24
Peak memory 201444 kb
Host smart-163b467a-0667-4517-b73a-e33166421ae9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264585747 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_tl_intg_err.4264585747
Directory /workspace/16.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.2416815408
Short name T799
Test name
Test status
Simulation time 2612464200 ps
CPU time 1.57 seconds
Started Mar 24 12:43:03 PM PDT 24
Finished Mar 24 12:43:04 PM PDT 24
Peak memory 201352 kb
Host smart-30c12ca1-d1f2-4198-b932-1438929dd598
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416815408 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_mem_rw_with_rand_reset.2416815408
Directory /workspace/17.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.1274774553
Short name T869
Test name
Test status
Simulation time 2061826736 ps
CPU time 2.01 seconds
Started Mar 24 12:43:02 PM PDT 24
Finished Mar 24 12:43:04 PM PDT 24
Peak memory 201224 kb
Host smart-fc715a20-cbc2-4917-8ad0-af78e0a47e6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274774553 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_
rw.1274774553
Directory /workspace/17.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.2606437394
Short name T895
Test name
Test status
Simulation time 2018972759 ps
CPU time 3.04 seconds
Started Mar 24 12:42:56 PM PDT 24
Finished Mar 24 12:42:59 PM PDT 24
Peak memory 200700 kb
Host smart-756af12f-cbd4-41f1-85f7-63a3488c932b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606437394 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_intr_te
st.2606437394
Directory /workspace/17.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.2283806488
Short name T325
Test name
Test status
Simulation time 7238851176 ps
CPU time 5.49 seconds
Started Mar 24 12:43:07 PM PDT 24
Finished Mar 24 12:43:12 PM PDT 24
Peak memory 201468 kb
Host smart-5643e28e-e709-4d23-a541-cefa97e17f6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283806488 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
7.sysrst_ctrl_same_csr_outstanding.2283806488
Directory /workspace/17.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.3034202331
Short name T354
Test name
Test status
Simulation time 22215029306 ps
CPU time 59.78 seconds
Started Mar 24 12:42:50 PM PDT 24
Finished Mar 24 12:43:50 PM PDT 24
Peak memory 201820 kb
Host smart-800aece2-1f13-46df-8ab8-e4b31c0d54cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034202331 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_tl_intg_err.3034202331
Directory /workspace/17.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2109177601
Short name T820
Test name
Test status
Simulation time 2198939424 ps
CPU time 2.45 seconds
Started Mar 24 12:42:40 PM PDT 24
Finished Mar 24 12:42:43 PM PDT 24
Peak memory 209880 kb
Host smart-182eb54e-f0ea-4b23-80ed-d93d4784134e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109177601 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2109177601
Directory /workspace/18.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.3889325295
Short name T321
Test name
Test status
Simulation time 2033511988 ps
CPU time 4.55 seconds
Started Mar 24 12:42:40 PM PDT 24
Finished Mar 24 12:42:45 PM PDT 24
Peak memory 201204 kb
Host smart-de137f28-33d0-4a2a-8519-ff9e8aa30050
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889325295 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_
rw.3889325295
Directory /workspace/18.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.2438484904
Short name T890
Test name
Test status
Simulation time 2050871422 ps
CPU time 1.38 seconds
Started Mar 24 12:42:46 PM PDT 24
Finished Mar 24 12:42:47 PM PDT 24
Peak memory 200704 kb
Host smart-9538bfc2-e6b9-4128-ba9c-981ff1aa266a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438484904 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_intr_te
st.2438484904
Directory /workspace/18.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.2206019190
Short name T850
Test name
Test status
Simulation time 5665318815 ps
CPU time 8.31 seconds
Started Mar 24 12:42:58 PM PDT 24
Finished Mar 24 12:43:06 PM PDT 24
Peak memory 201444 kb
Host smart-0d1d5636-61c6-4b2a-bc2d-676534edae90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206019190 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
8.sysrst_ctrl_same_csr_outstanding.2206019190
Directory /workspace/18.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.975176281
Short name T897
Test name
Test status
Simulation time 2149125503 ps
CPU time 5.99 seconds
Started Mar 24 12:43:07 PM PDT 24
Finished Mar 24 12:43:14 PM PDT 24
Peak memory 201372 kb
Host smart-34ef53d8-ad9b-4eac-8481-8c3973911bb0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975176281 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_error
s.975176281
Directory /workspace/18.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.3132416808
Short name T845
Test name
Test status
Simulation time 2085201069 ps
CPU time 6.65 seconds
Started Mar 24 12:42:51 PM PDT 24
Finished Mar 24 12:42:57 PM PDT 24
Peak memory 201300 kb
Host smart-05176344-30d0-4943-a528-bace36a87108
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132416808 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_mem_rw_with_rand_reset.3132416808
Directory /workspace/19.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.3219602181
Short name T327
Test name
Test status
Simulation time 2087231394 ps
CPU time 1.96 seconds
Started Mar 24 12:42:57 PM PDT 24
Finished Mar 24 12:42:59 PM PDT 24
Peak memory 201224 kb
Host smart-3bc61121-cd08-437c-8c7a-7a8c7db4b4c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219602181 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_
rw.3219602181
Directory /workspace/19.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.4188145518
Short name T788
Test name
Test status
Simulation time 2008890272 ps
CPU time 5.49 seconds
Started Mar 24 12:42:51 PM PDT 24
Finished Mar 24 12:42:56 PM PDT 24
Peak memory 200832 kb
Host smart-e3d5a1b2-2e70-4a88-b038-65f46a60db09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188145518 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_intr_te
st.4188145518
Directory /workspace/19.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.4247926299
Short name T900
Test name
Test status
Simulation time 9685077517 ps
CPU time 15.56 seconds
Started Mar 24 12:43:01 PM PDT 24
Finished Mar 24 12:43:21 PM PDT 24
Peak memory 201452 kb
Host smart-61064cc4-4ce6-4010-bad2-3beaaf87737d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247926299 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
9.sysrst_ctrl_same_csr_outstanding.4247926299
Directory /workspace/19.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.2151203944
Short name T868
Test name
Test status
Simulation time 2139678616 ps
CPU time 3.35 seconds
Started Mar 24 12:42:58 PM PDT 24
Finished Mar 24 12:43:01 PM PDT 24
Peak memory 201332 kb
Host smart-b9d7489a-8727-4147-a41e-460ff3c70537
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151203944 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_erro
rs.2151203944
Directory /workspace/19.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.949763415
Short name T888
Test name
Test status
Simulation time 22384042040 ps
CPU time 17.66 seconds
Started Mar 24 12:42:52 PM PDT 24
Finished Mar 24 12:43:09 PM PDT 24
Peak memory 201744 kb
Host smart-fd058b94-e472-4883-99d1-26d6efa58c94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949763415 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_c
trl_tl_intg_err.949763415
Directory /workspace/19.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.2790707331
Short name T323
Test name
Test status
Simulation time 2218477392 ps
CPU time 5.13 seconds
Started Mar 24 12:42:48 PM PDT 24
Finished Mar 24 12:42:53 PM PDT 24
Peak memory 201388 kb
Host smart-8afd86cf-3192-4b62-a0f9-f9c6c4b5b640
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790707331 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_aliasing.2790707331
Directory /workspace/2.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.1947055145
Short name T316
Test name
Test status
Simulation time 7728088920 ps
CPU time 12.73 seconds
Started Mar 24 12:42:32 PM PDT 24
Finished Mar 24 12:42:45 PM PDT 24
Peak memory 201412 kb
Host smart-42d30461-2c57-4171-844a-088b190a6612
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947055145 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_bit_bash.1947055145
Directory /workspace/2.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.4205671963
Short name T818
Test name
Test status
Simulation time 4040275509 ps
CPU time 5.57 seconds
Started Mar 24 12:42:33 PM PDT 24
Finished Mar 24 12:42:40 PM PDT 24
Peak memory 201180 kb
Host smart-b8d44fe6-6e68-4432-9e17-b93b5b1cae1b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205671963 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_hw_reset.4205671963
Directory /workspace/2.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.2696218066
Short name T910
Test name
Test status
Simulation time 2248904433 ps
CPU time 2.29 seconds
Started Mar 24 12:42:42 PM PDT 24
Finished Mar 24 12:42:45 PM PDT 24
Peak memory 201560 kb
Host smart-e23795ff-f58f-4bcb-865f-88bc8fd1fe74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696218066 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_mem_rw_with_rand_reset.2696218066
Directory /workspace/2.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.718939559
Short name T798
Test name
Test status
Simulation time 2112543268 ps
CPU time 1.13 seconds
Started Mar 24 12:42:38 PM PDT 24
Finished Mar 24 12:42:39 PM PDT 24
Peak memory 201152 kb
Host smart-875e03a8-dc39-4ad4-b1cf-cc9622c1b3be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718939559 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_rw
.718939559
Directory /workspace/2.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.1580456724
Short name T837
Test name
Test status
Simulation time 2046169758 ps
CPU time 1.35 seconds
Started Mar 24 12:42:41 PM PDT 24
Finished Mar 24 12:42:43 PM PDT 24
Peak memory 200656 kb
Host smart-46ff8f53-a305-4029-91a0-95ebbc657027
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580456724 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_intr_tes
t.1580456724
Directory /workspace/2.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.359055299
Short name T908
Test name
Test status
Simulation time 7726067220 ps
CPU time 19.91 seconds
Started Mar 24 12:42:51 PM PDT 24
Finished Mar 24 12:43:11 PM PDT 24
Peak memory 201564 kb
Host smart-b0737bec-0c20-49c5-af75-ef7ec5333e91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359055299 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
sysrst_ctrl_same_csr_outstanding.359055299
Directory /workspace/2.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.487296718
Short name T876
Test name
Test status
Simulation time 3373921592 ps
CPU time 3.38 seconds
Started Mar 24 12:42:47 PM PDT 24
Finished Mar 24 12:42:50 PM PDT 24
Peak memory 209724 kb
Host smart-62f78dc7-58ce-447d-89b7-26c1cd2c2ab9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487296718 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_errors
.487296718
Directory /workspace/2.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.2499671161
Short name T827
Test name
Test status
Simulation time 22231549641 ps
CPU time 51.6 seconds
Started Mar 24 12:42:46 PM PDT 24
Finished Mar 24 12:43:38 PM PDT 24
Peak memory 201500 kb
Host smart-1aeb5729-c253-462b-beec-478265756927
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499671161 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_tl_intg_err.2499671161
Directory /workspace/2.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.617586765
Short name T856
Test name
Test status
Simulation time 2023476463 ps
CPU time 3.3 seconds
Started Mar 24 12:42:41 PM PDT 24
Finished Mar 24 12:42:45 PM PDT 24
Peak memory 200748 kb
Host smart-1291a3bc-6fee-4e0d-afda-7b412a20a20b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617586765 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_intr_tes
t.617586765
Directory /workspace/20.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.2688534096
Short name T896
Test name
Test status
Simulation time 2008628469 ps
CPU time 5.95 seconds
Started Mar 24 12:42:47 PM PDT 24
Finished Mar 24 12:42:53 PM PDT 24
Peak memory 200748 kb
Host smart-6053f949-f6c5-4df2-b6cf-79c7e88723c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688534096 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_intr_te
st.2688534096
Directory /workspace/21.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.42711066
Short name T797
Test name
Test status
Simulation time 2026766419 ps
CPU time 1.91 seconds
Started Mar 24 12:42:44 PM PDT 24
Finished Mar 24 12:42:46 PM PDT 24
Peak memory 200644 kb
Host smart-953390a5-cbcb-493b-a1dc-08dcb719252f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42711066 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_intr_test
.42711066
Directory /workspace/22.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.2111064797
Short name T898
Test name
Test status
Simulation time 2017679305 ps
CPU time 3.26 seconds
Started Mar 24 12:42:49 PM PDT 24
Finished Mar 24 12:42:52 PM PDT 24
Peak memory 200704 kb
Host smart-fe5d370b-6241-4966-9aec-1dae97af18c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111064797 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_intr_te
st.2111064797
Directory /workspace/23.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.965763457
Short name T901
Test name
Test status
Simulation time 2009065169 ps
CPU time 5.59 seconds
Started Mar 24 12:42:55 PM PDT 24
Finished Mar 24 12:43:01 PM PDT 24
Peak memory 200572 kb
Host smart-25b61736-3f44-4e40-a5e6-bedeff69e425
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965763457 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_intr_tes
t.965763457
Directory /workspace/24.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.694529394
Short name T848
Test name
Test status
Simulation time 2033631383 ps
CPU time 1.93 seconds
Started Mar 24 12:42:56 PM PDT 24
Finished Mar 24 12:42:58 PM PDT 24
Peak memory 200668 kb
Host smart-eaa3855c-e218-4f58-8f53-72364eedebb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694529394 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_intr_tes
t.694529394
Directory /workspace/25.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.628230417
Short name T791
Test name
Test status
Simulation time 2015237861 ps
CPU time 5.77 seconds
Started Mar 24 12:42:38 PM PDT 24
Finished Mar 24 12:42:44 PM PDT 24
Peak memory 200664 kb
Host smart-0a42788e-9bf5-4bf2-911f-d9d2b15d1e6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628230417 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_intr_tes
t.628230417
Directory /workspace/26.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.2105978483
Short name T804
Test name
Test status
Simulation time 2052058915 ps
CPU time 1.86 seconds
Started Mar 24 12:43:01 PM PDT 24
Finished Mar 24 12:43:03 PM PDT 24
Peak memory 200692 kb
Host smart-20810720-7d1a-4b09-acc0-5dcab3921b7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105978483 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_intr_te
st.2105978483
Directory /workspace/27.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.1071953980
Short name T829
Test name
Test status
Simulation time 2102752216 ps
CPU time 1.12 seconds
Started Mar 24 12:43:01 PM PDT 24
Finished Mar 24 12:43:02 PM PDT 24
Peak memory 200716 kb
Host smart-2c2a4f2b-7226-45f6-afae-394f554a27e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071953980 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_intr_te
st.1071953980
Directory /workspace/28.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.2701880606
Short name T796
Test name
Test status
Simulation time 2028947648 ps
CPU time 1.89 seconds
Started Mar 24 12:42:44 PM PDT 24
Finished Mar 24 12:42:46 PM PDT 24
Peak memory 200640 kb
Host smart-d938cda4-267b-4ac4-bb25-01d85025864d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701880606 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_intr_te
st.2701880606
Directory /workspace/29.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.577189698
Short name T313
Test name
Test status
Simulation time 2201910597 ps
CPU time 7.9 seconds
Started Mar 24 12:42:48 PM PDT 24
Finished Mar 24 12:42:56 PM PDT 24
Peak memory 201344 kb
Host smart-2625bc1a-00c3-4e3e-8bfb-61bcb7d03352
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577189698 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_
csr_aliasing.577189698
Directory /workspace/3.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.3965689331
Short name T318
Test name
Test status
Simulation time 39008717397 ps
CPU time 91.5 seconds
Started Mar 24 12:42:46 PM PDT 24
Finished Mar 24 12:44:18 PM PDT 24
Peak memory 201496 kb
Host smart-a309bf05-e618-4d9f-bf76-97dd646bcd53
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965689331 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_bit_bash.3965689331
Directory /workspace/3.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.1601714583
Short name T889
Test name
Test status
Simulation time 4009987758 ps
CPU time 11.57 seconds
Started Mar 24 12:42:32 PM PDT 24
Finished Mar 24 12:42:44 PM PDT 24
Peak memory 201224 kb
Host smart-fe6f8cd5-b630-4562-99cc-e812ac105ccc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601714583 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_hw_reset.1601714583
Directory /workspace/3.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.2118101088
Short name T809
Test name
Test status
Simulation time 2160827469 ps
CPU time 2.48 seconds
Started Mar 24 12:42:39 PM PDT 24
Finished Mar 24 12:42:41 PM PDT 24
Peak memory 201508 kb
Host smart-8f13044f-fd16-46a1-aca4-13c4972b23da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118101088 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_mem_rw_with_rand_reset.2118101088
Directory /workspace/3.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.3373750605
Short name T834
Test name
Test status
Simulation time 2149289566 ps
CPU time 1.79 seconds
Started Mar 24 12:42:44 PM PDT 24
Finished Mar 24 12:42:46 PM PDT 24
Peak memory 201292 kb
Host smart-ff43ec1e-2196-427d-a395-60b14596e66a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373750605 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_r
w.3373750605
Directory /workspace/3.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.2407977104
Short name T802
Test name
Test status
Simulation time 2012965669 ps
CPU time 5.72 seconds
Started Mar 24 12:42:36 PM PDT 24
Finished Mar 24 12:42:42 PM PDT 24
Peak memory 200628 kb
Host smart-c30314fb-5386-4bd9-9e3d-f3c31b94c448
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407977104 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_intr_tes
t.2407977104
Directory /workspace/3.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.2314038753
Short name T329
Test name
Test status
Simulation time 5195767410 ps
CPU time 5.15 seconds
Started Mar 24 12:42:37 PM PDT 24
Finished Mar 24 12:42:42 PM PDT 24
Peak memory 201488 kb
Host smart-37e41069-df92-4cd3-82f0-80710e0301b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314038753 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.sysrst_ctrl_same_csr_outstanding.2314038753
Directory /workspace/3.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.663493045
Short name T894
Test name
Test status
Simulation time 2630140284 ps
CPU time 4.09 seconds
Started Mar 24 12:43:03 PM PDT 24
Finished Mar 24 12:43:07 PM PDT 24
Peak memory 209620 kb
Host smart-6b25be1b-68ac-4c1c-8823-2d9229bcab41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663493045 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_errors
.663493045
Directory /workspace/3.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.2831752360
Short name T811
Test name
Test status
Simulation time 42435715347 ps
CPU time 114.85 seconds
Started Mar 24 12:42:42 PM PDT 24
Finished Mar 24 12:44:37 PM PDT 24
Peak memory 201400 kb
Host smart-a7aa230c-3611-435b-9d06-9616c0aad7f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831752360 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_tl_intg_err.2831752360
Directory /workspace/3.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.1099240865
Short name T826
Test name
Test status
Simulation time 2047298540 ps
CPU time 1.98 seconds
Started Mar 24 12:43:02 PM PDT 24
Finished Mar 24 12:43:04 PM PDT 24
Peak memory 200620 kb
Host smart-34c9a449-57e2-42d7-9e8d-806688f4ffbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099240865 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_intr_te
st.1099240865
Directory /workspace/30.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.3657120747
Short name T800
Test name
Test status
Simulation time 2016311110 ps
CPU time 3.23 seconds
Started Mar 24 12:42:55 PM PDT 24
Finished Mar 24 12:42:58 PM PDT 24
Peak memory 200648 kb
Host smart-f736c563-0d05-48ee-ab0a-58740bdc3db2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657120747 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_intr_te
st.3657120747
Directory /workspace/31.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.1498420270
Short name T885
Test name
Test status
Simulation time 2023513599 ps
CPU time 1.87 seconds
Started Mar 24 12:42:50 PM PDT 24
Finished Mar 24 12:42:52 PM PDT 24
Peak memory 200620 kb
Host smart-7104eb52-e5fa-4c81-9877-0811b100d81f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498420270 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_intr_te
st.1498420270
Directory /workspace/32.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.874835131
Short name T805
Test name
Test status
Simulation time 2011686176 ps
CPU time 6.92 seconds
Started Mar 24 12:43:01 PM PDT 24
Finished Mar 24 12:43:08 PM PDT 24
Peak memory 200644 kb
Host smart-f63461fb-a1e5-4636-b57b-f5b77957c2a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874835131 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_intr_tes
t.874835131
Directory /workspace/33.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.1174871941
Short name T857
Test name
Test status
Simulation time 2012159438 ps
CPU time 6 seconds
Started Mar 24 12:42:48 PM PDT 24
Finished Mar 24 12:42:54 PM PDT 24
Peak memory 200628 kb
Host smart-dbee5841-6e3c-4890-9744-2aeb972a882c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174871941 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_intr_te
st.1174871941
Directory /workspace/34.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.430745719
Short name T831
Test name
Test status
Simulation time 2052915470 ps
CPU time 1.85 seconds
Started Mar 24 12:42:58 PM PDT 24
Finished Mar 24 12:43:00 PM PDT 24
Peak memory 200612 kb
Host smart-6654137b-180e-4e47-9126-0d9ebe182c6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430745719 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_intr_tes
t.430745719
Directory /workspace/35.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.2504970992
Short name T886
Test name
Test status
Simulation time 2038776809 ps
CPU time 2.02 seconds
Started Mar 24 12:42:57 PM PDT 24
Finished Mar 24 12:42:59 PM PDT 24
Peak memory 200604 kb
Host smart-19e1a2d8-0f33-4a96-a60c-108f5edebdc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504970992 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_intr_te
st.2504970992
Directory /workspace/36.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.1706046880
Short name T862
Test name
Test status
Simulation time 2009330754 ps
CPU time 5.76 seconds
Started Mar 24 12:42:48 PM PDT 24
Finished Mar 24 12:42:54 PM PDT 24
Peak memory 200692 kb
Host smart-848c757e-1160-4623-bd5f-68db03370d9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706046880 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_intr_te
st.1706046880
Directory /workspace/37.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.3096862948
Short name T855
Test name
Test status
Simulation time 2017068719 ps
CPU time 3.43 seconds
Started Mar 24 12:42:58 PM PDT 24
Finished Mar 24 12:43:03 PM PDT 24
Peak memory 200732 kb
Host smart-ac2575ab-6535-4e85-b54f-1391a23baf4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096862948 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_intr_te
st.3096862948
Directory /workspace/38.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.3717480100
Short name T786
Test name
Test status
Simulation time 2016530190 ps
CPU time 3.61 seconds
Started Mar 24 12:42:51 PM PDT 24
Finished Mar 24 12:42:55 PM PDT 24
Peak memory 200740 kb
Host smart-bedff422-0ccf-4741-943f-6d9d7495a8f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717480100 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_intr_te
st.3717480100
Directory /workspace/39.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.2616164396
Short name T807
Test name
Test status
Simulation time 2704765241 ps
CPU time 5.85 seconds
Started Mar 24 12:42:35 PM PDT 24
Finished Mar 24 12:42:41 PM PDT 24
Peak memory 201356 kb
Host smart-5afb344d-1a78-4ffa-b9dd-3fc0c115a2e2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616164396 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_aliasing.2616164396
Directory /workspace/4.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.2591287826
Short name T317
Test name
Test status
Simulation time 37172599608 ps
CPU time 164.89 seconds
Started Mar 24 12:43:02 PM PDT 24
Finished Mar 24 12:45:47 PM PDT 24
Peak memory 201380 kb
Host smart-8f54645a-dfe4-46b0-895c-d93ae018646f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591287826 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_bit_bash.2591287826
Directory /workspace/4.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.492266635
Short name T795
Test name
Test status
Simulation time 6114960347 ps
CPU time 3.73 seconds
Started Mar 24 12:42:43 PM PDT 24
Finished Mar 24 12:42:52 PM PDT 24
Peak memory 201256 kb
Host smart-db144ef6-1a02-4b5a-b6f8-35d1f2b5e133
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492266635 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_
csr_hw_reset.492266635
Directory /workspace/4.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.1288967340
Short name T813
Test name
Test status
Simulation time 2218274393 ps
CPU time 2.5 seconds
Started Mar 24 12:42:39 PM PDT 24
Finished Mar 24 12:42:41 PM PDT 24
Peak memory 201204 kb
Host smart-e1cfb375-c4d4-4b6a-bd33-f78ac497874d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288967340 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_mem_rw_with_rand_reset.1288967340
Directory /workspace/4.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.3791192781
Short name T854
Test name
Test status
Simulation time 2051781940 ps
CPU time 2.12 seconds
Started Mar 24 12:42:41 PM PDT 24
Finished Mar 24 12:42:49 PM PDT 24
Peak memory 201124 kb
Host smart-5ecc2f5a-70a9-40a3-afdd-3cd914a32d63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791192781 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_r
w.3791192781
Directory /workspace/4.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.3393258700
Short name T789
Test name
Test status
Simulation time 2028128949 ps
CPU time 1.94 seconds
Started Mar 24 12:42:55 PM PDT 24
Finished Mar 24 12:42:57 PM PDT 24
Peak memory 200636 kb
Host smart-c0fa84bd-6af2-41de-8347-6847c918cb4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393258700 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_intr_tes
t.3393258700
Directory /workspace/4.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.76926355
Short name T808
Test name
Test status
Simulation time 9252883898 ps
CPU time 23.95 seconds
Started Mar 24 12:42:40 PM PDT 24
Finished Mar 24 12:43:04 PM PDT 24
Peak memory 201496 kb
Host smart-4dd82d9c-488d-4d1c-903e-86ba669caeaa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76926355 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=
sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
ysrst_ctrl_same_csr_outstanding.76926355
Directory /workspace/4.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.4231091606
Short name T883
Test name
Test status
Simulation time 2127934671 ps
CPU time 7.59 seconds
Started Mar 24 12:42:47 PM PDT 24
Finished Mar 24 12:42:54 PM PDT 24
Peak memory 201384 kb
Host smart-b814377d-f8c5-4cc7-935c-84899cc78b6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231091606 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_error
s.4231091606
Directory /workspace/4.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.2549871910
Short name T870
Test name
Test status
Simulation time 42550129393 ps
CPU time 58.05 seconds
Started Mar 24 12:42:44 PM PDT 24
Finished Mar 24 12:43:43 PM PDT 24
Peak memory 201420 kb
Host smart-e558c555-4d2a-4fc2-9b8a-3f27d65d5e26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549871910 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_tl_intg_err.2549871910
Directory /workspace/4.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.563846810
Short name T824
Test name
Test status
Simulation time 2014223943 ps
CPU time 6 seconds
Started Mar 24 12:43:16 PM PDT 24
Finished Mar 24 12:43:22 PM PDT 24
Peak memory 200620 kb
Host smart-1a4bd682-20c4-47a3-a083-7f03011c539d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563846810 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_intr_tes
t.563846810
Directory /workspace/40.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.2783398439
Short name T859
Test name
Test status
Simulation time 2014724195 ps
CPU time 4.96 seconds
Started Mar 24 12:42:51 PM PDT 24
Finished Mar 24 12:42:57 PM PDT 24
Peak memory 200912 kb
Host smart-0393c925-ae97-461e-bbce-ec88584a0e35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783398439 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_intr_te
st.2783398439
Directory /workspace/41.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.1060578730
Short name T879
Test name
Test status
Simulation time 2017647222 ps
CPU time 3.29 seconds
Started Mar 24 12:43:00 PM PDT 24
Finished Mar 24 12:43:03 PM PDT 24
Peak memory 200636 kb
Host smart-1bb8b5c2-4535-49eb-a68d-6bae9948f96d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060578730 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_intr_te
st.1060578730
Directory /workspace/42.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.3916116727
Short name T787
Test name
Test status
Simulation time 2010442394 ps
CPU time 5.69 seconds
Started Mar 24 12:43:06 PM PDT 24
Finished Mar 24 12:43:11 PM PDT 24
Peak memory 200728 kb
Host smart-2411d4cc-eaed-44e4-ac7d-08764c930498
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916116727 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_intr_te
st.3916116727
Directory /workspace/43.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.4292776621
Short name T839
Test name
Test status
Simulation time 2013246680 ps
CPU time 5.76 seconds
Started Mar 24 12:43:00 PM PDT 24
Finished Mar 24 12:43:06 PM PDT 24
Peak memory 200744 kb
Host smart-3fcf0a75-4087-4802-a124-b4aaa5700d2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292776621 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_intr_te
st.4292776621
Directory /workspace/44.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.2218539048
Short name T823
Test name
Test status
Simulation time 2040800220 ps
CPU time 1.97 seconds
Started Mar 24 12:43:01 PM PDT 24
Finished Mar 24 12:43:03 PM PDT 24
Peak memory 201044 kb
Host smart-396e28f9-8f45-45ad-b79e-b2463943e90f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218539048 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_intr_te
st.2218539048
Directory /workspace/45.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.2859775741
Short name T794
Test name
Test status
Simulation time 2042225537 ps
CPU time 1.63 seconds
Started Mar 24 12:43:19 PM PDT 24
Finished Mar 24 12:43:22 PM PDT 24
Peak memory 200640 kb
Host smart-b8bb0400-8313-4cef-93a0-0f4188b3bdab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859775741 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_intr_te
st.2859775741
Directory /workspace/46.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.568507217
Short name T909
Test name
Test status
Simulation time 2025167483 ps
CPU time 2.07 seconds
Started Mar 24 12:43:06 PM PDT 24
Finished Mar 24 12:43:08 PM PDT 24
Peak memory 200644 kb
Host smart-036fa589-4075-4016-8922-571540702006
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568507217 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_intr_tes
t.568507217
Directory /workspace/47.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.3550021853
Short name T785
Test name
Test status
Simulation time 2015037650 ps
CPU time 6.3 seconds
Started Mar 24 12:43:01 PM PDT 24
Finished Mar 24 12:43:07 PM PDT 24
Peak memory 200752 kb
Host smart-f73cdc4f-e93d-4eb4-99c9-7a27bab835af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550021853 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_intr_te
st.3550021853
Directory /workspace/48.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.2347006773
Short name T793
Test name
Test status
Simulation time 2014609516 ps
CPU time 4.62 seconds
Started Mar 24 12:43:04 PM PDT 24
Finished Mar 24 12:43:09 PM PDT 24
Peak memory 200744 kb
Host smart-786d411e-711c-4957-80c5-a7c22c5044eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347006773 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_intr_te
st.2347006773
Directory /workspace/49.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.1553412716
Short name T812
Test name
Test status
Simulation time 2140359779 ps
CPU time 2.33 seconds
Started Mar 24 12:42:47 PM PDT 24
Finished Mar 24 12:42:49 PM PDT 24
Peak memory 201276 kb
Host smart-85c2dbce-943a-4921-8708-a16191172ecf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553412716 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_mem_rw_with_rand_reset.1553412716
Directory /workspace/5.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.238786424
Short name T882
Test name
Test status
Simulation time 2018122288 ps
CPU time 3.43 seconds
Started Mar 24 12:42:50 PM PDT 24
Finished Mar 24 12:42:53 PM PDT 24
Peak memory 200632 kb
Host smart-f1f53548-a96f-4709-90b6-ce2c9993c43a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238786424 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_intr_test
.238786424
Directory /workspace/5.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.1026084999
Short name T18
Test name
Test status
Simulation time 5221012671 ps
CPU time 10.66 seconds
Started Mar 24 12:42:43 PM PDT 24
Finished Mar 24 12:42:53 PM PDT 24
Peak memory 201452 kb
Host smart-c388867a-94f0-47e9-aade-aac1aaf7e21c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026084999 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5
.sysrst_ctrl_same_csr_outstanding.1026084999
Directory /workspace/5.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.278985546
Short name T817
Test name
Test status
Simulation time 2157759312 ps
CPU time 4.24 seconds
Started Mar 24 12:42:36 PM PDT 24
Finished Mar 24 12:42:40 PM PDT 24
Peak memory 201476 kb
Host smart-22249661-fa64-4174-a0c7-0e98a82464d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278985546 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_errors
.278985546
Directory /workspace/5.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.1563855796
Short name T264
Test name
Test status
Simulation time 22225813023 ps
CPU time 60.56 seconds
Started Mar 24 12:42:43 PM PDT 24
Finished Mar 24 12:43:44 PM PDT 24
Peak memory 201484 kb
Host smart-829e879a-0ebf-4150-861a-263ced8fe21d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563855796 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_tl_intg_err.1563855796
Directory /workspace/5.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.1399184527
Short name T861
Test name
Test status
Simulation time 2122592258 ps
CPU time 1.57 seconds
Started Mar 24 12:42:46 PM PDT 24
Finished Mar 24 12:42:47 PM PDT 24
Peak memory 201180 kb
Host smart-6924d985-001e-4fea-bbd3-d64e01a17b70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399184527 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_mem_rw_with_rand_reset.1399184527
Directory /workspace/6.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.4081416683
Short name T324
Test name
Test status
Simulation time 2082224704 ps
CPU time 3.32 seconds
Started Mar 24 12:42:53 PM PDT 24
Finished Mar 24 12:42:56 PM PDT 24
Peak memory 201208 kb
Host smart-3f75ce3a-7eee-4cee-88cf-af70961bb78f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081416683 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_r
w.4081416683
Directory /workspace/6.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.2704083356
Short name T792
Test name
Test status
Simulation time 2019037935 ps
CPU time 3.45 seconds
Started Mar 24 12:42:40 PM PDT 24
Finished Mar 24 12:42:44 PM PDT 24
Peak memory 200768 kb
Host smart-75caa899-1430-41ec-a86a-b6b802edc0b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704083356 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_intr_tes
t.2704083356
Directory /workspace/6.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.3226480212
Short name T801
Test name
Test status
Simulation time 7742677382 ps
CPU time 21.1 seconds
Started Mar 24 12:42:41 PM PDT 24
Finished Mar 24 12:43:02 PM PDT 24
Peak memory 201476 kb
Host smart-17ddf352-c141-4236-8306-a6eed1ccf39a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226480212 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6
.sysrst_ctrl_same_csr_outstanding.3226480212
Directory /workspace/6.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.1072994913
Short name T836
Test name
Test status
Simulation time 2600972186 ps
CPU time 3.31 seconds
Started Mar 24 12:43:00 PM PDT 24
Finished Mar 24 12:43:04 PM PDT 24
Peak memory 201432 kb
Host smart-bc9e9b3d-3a7c-47b7-9f8f-466579e083d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072994913 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_error
s.1072994913
Directory /workspace/6.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.3630227459
Short name T891
Test name
Test status
Simulation time 22266128856 ps
CPU time 29.14 seconds
Started Mar 24 12:42:47 PM PDT 24
Finished Mar 24 12:43:17 PM PDT 24
Peak memory 201492 kb
Host smart-1cc8c691-7c83-4f0b-963b-3c7c28f5a88d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630227459 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_tl_intg_err.3630227459
Directory /workspace/6.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.277025765
Short name T903
Test name
Test status
Simulation time 2107248206 ps
CPU time 2.26 seconds
Started Mar 24 12:42:52 PM PDT 24
Finished Mar 24 12:42:55 PM PDT 24
Peak memory 201188 kb
Host smart-dfe3a5c4-6deb-4ab4-9a06-e67ca54c2be4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277025765 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_mem_rw_with_rand_reset.277025765
Directory /workspace/7.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.361535963
Short name T828
Test name
Test status
Simulation time 2104945332 ps
CPU time 2.13 seconds
Started Mar 24 12:42:42 PM PDT 24
Finished Mar 24 12:42:45 PM PDT 24
Peak memory 201344 kb
Host smart-9546a009-c575-4d36-bb64-ff89299d487e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361535963 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_rw
.361535963
Directory /workspace/7.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.1148457431
Short name T814
Test name
Test status
Simulation time 2009107878 ps
CPU time 5.45 seconds
Started Mar 24 12:42:51 PM PDT 24
Finished Mar 24 12:42:57 PM PDT 24
Peak memory 200708 kb
Host smart-c2153fe4-3504-44a0-9d8f-45cbf5d20bc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148457431 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_intr_tes
t.1148457431
Directory /workspace/7.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.2083212856
Short name T874
Test name
Test status
Simulation time 9839671320 ps
CPU time 27.87 seconds
Started Mar 24 12:42:44 PM PDT 24
Finished Mar 24 12:43:12 PM PDT 24
Peak memory 201460 kb
Host smart-59bb45ee-26e4-46f0-a89e-fd9297ebb9da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083212856 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7
.sysrst_ctrl_same_csr_outstanding.2083212856
Directory /workspace/7.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.740673726
Short name T877
Test name
Test status
Simulation time 2048053233 ps
CPU time 7.74 seconds
Started Mar 24 12:42:46 PM PDT 24
Finished Mar 24 12:42:54 PM PDT 24
Peak memory 209544 kb
Host smart-c6b87c91-fd6b-4ecb-8fa5-d7d763978963
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740673726 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_errors
.740673726
Directory /workspace/7.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.4260850469
Short name T263
Test name
Test status
Simulation time 22409368689 ps
CPU time 18.31 seconds
Started Mar 24 12:42:52 PM PDT 24
Finished Mar 24 12:43:11 PM PDT 24
Peak memory 201500 kb
Host smart-9bef824a-063f-4840-87ce-b7a20a4cf48d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260850469 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_tl_intg_err.4260850469
Directory /workspace/7.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.3162825844
Short name T838
Test name
Test status
Simulation time 2084766561 ps
CPU time 2.26 seconds
Started Mar 24 12:42:59 PM PDT 24
Finished Mar 24 12:43:01 PM PDT 24
Peak memory 201244 kb
Host smart-b8461c08-3f07-49b0-bfc1-dd47cadc1c18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162825844 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_mem_rw_with_rand_reset.3162825844
Directory /workspace/8.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.3197673641
Short name T840
Test name
Test status
Simulation time 2107255846 ps
CPU time 1.48 seconds
Started Mar 24 12:42:48 PM PDT 24
Finished Mar 24 12:42:50 PM PDT 24
Peak memory 201236 kb
Host smart-5889bccc-1945-41df-8e1b-0a6f82597524
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197673641 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_r
w.3197673641
Directory /workspace/8.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.4006205149
Short name T806
Test name
Test status
Simulation time 2020626635 ps
CPU time 3.3 seconds
Started Mar 24 12:42:44 PM PDT 24
Finished Mar 24 12:42:48 PM PDT 24
Peak memory 200760 kb
Host smart-d88fc618-434f-4fe9-ac3c-624b9334a265
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006205149 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_intr_tes
t.4006205149
Directory /workspace/8.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.1766871125
Short name T846
Test name
Test status
Simulation time 4579318102 ps
CPU time 6.65 seconds
Started Mar 24 12:42:56 PM PDT 24
Finished Mar 24 12:43:03 PM PDT 24
Peak memory 201180 kb
Host smart-66eefd0e-a02b-4239-8776-5c40f1b86370
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766871125 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8
.sysrst_ctrl_same_csr_outstanding.1766871125
Directory /workspace/8.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.1865265746
Short name T851
Test name
Test status
Simulation time 2111798921 ps
CPU time 6.98 seconds
Started Mar 24 12:42:47 PM PDT 24
Finished Mar 24 12:42:54 PM PDT 24
Peak memory 201352 kb
Host smart-32e85617-9e72-4eca-b3ef-34414c869504
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865265746 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_error
s.1865265746
Directory /workspace/8.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.290143511
Short name T830
Test name
Test status
Simulation time 22232624201 ps
CPU time 63.72 seconds
Started Mar 24 12:42:42 PM PDT 24
Finished Mar 24 12:43:45 PM PDT 24
Peak memory 201456 kb
Host smart-b5d3fd82-1ccf-428b-85a5-3db6776dda1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290143511 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ct
rl_tl_intg_err.290143511
Directory /workspace/8.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.2175574014
Short name T878
Test name
Test status
Simulation time 2061478641 ps
CPU time 3.44 seconds
Started Mar 24 12:42:33 PM PDT 24
Finished Mar 24 12:42:37 PM PDT 24
Peak memory 201576 kb
Host smart-342560e4-6652-4738-bad6-338dae490161
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175574014 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_mem_rw_with_rand_reset.2175574014
Directory /workspace/9.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.266913446
Short name T844
Test name
Test status
Simulation time 2040102637 ps
CPU time 6.26 seconds
Started Mar 24 12:42:47 PM PDT 24
Finished Mar 24 12:42:54 PM PDT 24
Peak memory 201140 kb
Host smart-2464a1ed-5b4d-453c-a611-be4359f2dd10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266913446 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_rw
.266913446
Directory /workspace/9.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.1141168134
Short name T810
Test name
Test status
Simulation time 2035556924 ps
CPU time 1.92 seconds
Started Mar 24 12:42:48 PM PDT 24
Finished Mar 24 12:42:50 PM PDT 24
Peak memory 200696 kb
Host smart-cef75623-128f-4dd2-84d1-8339c07b011b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141168134 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_intr_tes
t.1141168134
Directory /workspace/9.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.1803153035
Short name T20
Test name
Test status
Simulation time 4491046889 ps
CPU time 17.47 seconds
Started Mar 24 12:42:56 PM PDT 24
Finished Mar 24 12:43:14 PM PDT 24
Peak memory 201428 kb
Host smart-659daab3-dcee-48e3-a732-f2efe524e08a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803153035 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9
.sysrst_ctrl_same_csr_outstanding.1803153035
Directory /workspace/9.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.1579862445
Short name T269
Test name
Test status
Simulation time 2187201223 ps
CPU time 8.54 seconds
Started Mar 24 12:42:42 PM PDT 24
Finished Mar 24 12:42:51 PM PDT 24
Peak memory 209588 kb
Host smart-537176c1-088f-4529-ae20-fe3efa73b85e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579862445 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_error
s.1579862445
Directory /workspace/9.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.2122727402
Short name T355
Test name
Test status
Simulation time 42362088277 ps
CPU time 113.01 seconds
Started Mar 24 12:42:54 PM PDT 24
Finished Mar 24 12:44:47 PM PDT 24
Peak memory 201432 kb
Host smart-66db1889-7a8c-4dab-900c-c84f980b95a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122727402 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_tl_intg_err.2122727402
Directory /workspace/9.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_alert_test.113918637
Short name T553
Test name
Test status
Simulation time 2058126507 ps
CPU time 1.81 seconds
Started Mar 24 01:14:48 PM PDT 24
Finished Mar 24 01:14:51 PM PDT 24
Peak memory 202072 kb
Host smart-4d701fb7-e058-4caa-8378-e9792f04d07c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113918637 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_alert_test
.113918637
Directory /workspace/0.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.2388751759
Short name T609
Test name
Test status
Simulation time 3383578175 ps
CPU time 1.91 seconds
Started Mar 24 01:14:48 PM PDT 24
Finished Mar 24 01:14:50 PM PDT 24
Peak memory 202132 kb
Host smart-ad5f7b3d-ba32-468f-b851-1e9b08f4a410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388751759 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_auto_blk_key_output.2388751759
Directory /workspace/0.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect.3111075348
Short name T338
Test name
Test status
Simulation time 89457410911 ps
CPU time 34.91 seconds
Started Mar 24 01:14:51 PM PDT 24
Finished Mar 24 01:15:26 PM PDT 24
Peak memory 202520 kb
Host smart-5c81d842-b7aa-4bd8-8505-54543a4e4972
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111075348 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ct
rl_combo_detect.3111075348
Directory /workspace/0.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.3849154929
Short name T212
Test name
Test status
Simulation time 2425942098 ps
CPU time 3.5 seconds
Started Mar 24 01:14:47 PM PDT 24
Finished Mar 24 01:14:51 PM PDT 24
Peak memory 202032 kb
Host smart-e288084f-0ccb-429c-807c-b16e7651f32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849154929 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst.3849154929
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2932870874
Short name T217
Test name
Test status
Simulation time 2364175865 ps
CPU time 1.56 seconds
Started Mar 24 01:14:44 PM PDT 24
Finished Mar 24 01:14:46 PM PDT 24
Peak memory 202072 kb
Host smart-22e12530-2a96-4acd-8163-a1e767545154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932870874 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.2932870874
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.1130334368
Short name T366
Test name
Test status
Simulation time 55381952901 ps
CPU time 29.88 seconds
Started Mar 24 01:14:45 PM PDT 24
Finished Mar 24 01:15:15 PM PDT 24
Peak memory 202252 kb
Host smart-bb063f91-f4d6-4539-a909-b281b46bb02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130334368 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_wi
th_pre_cond.1130334368
Directory /workspace/0.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.2163048300
Short name T281
Test name
Test status
Simulation time 3914136921 ps
CPU time 7.32 seconds
Started Mar 24 01:14:44 PM PDT 24
Finished Mar 24 01:14:52 PM PDT 24
Peak memory 202048 kb
Host smart-506e3672-6b91-4037-ad0d-f1115b1cfb07
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163048300 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_ec_pwr_on_rst.2163048300
Directory /workspace/0.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_edge_detect.2112999188
Short name T629
Test name
Test status
Simulation time 3858239644 ps
CPU time 1.12 seconds
Started Mar 24 01:14:49 PM PDT 24
Finished Mar 24 01:14:51 PM PDT 24
Peak memory 201968 kb
Host smart-7523976a-dff8-4ed3-9077-70054836ae3f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112999188 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctr
l_edge_detect.2112999188
Directory /workspace/0.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.2631012690
Short name T534
Test name
Test status
Simulation time 2611650273 ps
CPU time 6.96 seconds
Started Mar 24 01:14:49 PM PDT 24
Finished Mar 24 01:14:57 PM PDT 24
Peak memory 202040 kb
Host smart-f74a146e-59db-41f6-a12c-e5c26ec9142f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631012690 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_flash_wr_prot_out.2631012690
Directory /workspace/0.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.2600026615
Short name T64
Test name
Test status
Simulation time 2478814978 ps
CPU time 1.61 seconds
Started Mar 24 01:14:51 PM PDT 24
Finished Mar 24 01:14:53 PM PDT 24
Peak memory 202048 kb
Host smart-1a282a08-68f0-4c50-85fe-fdd8038940ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600026615 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_in_out_inverted.2600026615
Directory /workspace/0.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_access_test.774099357
Short name T766
Test name
Test status
Simulation time 2075845328 ps
CPU time 2.82 seconds
Started Mar 24 01:14:53 PM PDT 24
Finished Mar 24 01:14:57 PM PDT 24
Peak memory 201948 kb
Host smart-a246e360-7bdf-4146-8e5c-1a94d584f5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774099357 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_access_test.774099357
Directory /workspace/0.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_override_test.1507457183
Short name T295
Test name
Test status
Simulation time 2525288729 ps
CPU time 3.28 seconds
Started Mar 24 01:14:47 PM PDT 24
Finished Mar 24 01:14:50 PM PDT 24
Peak memory 202040 kb
Host smart-060a11f7-fadc-4e7e-8320-268f03c98689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507457183 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_override_test.1507457183
Directory /workspace/0.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_smoke.3980839471
Short name T556
Test name
Test status
Simulation time 2146142892 ps
CPU time 1.65 seconds
Started Mar 24 01:14:48 PM PDT 24
Finished Mar 24 01:14:50 PM PDT 24
Peak memory 201868 kb
Host smart-7a78b6ba-deae-42ba-ae79-060612503a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980839471 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_smoke.3980839471
Directory /workspace/0.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all.2586723091
Short name T198
Test name
Test status
Simulation time 115281724474 ps
CPU time 72.51 seconds
Started Mar 24 01:14:51 PM PDT 24
Finished Mar 24 01:16:04 PM PDT 24
Peak memory 202100 kb
Host smart-a6929efc-942a-458f-a8d8-65167b505bf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586723091 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_st
ress_all.2586723091
Directory /workspace/0.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.2548259123
Short name T178
Test name
Test status
Simulation time 36681592100 ps
CPU time 16.76 seconds
Started Mar 24 01:14:41 PM PDT 24
Finished Mar 24 01:14:58 PM PDT 24
Peak memory 218800 kb
Host smart-93fe34e9-a50b-4a4a-8849-8179258c3595
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548259123 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_stress_all_with_rand_reset.2548259123
Directory /workspace/0.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_alert_test.899691132
Short name T130
Test name
Test status
Simulation time 2068938301 ps
CPU time 1.18 seconds
Started Mar 24 01:14:50 PM PDT 24
Finished Mar 24 01:14:52 PM PDT 24
Peak memory 202084 kb
Host smart-7bc82109-eeb0-4fd1-8b08-2d63e154fe8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899691132 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_alert_test
.899691132
Directory /workspace/1.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_auto_blk_key_output.250538753
Short name T635
Test name
Test status
Simulation time 100571213869 ps
CPU time 71.15 seconds
Started Mar 24 01:14:43 PM PDT 24
Finished Mar 24 01:15:55 PM PDT 24
Peak memory 202036 kb
Host smart-b9321c43-db19-4b7b-b18a-1f44604c6918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250538753 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_auto_blk_key_output.250538753
Directory /workspace/1.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect.460953324
Short name T644
Test name
Test status
Simulation time 78874959306 ps
CPU time 205.88 seconds
Started Mar 24 01:14:49 PM PDT 24
Finished Mar 24 01:18:15 PM PDT 24
Peak memory 202252 kb
Host smart-20c5aa86-91f8-440e-a1a4-2700115a1217
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460953324 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctr
l_combo_detect.460953324
Directory /workspace/1.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.384979634
Short name T679
Test name
Test status
Simulation time 2446943190 ps
CPU time 2.21 seconds
Started Mar 24 01:14:42 PM PDT 24
Finished Mar 24 01:14:44 PM PDT 24
Peak memory 202300 kb
Host smart-160fed58-e476-49e5-8c0d-14889afeea84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384979634 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst.384979634
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2258537201
Short name T631
Test name
Test status
Simulation time 2537824862 ps
CPU time 7.07 seconds
Started Mar 24 01:14:48 PM PDT 24
Finished Mar 24 01:14:55 PM PDT 24
Peak memory 202076 kb
Host smart-8003cf6c-8359-4ae7-9ca4-2788a60a7638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258537201 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.2258537201
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.2630527570
Short name T547
Test name
Test status
Simulation time 26097114051 ps
CPU time 18.03 seconds
Started Mar 24 01:14:50 PM PDT 24
Finished Mar 24 01:15:09 PM PDT 24
Peak memory 202292 kb
Host smart-edf80be6-5085-4dd9-9f77-05d3bc5c6d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630527570 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_wi
th_pre_cond.2630527570
Directory /workspace/1.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.3667378160
Short name T653
Test name
Test status
Simulation time 2965366808 ps
CPU time 2.54 seconds
Started Mar 24 01:14:50 PM PDT 24
Finished Mar 24 01:14:53 PM PDT 24
Peak memory 202048 kb
Host smart-717a9aa4-0385-487a-b60d-8a02d8a74ea3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667378160 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_ec_pwr_on_rst.3667378160
Directory /workspace/1.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_edge_detect.1910261304
Short name T148
Test name
Test status
Simulation time 4425239762 ps
CPU time 9.59 seconds
Started Mar 24 01:14:47 PM PDT 24
Finished Mar 24 01:14:57 PM PDT 24
Peak memory 202048 kb
Host smart-b12a887f-1aa6-4209-95e5-36e9fae9eb76
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910261304 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctr
l_edge_detect.1910261304
Directory /workspace/1.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.3119633202
Short name T664
Test name
Test status
Simulation time 2614515059 ps
CPU time 7.54 seconds
Started Mar 24 01:14:48 PM PDT 24
Finished Mar 24 01:14:55 PM PDT 24
Peak memory 202060 kb
Host smart-dcd934a2-1e36-4e64-ba29-2ddefd5366bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119633202 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_flash_wr_prot_out.3119633202
Directory /workspace/1.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.3130768550
Short name T218
Test name
Test status
Simulation time 2510015386 ps
CPU time 1.09 seconds
Started Mar 24 01:14:53 PM PDT 24
Finished Mar 24 01:14:54 PM PDT 24
Peak memory 202052 kb
Host smart-2e6ec8b4-99c2-4e7e-9f06-c7cb17a003df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130768550 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_in_out_inverted.3130768550
Directory /workspace/1.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_access_test.2406633790
Short name T53
Test name
Test status
Simulation time 2123680161 ps
CPU time 1.35 seconds
Started Mar 24 01:14:49 PM PDT 24
Finished Mar 24 01:14:51 PM PDT 24
Peak memory 201880 kb
Host smart-07a7b88e-1d51-45ef-bd78-dd3978488bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406633790 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_access_test.2406633790
Directory /workspace/1.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_override_test.1873856733
Short name T678
Test name
Test status
Simulation time 2534425037 ps
CPU time 1.95 seconds
Started Mar 24 01:14:49 PM PDT 24
Finished Mar 24 01:14:51 PM PDT 24
Peak memory 201952 kb
Host smart-04e41bfa-b153-424a-92da-f855c0c0b50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873856733 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_override_test.1873856733
Directory /workspace/1.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_sec_cm.2934120395
Short name T271
Test name
Test status
Simulation time 22015353325 ps
CPU time 53.6 seconds
Started Mar 24 01:14:50 PM PDT 24
Finished Mar 24 01:15:44 PM PDT 24
Peak memory 221748 kb
Host smart-8cb38803-867d-43cb-8d16-ab33d3142bcf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934120395 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_sec_cm.2934120395
Directory /workspace/1.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_smoke.4087958039
Short name T292
Test name
Test status
Simulation time 2111527093 ps
CPU time 5.9 seconds
Started Mar 24 01:14:50 PM PDT 24
Finished Mar 24 01:14:56 PM PDT 24
Peak memory 201956 kb
Host smart-4face583-7a29-4702-8073-944912a62002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087958039 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_smoke.4087958039
Directory /workspace/1.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.725208325
Short name T59
Test name
Test status
Simulation time 9110277738 ps
CPU time 1.45 seconds
Started Mar 24 01:14:47 PM PDT 24
Finished Mar 24 01:14:49 PM PDT 24
Peak memory 202076 kb
Host smart-626619f0-a881-419f-8c01-db71fac5d5c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725208325 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ct
rl_ultra_low_pwr.725208325
Directory /workspace/1.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_alert_test.3563506405
Short name T518
Test name
Test status
Simulation time 2029198235 ps
CPU time 1.93 seconds
Started Mar 24 01:15:11 PM PDT 24
Finished Mar 24 01:15:13 PM PDT 24
Peak memory 202040 kb
Host smart-9363cb0e-3081-4d8e-80e9-dbde96bb6784
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563506405 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_alert_te
st.3563506405
Directory /workspace/10.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.3188677976
Short name T568
Test name
Test status
Simulation time 4158908085 ps
CPU time 1.14 seconds
Started Mar 24 01:15:25 PM PDT 24
Finished Mar 24 01:15:26 PM PDT 24
Peak memory 202108 kb
Host smart-1af167a1-f2b0-4a77-ac21-e7e52f648238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188677976 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_auto_blk_key_output.3
188677976
Directory /workspace/10.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect.3734333608
Short name T743
Test name
Test status
Simulation time 105183603196 ps
CPU time 31.69 seconds
Started Mar 24 01:15:19 PM PDT 24
Finished Mar 24 01:15:51 PM PDT 24
Peak memory 202224 kb
Host smart-36fffc93-0600-4aae-86c8-3e8dd80f7304
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734333608 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_c
trl_combo_detect.3734333608
Directory /workspace/10.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.143822488
Short name T205
Test name
Test status
Simulation time 2809780546 ps
CPU time 5.43 seconds
Started Mar 24 01:15:09 PM PDT 24
Finished Mar 24 01:15:14 PM PDT 24
Peak memory 202032 kb
Host smart-5fcc4e95-bdda-4721-ab71-605d02c7e0e9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143822488 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_c
trl_ec_pwr_on_rst.143822488
Directory /workspace/10.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_edge_detect.268185229
Short name T126
Test name
Test status
Simulation time 3470787452 ps
CPU time 8.02 seconds
Started Mar 24 01:15:09 PM PDT 24
Finished Mar 24 01:15:18 PM PDT 24
Peak memory 202052 kb
Host smart-7f8ac242-bf4e-4877-9e3d-71f2a3b0818a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268185229 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctr
l_edge_detect.268185229
Directory /workspace/10.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.1449125894
Short name T650
Test name
Test status
Simulation time 2626731332 ps
CPU time 2.13 seconds
Started Mar 24 01:15:11 PM PDT 24
Finished Mar 24 01:15:13 PM PDT 24
Peak memory 202036 kb
Host smart-81f6f572-a900-41ef-a18b-cc88f3a21944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449125894 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_flash_wr_prot_out.1449125894
Directory /workspace/10.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.2858252077
Short name T752
Test name
Test status
Simulation time 2474324434 ps
CPU time 2.56 seconds
Started Mar 24 01:15:12 PM PDT 24
Finished Mar 24 01:15:14 PM PDT 24
Peak memory 202080 kb
Host smart-30d1b729-ebe2-4d55-b090-ca0d6612d730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858252077 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_in_out_inverted.2858252077
Directory /workspace/10.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_access_test.2993180736
Short name T57
Test name
Test status
Simulation time 2262079513 ps
CPU time 6.64 seconds
Started Mar 24 01:15:08 PM PDT 24
Finished Mar 24 01:15:15 PM PDT 24
Peak memory 202020 kb
Host smart-0da05bf1-f62e-411b-ac4c-8036febb2b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993180736 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_access_test.2993180736
Directory /workspace/10.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_override_test.3266515874
Short name T513
Test name
Test status
Simulation time 2513219172 ps
CPU time 7.05 seconds
Started Mar 24 01:15:28 PM PDT 24
Finished Mar 24 01:15:35 PM PDT 24
Peak memory 202072 kb
Host smart-40d7cc06-3e6f-494e-8743-0106cfe30746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266515874 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_override_test.3266515874
Directory /workspace/10.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_smoke.2301685899
Short name T646
Test name
Test status
Simulation time 2137147265 ps
CPU time 2 seconds
Started Mar 24 01:15:18 PM PDT 24
Finished Mar 24 01:15:20 PM PDT 24
Peak memory 201940 kb
Host smart-71cee00a-354f-4a20-b989-9e960b8b7175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301685899 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_smoke.2301685899
Directory /workspace/10.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all.3252708889
Short name T756
Test name
Test status
Simulation time 47023010738 ps
CPU time 32.26 seconds
Started Mar 24 01:15:11 PM PDT 24
Finished Mar 24 01:15:43 PM PDT 24
Peak memory 202240 kb
Host smart-abc551ff-94e6-49c9-964d-e841db1b9428
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252708889 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_s
tress_all.3252708889
Directory /workspace/10.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.90330379
Short name T783
Test name
Test status
Simulation time 77459288135 ps
CPU time 41.8 seconds
Started Mar 24 01:15:07 PM PDT 24
Finished Mar 24 01:15:49 PM PDT 24
Peak memory 210672 kb
Host smart-0ee97a9d-85d9-4476-8ba9-f3b88bf44c27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90330379 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_stress_all_with_rand_reset.90330379
Directory /workspace/10.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.3483320436
Short name T685
Test name
Test status
Simulation time 6091083100 ps
CPU time 3.18 seconds
Started Mar 24 01:15:23 PM PDT 24
Finished Mar 24 01:15:26 PM PDT 24
Peak memory 202072 kb
Host smart-ce3f6b5b-ad03-4b50-8198-81ebcd9deb6f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483320436 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_ultra_low_pwr.3483320436
Directory /workspace/10.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_alert_test.727711880
Short name T605
Test name
Test status
Simulation time 2075365854 ps
CPU time 1.03 seconds
Started Mar 24 01:15:29 PM PDT 24
Finished Mar 24 01:15:30 PM PDT 24
Peak memory 202072 kb
Host smart-e53b97c3-67e3-4b1f-9e7a-c9263e2248ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727711880 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_alert_tes
t.727711880
Directory /workspace/11.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.930311735
Short name T620
Test name
Test status
Simulation time 3633783912 ps
CPU time 1.23 seconds
Started Mar 24 01:15:23 PM PDT 24
Finished Mar 24 01:15:25 PM PDT 24
Peak memory 202120 kb
Host smart-10ee934d-490b-4f3a-a4d9-fd6326a5fcde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930311735 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_auto_blk_key_output.930311735
Directory /workspace/11.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.2152539108
Short name T200
Test name
Test status
Simulation time 2798969809 ps
CPU time 2.04 seconds
Started Mar 24 01:15:07 PM PDT 24
Finished Mar 24 01:15:09 PM PDT 24
Peak memory 202044 kb
Host smart-2b78c68d-6590-45bb-a800-8d9ed70d909d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152539108 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_ec_pwr_on_rst.2152539108
Directory /workspace/11.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_edge_detect.1281134975
Short name T167
Test name
Test status
Simulation time 4544279178 ps
CPU time 8.2 seconds
Started Mar 24 01:15:19 PM PDT 24
Finished Mar 24 01:15:28 PM PDT 24
Peak memory 202088 kb
Host smart-0d02a81a-9d5b-4a21-aad6-4bc548c04f64
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281134975 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ct
rl_edge_detect.1281134975
Directory /workspace/11.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.1041158625
Short name T398
Test name
Test status
Simulation time 2612465691 ps
CPU time 7.68 seconds
Started Mar 24 01:15:08 PM PDT 24
Finished Mar 24 01:15:16 PM PDT 24
Peak memory 202048 kb
Host smart-dbcba89a-bc47-48d2-93af-cddb8455a48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041158625 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_flash_wr_prot_out.1041158625
Directory /workspace/11.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_in_out_inverted.2106556617
Short name T472
Test name
Test status
Simulation time 2462784064 ps
CPU time 2.25 seconds
Started Mar 24 01:15:12 PM PDT 24
Finished Mar 24 01:15:15 PM PDT 24
Peak memory 202060 kb
Host smart-a6fe57b3-b74a-4e96-a8bd-e39525b7fa78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106556617 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_in_out_inverted.2106556617
Directory /workspace/11.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_access_test.2247641434
Short name T758
Test name
Test status
Simulation time 2127863007 ps
CPU time 3.59 seconds
Started Mar 24 01:15:14 PM PDT 24
Finished Mar 24 01:15:17 PM PDT 24
Peak memory 201928 kb
Host smart-a7e6941d-29e2-4e64-8991-c4fd2785afcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247641434 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_access_test.2247641434
Directory /workspace/11.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_override_test.315798008
Short name T741
Test name
Test status
Simulation time 2507685041 ps
CPU time 7.23 seconds
Started Mar 24 01:15:10 PM PDT 24
Finished Mar 24 01:15:17 PM PDT 24
Peak memory 202080 kb
Host smart-81ecc60c-4419-4f94-b86a-5c4df2b8f28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315798008 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_override_test.315798008
Directory /workspace/11.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_smoke.2613775765
Short name T499
Test name
Test status
Simulation time 2162187889 ps
CPU time 1.31 seconds
Started Mar 24 01:15:14 PM PDT 24
Finished Mar 24 01:15:15 PM PDT 24
Peak memory 202048 kb
Host smart-dbd1b2db-b02e-4cd0-9a27-1063c31e3521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613775765 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_smoke.2613775765
Directory /workspace/11.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.585335407
Short name T301
Test name
Test status
Simulation time 32304503426 ps
CPU time 38.41 seconds
Started Mar 24 01:15:18 PM PDT 24
Finished Mar 24 01:15:57 PM PDT 24
Peak memory 210596 kb
Host smart-1873d9e1-e3f8-488f-bab2-518a35ebc3ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585335407 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_stress_all_with_rand_reset.585335407
Directory /workspace/11.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.3290119960
Short name T697
Test name
Test status
Simulation time 8205579966 ps
CPU time 2.42 seconds
Started Mar 24 01:15:10 PM PDT 24
Finished Mar 24 01:15:13 PM PDT 24
Peak memory 202032 kb
Host smart-7c7ffe73-0c7a-4681-8fa3-7ebeee2bcab0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290119960 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_ultra_low_pwr.3290119960
Directory /workspace/11.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_alert_test.1344226526
Short name T669
Test name
Test status
Simulation time 2015122210 ps
CPU time 5.69 seconds
Started Mar 24 01:15:27 PM PDT 24
Finished Mar 24 01:15:33 PM PDT 24
Peak memory 202104 kb
Host smart-f90ddeb7-83e9-4a84-a9ec-de7442bdc843
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344226526 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_alert_te
st.1344226526
Directory /workspace/12.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.1079699932
Short name T402
Test name
Test status
Simulation time 252399162239 ps
CPU time 49.94 seconds
Started Mar 24 01:15:21 PM PDT 24
Finished Mar 24 01:16:12 PM PDT 24
Peak memory 202120 kb
Host smart-81af2033-a511-47b7-ad23-7fd900078260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079699932 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_auto_blk_key_output.1
079699932
Directory /workspace/12.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.4123489284
Short name T578
Test name
Test status
Simulation time 24841429294 ps
CPU time 26.96 seconds
Started Mar 24 01:15:21 PM PDT 24
Finished Mar 24 01:15:49 PM PDT 24
Peak memory 202284 kb
Host smart-c29433d1-be63-48f7-a70f-aed402697f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123489284 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect_w
ith_pre_cond.4123489284
Directory /workspace/12.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.2486319688
Short name T156
Test name
Test status
Simulation time 2456438656 ps
CPU time 5.87 seconds
Started Mar 24 01:15:14 PM PDT 24
Finished Mar 24 01:15:20 PM PDT 24
Peak memory 202000 kb
Host smart-a602b44c-3899-4d0c-896e-c800c65a3f5f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486319688 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_ec_pwr_on_rst.2486319688
Directory /workspace/12.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_edge_detect.208272448
Short name T170
Test name
Test status
Simulation time 2416703992 ps
CPU time 6.08 seconds
Started Mar 24 01:15:28 PM PDT 24
Finished Mar 24 01:15:34 PM PDT 24
Peak memory 202052 kb
Host smart-8bf1f7dc-73b3-4110-8e60-dc729128060c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208272448 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctr
l_edge_detect.208272448
Directory /workspace/12.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.631352504
Short name T310
Test name
Test status
Simulation time 2612233423 ps
CPU time 7.01 seconds
Started Mar 24 01:15:17 PM PDT 24
Finished Mar 24 01:15:25 PM PDT 24
Peak memory 202072 kb
Host smart-00f5cbdb-35e0-419e-aa2d-56cc84b88da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631352504 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_flash_wr_prot_out.631352504
Directory /workspace/12.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.3131782235
Short name T505
Test name
Test status
Simulation time 2488659366 ps
CPU time 7.25 seconds
Started Mar 24 01:15:25 PM PDT 24
Finished Mar 24 01:15:32 PM PDT 24
Peak memory 202060 kb
Host smart-0e59e019-60c3-4793-8f1e-2f38ba1b2bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131782235 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_in_out_inverted.3131782235
Directory /workspace/12.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_access_test.1263308632
Short name T535
Test name
Test status
Simulation time 2088530573 ps
CPU time 2.02 seconds
Started Mar 24 01:15:26 PM PDT 24
Finished Mar 24 01:15:29 PM PDT 24
Peak memory 201904 kb
Host smart-bf345db8-4bc9-4882-8128-7cdbfbcca510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263308632 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_access_test.1263308632
Directory /workspace/12.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_override_test.943921392
Short name T391
Test name
Test status
Simulation time 2514385427 ps
CPU time 4.16 seconds
Started Mar 24 01:15:22 PM PDT 24
Finished Mar 24 01:15:31 PM PDT 24
Peak memory 202044 kb
Host smart-cf7037ba-7326-43c6-8616-48424f00b5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943921392 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_override_test.943921392
Directory /workspace/12.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_smoke.788820600
Short name T563
Test name
Test status
Simulation time 2116407301 ps
CPU time 3.34 seconds
Started Mar 24 01:15:15 PM PDT 24
Finished Mar 24 01:15:18 PM PDT 24
Peak memory 201944 kb
Host smart-cd0bad07-ab86-46c8-8760-c32eb48d7649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788820600 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_smoke.788820600
Directory /workspace/12.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.1427198211
Short name T572
Test name
Test status
Simulation time 7078487885 ps
CPU time 2.23 seconds
Started Mar 24 01:15:18 PM PDT 24
Finished Mar 24 01:15:21 PM PDT 24
Peak memory 202076 kb
Host smart-38b9f2a4-c9a2-4cff-b653-3e4e4b60a183
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427198211 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_ultra_low_pwr.1427198211
Directory /workspace/12.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_alert_test.363536091
Short name T412
Test name
Test status
Simulation time 2047598737 ps
CPU time 1.73 seconds
Started Mar 24 01:15:26 PM PDT 24
Finished Mar 24 01:15:29 PM PDT 24
Peak memory 202092 kb
Host smart-29509b1c-8ac9-4160-a111-bb15f53113c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363536091 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_alert_tes
t.363536091
Directory /workspace/13.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_auto_blk_key_output.461994694
Short name T168
Test name
Test status
Simulation time 3577227374 ps
CPU time 1.41 seconds
Started Mar 24 01:15:19 PM PDT 24
Finished Mar 24 01:15:20 PM PDT 24
Peak memory 202084 kb
Host smart-56028300-e7da-422a-bf98-695b7916ca05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461994694 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_auto_blk_key_output.461994694
Directory /workspace/13.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect.1482719328
Short name T1
Test name
Test status
Simulation time 79062114858 ps
CPU time 203.85 seconds
Started Mar 24 01:15:15 PM PDT 24
Finished Mar 24 01:18:39 PM PDT 24
Peak memory 202280 kb
Host smart-f49d90d1-fb9b-4d66-8db8-2b6b1d731f86
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482719328 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_c
trl_combo_detect.1482719328
Directory /workspace/13.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.1845467144
Short name T729
Test name
Test status
Simulation time 3704963846 ps
CPU time 1.59 seconds
Started Mar 24 01:15:29 PM PDT 24
Finished Mar 24 01:15:31 PM PDT 24
Peak memory 202024 kb
Host smart-9603e6a6-a68c-473a-a481-ac95ecb80861
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845467144 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_ec_pwr_on_rst.1845467144
Directory /workspace/13.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_edge_detect.644297642
Short name T750
Test name
Test status
Simulation time 3948930455 ps
CPU time 9.81 seconds
Started Mar 24 01:15:25 PM PDT 24
Finished Mar 24 01:15:35 PM PDT 24
Peak memory 202032 kb
Host smart-2a3f8428-1a59-4bf4-b3f4-414ca054e24d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644297642 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctr
l_edge_detect.644297642
Directory /workspace/13.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.3351007497
Short name T489
Test name
Test status
Simulation time 2633348974 ps
CPU time 2.35 seconds
Started Mar 24 01:15:26 PM PDT 24
Finished Mar 24 01:15:29 PM PDT 24
Peak memory 202084 kb
Host smart-ea6f0eb3-cdf2-4c73-bd77-c43681e74fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351007497 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_flash_wr_prot_out.3351007497
Directory /workspace/13.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.1808789133
Short name T471
Test name
Test status
Simulation time 2456465297 ps
CPU time 6.81 seconds
Started Mar 24 01:15:26 PM PDT 24
Finished Mar 24 01:15:34 PM PDT 24
Peak memory 202040 kb
Host smart-5222f48d-b3ed-4f2b-adc7-f5f7c8679ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808789133 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_in_out_inverted.1808789133
Directory /workspace/13.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_access_test.774300090
Short name T720
Test name
Test status
Simulation time 2097657357 ps
CPU time 3.48 seconds
Started Mar 24 01:15:17 PM PDT 24
Finished Mar 24 01:15:20 PM PDT 24
Peak memory 201880 kb
Host smart-2e14f5e0-6e9d-459a-bd6f-7a355aa0d2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774300090 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_access_test.774300090
Directory /workspace/13.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_override_test.1436415851
Short name T711
Test name
Test status
Simulation time 2509465001 ps
CPU time 6.86 seconds
Started Mar 24 01:15:22 PM PDT 24
Finished Mar 24 01:15:29 PM PDT 24
Peak memory 202024 kb
Host smart-af80969c-f41e-4f80-962f-43bc4c9a4340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436415851 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_override_test.1436415851
Directory /workspace/13.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_smoke.3160499308
Short name T474
Test name
Test status
Simulation time 2137843995 ps
CPU time 1.86 seconds
Started Mar 24 01:15:22 PM PDT 24
Finished Mar 24 01:15:24 PM PDT 24
Peak memory 201912 kb
Host smart-7a83ed26-ed22-4635-8e10-811c1249184b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160499308 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_smoke.3160499308
Directory /workspace/13.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all.2650101202
Short name T192
Test name
Test status
Simulation time 6332711619 ps
CPU time 4.82 seconds
Started Mar 24 01:15:23 PM PDT 24
Finished Mar 24 01:15:29 PM PDT 24
Peak memory 201960 kb
Host smart-71119d22-5890-489e-8e1b-25c21bab43dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650101202 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_s
tress_all.2650101202
Directory /workspace/13.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.4230624504
Short name T82
Test name
Test status
Simulation time 116215761242 ps
CPU time 20.09 seconds
Started Mar 24 01:15:19 PM PDT 24
Finished Mar 24 01:15:40 PM PDT 24
Peak memory 210748 kb
Host smart-6f25cbe4-b68c-4851-a637-877106abb84b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230624504 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_stress_all_with_rand_reset.4230624504
Directory /workspace/13.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_alert_test.3037457794
Short name T411
Test name
Test status
Simulation time 2043475291 ps
CPU time 1.9 seconds
Started Mar 24 01:15:23 PM PDT 24
Finished Mar 24 01:15:25 PM PDT 24
Peak memory 202088 kb
Host smart-e683b3ff-ccd0-4b62-8a2a-d5308ee33d82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037457794 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_alert_te
st.3037457794
Directory /workspace/14.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.404315261
Short name T463
Test name
Test status
Simulation time 3635256844 ps
CPU time 9.96 seconds
Started Mar 24 01:15:26 PM PDT 24
Finished Mar 24 01:15:36 PM PDT 24
Peak memory 202124 kb
Host smart-241ef200-c7dc-49cc-8f96-09074d8e6940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404315261 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_auto_blk_key_output.404315261
Directory /workspace/14.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.1457952380
Short name T72
Test name
Test status
Simulation time 28336317747 ps
CPU time 38.47 seconds
Started Mar 24 01:15:25 PM PDT 24
Finished Mar 24 01:16:04 PM PDT 24
Peak memory 202240 kb
Host smart-58fcffcb-3318-41e6-affc-fbc1c9548ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457952380 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect_w
ith_pre_cond.1457952380
Directory /workspace/14.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.539084746
Short name T220
Test name
Test status
Simulation time 3141738960 ps
CPU time 2.75 seconds
Started Mar 24 01:15:12 PM PDT 24
Finished Mar 24 01:15:14 PM PDT 24
Peak memory 202012 kb
Host smart-d337df07-c3a8-4084-bd67-ed72201b7e37
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539084746 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_c
trl_ec_pwr_on_rst.539084746
Directory /workspace/14.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_edge_detect.4198387883
Short name T35
Test name
Test status
Simulation time 3127010041 ps
CPU time 1 seconds
Started Mar 24 01:15:30 PM PDT 24
Finished Mar 24 01:15:31 PM PDT 24
Peak memory 202044 kb
Host smart-c08ae482-307e-48e1-a668-50215818a237
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198387883 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ct
rl_edge_detect.4198387883
Directory /workspace/14.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.2219094703
Short name T158
Test name
Test status
Simulation time 2620151125 ps
CPU time 4.75 seconds
Started Mar 24 01:15:26 PM PDT 24
Finished Mar 24 01:15:32 PM PDT 24
Peak memory 202076 kb
Host smart-f03920db-3807-4757-bc45-ec0625ee25bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219094703 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_flash_wr_prot_out.2219094703
Directory /workspace/14.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.1878248348
Short name T68
Test name
Test status
Simulation time 2489232206 ps
CPU time 2.01 seconds
Started Mar 24 01:15:27 PM PDT 24
Finished Mar 24 01:15:29 PM PDT 24
Peak memory 201980 kb
Host smart-47810ad3-0f63-4982-b4c5-2bac988811b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878248348 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_in_out_inverted.1878248348
Directory /workspace/14.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_access_test.2109617704
Short name T176
Test name
Test status
Simulation time 2037316360 ps
CPU time 5.74 seconds
Started Mar 24 01:15:24 PM PDT 24
Finished Mar 24 01:15:30 PM PDT 24
Peak memory 201928 kb
Host smart-9bd2ea8c-6f1c-4057-b873-42900504ae00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109617704 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_access_test.2109617704
Directory /workspace/14.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_override_test.4142774488
Short name T745
Test name
Test status
Simulation time 2516147291 ps
CPU time 5.21 seconds
Started Mar 24 01:15:17 PM PDT 24
Finished Mar 24 01:15:23 PM PDT 24
Peak memory 202052 kb
Host smart-cff2a63a-134c-4a23-a249-415026bf8744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142774488 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_override_test.4142774488
Directory /workspace/14.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_smoke.239683046
Short name T686
Test name
Test status
Simulation time 2109893366 ps
CPU time 6.23 seconds
Started Mar 24 01:15:26 PM PDT 24
Finished Mar 24 01:15:33 PM PDT 24
Peak memory 202180 kb
Host smart-aac831f0-6fc3-4998-b38d-cae31897a2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239683046 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_smoke.239683046
Directory /workspace/14.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all.1181157668
Short name T161
Test name
Test status
Simulation time 198023518602 ps
CPU time 243.6 seconds
Started Mar 24 01:15:20 PM PDT 24
Finished Mar 24 01:19:24 PM PDT 24
Peak memory 202256 kb
Host smart-28279982-8e18-400f-afb7-1ca537829dae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181157668 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_s
tress_all.1181157668
Directory /workspace/14.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.3178019408
Short name T575
Test name
Test status
Simulation time 4124023663 ps
CPU time 1.49 seconds
Started Mar 24 01:15:21 PM PDT 24
Finished Mar 24 01:15:23 PM PDT 24
Peak memory 202068 kb
Host smart-df6caa36-8dda-4f24-be97-760061439a50
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178019408 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_ultra_low_pwr.3178019408
Directory /workspace/14.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_alert_test.325015389
Short name T566
Test name
Test status
Simulation time 2027143620 ps
CPU time 1.76 seconds
Started Mar 24 01:15:29 PM PDT 24
Finished Mar 24 01:15:31 PM PDT 24
Peak memory 202008 kb
Host smart-69a17667-d7d2-48f0-af7e-3177b374de91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325015389 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_alert_tes
t.325015389
Directory /workspace/15.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.3577304709
Short name T585
Test name
Test status
Simulation time 3375493132 ps
CPU time 2.94 seconds
Started Mar 24 01:15:27 PM PDT 24
Finished Mar 24 01:15:30 PM PDT 24
Peak memory 202032 kb
Host smart-22c860b4-c894-4d96-bc46-b5c6b4b424c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577304709 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_auto_blk_key_output.3
577304709
Directory /workspace/15.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect.1651714921
Short name T248
Test name
Test status
Simulation time 161166969320 ps
CPU time 52.43 seconds
Started Mar 24 01:15:22 PM PDT 24
Finished Mar 24 01:16:15 PM PDT 24
Peak memory 202244 kb
Host smart-5d3cfae4-e55e-4130-8e4e-2738718a0b09
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651714921 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_c
trl_combo_detect.1651714921
Directory /workspace/15.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.862948915
Short name T433
Test name
Test status
Simulation time 3143037100 ps
CPU time 9.35 seconds
Started Mar 24 01:15:31 PM PDT 24
Finished Mar 24 01:15:40 PM PDT 24
Peak memory 202036 kb
Host smart-b179c9b0-e1c3-4d05-9539-359f1ccafa92
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862948915 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_c
trl_ec_pwr_on_rst.862948915
Directory /workspace/15.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_edge_detect.4037057022
Short name T80
Test name
Test status
Simulation time 3750059081 ps
CPU time 3.39 seconds
Started Mar 24 01:15:26 PM PDT 24
Finished Mar 24 01:15:29 PM PDT 24
Peak memory 202036 kb
Host smart-10d1aaed-29ac-40d5-9664-48aed0ead370
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037057022 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ct
rl_edge_detect.4037057022
Directory /workspace/15.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.1558701205
Short name T623
Test name
Test status
Simulation time 2612948481 ps
CPU time 7.69 seconds
Started Mar 24 01:15:25 PM PDT 24
Finished Mar 24 01:15:33 PM PDT 24
Peak memory 202028 kb
Host smart-3a4b986f-164f-494f-9a9e-454cccd817fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558701205 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_flash_wr_prot_out.1558701205
Directory /workspace/15.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.136732621
Short name T461
Test name
Test status
Simulation time 2496086400 ps
CPU time 2.39 seconds
Started Mar 24 01:15:27 PM PDT 24
Finished Mar 24 01:15:30 PM PDT 24
Peak memory 202060 kb
Host smart-33e0ab4c-c73f-4679-a1ac-324b715c73d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136732621 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_in_out_inverted.136732621
Directory /workspace/15.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_access_test.2301659050
Short name T619
Test name
Test status
Simulation time 2256911105 ps
CPU time 6.84 seconds
Started Mar 24 01:15:31 PM PDT 24
Finished Mar 24 01:15:38 PM PDT 24
Peak memory 202020 kb
Host smart-026b5012-1b3a-40ac-8d97-96cfdc0ec3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301659050 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_access_test.2301659050
Directory /workspace/15.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_override_test.41735041
Short name T614
Test name
Test status
Simulation time 2510912102 ps
CPU time 7.23 seconds
Started Mar 24 01:15:27 PM PDT 24
Finished Mar 24 01:15:35 PM PDT 24
Peak memory 202076 kb
Host smart-bec942da-f1b8-44ef-8983-fad03230109c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41735041 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_override_test.41735041
Directory /workspace/15.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_smoke.3066788428
Short name T674
Test name
Test status
Simulation time 2113921210 ps
CPU time 6.06 seconds
Started Mar 24 01:15:22 PM PDT 24
Finished Mar 24 01:15:28 PM PDT 24
Peak memory 201936 kb
Host smart-eaab6f92-2ab6-44e1-b9ac-4d039242886d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066788428 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_smoke.3066788428
Directory /workspace/15.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all.3503411631
Short name T389
Test name
Test status
Simulation time 1918489010322 ps
CPU time 179.83 seconds
Started Mar 24 01:15:23 PM PDT 24
Finished Mar 24 01:18:24 PM PDT 24
Peak memory 202064 kb
Host smart-f5e958aa-3887-4f95-8637-d4e9528767ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503411631 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_s
tress_all.3503411631
Directory /workspace/15.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.3261764674
Short name T773
Test name
Test status
Simulation time 11814904059 ps
CPU time 33.34 seconds
Started Mar 24 01:15:30 PM PDT 24
Finished Mar 24 01:16:04 PM PDT 24
Peak memory 202428 kb
Host smart-d0a68701-69dc-4141-92fa-5085a8ac6729
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261764674 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_stress_all_with_rand_reset.3261764674
Directory /workspace/15.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ultra_low_pwr.2624979305
Short name T511
Test name
Test status
Simulation time 7502642719 ps
CPU time 2.19 seconds
Started Mar 24 01:15:26 PM PDT 24
Finished Mar 24 01:15:29 PM PDT 24
Peak memory 202072 kb
Host smart-3bb544b1-c4bf-4b6b-bcb0-35f0d5153f8a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624979305 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_ultra_low_pwr.2624979305
Directory /workspace/15.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_alert_test.3232581224
Short name T603
Test name
Test status
Simulation time 2013812045 ps
CPU time 6.29 seconds
Started Mar 24 01:15:28 PM PDT 24
Finished Mar 24 01:15:35 PM PDT 24
Peak memory 202296 kb
Host smart-326d558b-5f39-4876-ba25-c9107e70c9cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232581224 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_alert_te
st.3232581224
Directory /workspace/16.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.3994798471
Short name T770
Test name
Test status
Simulation time 3251562884 ps
CPU time 4.66 seconds
Started Mar 24 01:15:24 PM PDT 24
Finished Mar 24 01:15:28 PM PDT 24
Peak memory 202140 kb
Host smart-32fbeec2-e814-4b6f-83de-6c5a4f8aa879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994798471 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_auto_blk_key_output.3
994798471
Directory /workspace/16.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.3597493519
Short name T599
Test name
Test status
Simulation time 3398044758 ps
CPU time 2.93 seconds
Started Mar 24 01:15:25 PM PDT 24
Finished Mar 24 01:15:28 PM PDT 24
Peak memory 202028 kb
Host smart-41bb5924-7c12-40e7-a1c0-46bc797b248e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597493519 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_ec_pwr_on_rst.3597493519
Directory /workspace/16.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_edge_detect.3773379263
Short name T194
Test name
Test status
Simulation time 6312714289 ps
CPU time 2.93 seconds
Started Mar 24 01:15:23 PM PDT 24
Finished Mar 24 01:15:27 PM PDT 24
Peak memory 202008 kb
Host smart-289b8c12-585c-43cd-9130-aca1a3d0b763
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773379263 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ct
rl_edge_detect.3773379263
Directory /workspace/16.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.1755878281
Short name T573
Test name
Test status
Simulation time 2624912960 ps
CPU time 2.43 seconds
Started Mar 24 01:15:24 PM PDT 24
Finished Mar 24 01:15:27 PM PDT 24
Peak memory 202004 kb
Host smart-5a0f9b8b-6d59-4861-8ac9-7d9d704a9a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755878281 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_flash_wr_prot_out.1755878281
Directory /workspace/16.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.489119095
Short name T558
Test name
Test status
Simulation time 2479614903 ps
CPU time 2.35 seconds
Started Mar 24 01:15:31 PM PDT 24
Finished Mar 24 01:15:33 PM PDT 24
Peak memory 202052 kb
Host smart-04ade21a-f526-4b47-bf99-7f993c3fdef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489119095 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_in_out_inverted.489119095
Directory /workspace/16.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_access_test.4201492720
Short name T410
Test name
Test status
Simulation time 2254256032 ps
CPU time 1.47 seconds
Started Mar 24 01:15:28 PM PDT 24
Finished Mar 24 01:15:30 PM PDT 24
Peak memory 201984 kb
Host smart-e3e1fd45-3742-4423-93f0-38141bedb5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201492720 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_access_test.4201492720
Directory /workspace/16.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_override_test.3120342155
Short name T457
Test name
Test status
Simulation time 2512668051 ps
CPU time 7.31 seconds
Started Mar 24 01:15:25 PM PDT 24
Finished Mar 24 01:15:33 PM PDT 24
Peak memory 202040 kb
Host smart-6eb9863e-0443-4851-8d1f-0e5216b4dca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120342155 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_override_test.3120342155
Directory /workspace/16.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_smoke.4012355934
Short name T751
Test name
Test status
Simulation time 2125157400 ps
CPU time 1.85 seconds
Started Mar 24 01:15:20 PM PDT 24
Finished Mar 24 01:15:22 PM PDT 24
Peak memory 201932 kb
Host smart-ca0e3bb9-b2f1-4286-8476-33d0171e8baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012355934 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_smoke.4012355934
Directory /workspace/16.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all.3923548063
Short name T517
Test name
Test status
Simulation time 7089768142 ps
CPU time 5.52 seconds
Started Mar 24 01:15:27 PM PDT 24
Finished Mar 24 01:15:33 PM PDT 24
Peak memory 202000 kb
Host smart-6bf9a700-76b4-4f1f-8d48-dd11e54af555
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923548063 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_s
tress_all.3923548063
Directory /workspace/16.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.572742221
Short name T99
Test name
Test status
Simulation time 4874787085157 ps
CPU time 373.74 seconds
Started Mar 24 01:15:24 PM PDT 24
Finished Mar 24 01:21:38 PM PDT 24
Peak memory 202096 kb
Host smart-649649c5-3dab-425e-8c19-621dfc1845a5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572742221 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_c
trl_ultra_low_pwr.572742221
Directory /workspace/16.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_alert_test.1883121100
Short name T468
Test name
Test status
Simulation time 2008041474 ps
CPU time 5.93 seconds
Started Mar 24 01:15:24 PM PDT 24
Finished Mar 24 01:15:30 PM PDT 24
Peak memory 202072 kb
Host smart-c7e858d3-ce5d-480a-ac0a-f2cdaa6aee25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883121100 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_alert_te
st.1883121100
Directory /workspace/17.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_auto_blk_key_output.4174788931
Short name T589
Test name
Test status
Simulation time 3518467614 ps
CPU time 9.88 seconds
Started Mar 24 01:15:42 PM PDT 24
Finished Mar 24 01:15:52 PM PDT 24
Peak memory 202088 kb
Host smart-24e3e15c-82fd-44cb-9350-3da825009cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174788931 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_auto_blk_key_output.4
174788931
Directory /workspace/17.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect.3088921316
Short name T247
Test name
Test status
Simulation time 69367599118 ps
CPU time 180.53 seconds
Started Mar 24 01:15:26 PM PDT 24
Finished Mar 24 01:18:27 PM PDT 24
Peak memory 202240 kb
Host smart-596d7c45-6127-45ff-a63c-49f10525d56f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088921316 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_c
trl_combo_detect.3088921316
Directory /workspace/17.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.1408906059
Short name T84
Test name
Test status
Simulation time 27579674761 ps
CPU time 77.31 seconds
Started Mar 24 01:15:28 PM PDT 24
Finished Mar 24 01:16:46 PM PDT 24
Peak memory 202336 kb
Host smart-c6dce9bf-c7c8-488c-a036-fa5973ec36a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408906059 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect_w
ith_pre_cond.1408906059
Directory /workspace/17.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.3321672640
Short name T780
Test name
Test status
Simulation time 4918424014 ps
CPU time 13.91 seconds
Started Mar 24 01:15:24 PM PDT 24
Finished Mar 24 01:15:38 PM PDT 24
Peak memory 202056 kb
Host smart-64b0b123-16c3-4a35-a8e8-570415909e83
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321672640 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_ec_pwr_on_rst.3321672640
Directory /workspace/17.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_edge_detect.3018451538
Short name T216
Test name
Test status
Simulation time 4738090521 ps
CPU time 12.15 seconds
Started Mar 24 01:15:31 PM PDT 24
Finished Mar 24 01:15:43 PM PDT 24
Peak memory 202132 kb
Host smart-d08d4bb2-ebb5-46da-b002-ec4a96f3b75d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018451538 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ct
rl_edge_detect.3018451538
Directory /workspace/17.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.2751367856
Short name T103
Test name
Test status
Simulation time 2622118947 ps
CPU time 3.54 seconds
Started Mar 24 01:15:30 PM PDT 24
Finished Mar 24 01:15:34 PM PDT 24
Peak memory 202048 kb
Host smart-f069b11d-e94d-48d5-9e29-45c7f6e36a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751367856 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_flash_wr_prot_out.2751367856
Directory /workspace/17.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.4240359452
Short name T570
Test name
Test status
Simulation time 2463996110 ps
CPU time 3.81 seconds
Started Mar 24 01:15:24 PM PDT 24
Finished Mar 24 01:15:28 PM PDT 24
Peak memory 202024 kb
Host smart-5f9f46be-b5e1-45d9-901f-0bea69bd01a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240359452 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_in_out_inverted.4240359452
Directory /workspace/17.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_access_test.3588669543
Short name T515
Test name
Test status
Simulation time 2049763413 ps
CPU time 6.15 seconds
Started Mar 24 01:15:31 PM PDT 24
Finished Mar 24 01:15:37 PM PDT 24
Peak memory 201912 kb
Host smart-2c83f4e7-5fe7-4a28-8887-990762e3922f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588669543 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_access_test.3588669543
Directory /workspace/17.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_override_test.3438332404
Short name T392
Test name
Test status
Simulation time 2511405501 ps
CPU time 7.38 seconds
Started Mar 24 01:15:25 PM PDT 24
Finished Mar 24 01:15:33 PM PDT 24
Peak memory 202080 kb
Host smart-c5d51561-a4af-4c7b-b459-bde7ea44fbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438332404 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_override_test.3438332404
Directory /workspace/17.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_smoke.1799472209
Short name T762
Test name
Test status
Simulation time 2113636998 ps
CPU time 6.09 seconds
Started Mar 24 01:15:27 PM PDT 24
Finished Mar 24 01:15:33 PM PDT 24
Peak memory 201928 kb
Host smart-3c617f39-b60e-4cf2-8a2e-ba607e756b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799472209 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_smoke.1799472209
Directory /workspace/17.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all.657813861
Short name T2
Test name
Test status
Simulation time 680778829344 ps
CPU time 312.47 seconds
Started Mar 24 01:15:29 PM PDT 24
Finished Mar 24 01:20:42 PM PDT 24
Peak memory 201932 kb
Host smart-f3626be4-6448-4aa3-ab7c-02789970edb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657813861 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_st
ress_all.657813861
Directory /workspace/17.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ultra_low_pwr.973370893
Short name T454
Test name
Test status
Simulation time 2779925289 ps
CPU time 5.14 seconds
Started Mar 24 01:15:23 PM PDT 24
Finished Mar 24 01:15:28 PM PDT 24
Peak memory 202072 kb
Host smart-7e16258d-ea7b-4472-8fcb-6030883b25b3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973370893 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_c
trl_ultra_low_pwr.973370893
Directory /workspace/17.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_alert_test.945239332
Short name T731
Test name
Test status
Simulation time 2033987995 ps
CPU time 1.87 seconds
Started Mar 24 01:15:25 PM PDT 24
Finished Mar 24 01:15:28 PM PDT 24
Peak memory 202040 kb
Host smart-75413252-3d6a-4c12-8354-eb4fd95a8a2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945239332 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_alert_tes
t.945239332
Directory /workspace/18.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.21549671
Short name T581
Test name
Test status
Simulation time 4095855225 ps
CPU time 10.79 seconds
Started Mar 24 01:15:33 PM PDT 24
Finished Mar 24 01:15:44 PM PDT 24
Peak memory 202140 kb
Host smart-fbd9f868-5c1f-4825-8eea-dcdaee7508ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21549671 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_auto_blk_key_output.21549671
Directory /workspace/18.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect.3833704381
Short name T255
Test name
Test status
Simulation time 71462219184 ps
CPU time 186.37 seconds
Started Mar 24 01:15:31 PM PDT 24
Finished Mar 24 01:18:38 PM PDT 24
Peak memory 202264 kb
Host smart-6734babc-2ccf-4993-82ce-7b387d2daa84
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833704381 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_c
trl_combo_detect.3833704381
Directory /workspace/18.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.41897943
Short name T593
Test name
Test status
Simulation time 45248420657 ps
CPU time 124.5 seconds
Started Mar 24 01:15:30 PM PDT 24
Finished Mar 24 01:17:34 PM PDT 24
Peak memory 202236 kb
Host smart-b13e5fef-68b8-4997-95a5-bc9663c24b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41897943 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect_wit
h_pre_cond.41897943
Directory /workspace/18.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.2777704834
Short name T723
Test name
Test status
Simulation time 3772569924 ps
CPU time 10.5 seconds
Started Mar 24 01:15:31 PM PDT 24
Finished Mar 24 01:15:41 PM PDT 24
Peak memory 202048 kb
Host smart-cfc4d2a7-f28e-42b5-8512-6e16ed5c2093
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777704834 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_ec_pwr_on_rst.2777704834
Directory /workspace/18.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_edge_detect.3906187189
Short name T199
Test name
Test status
Simulation time 501417068278 ps
CPU time 62.46 seconds
Started Mar 24 01:15:29 PM PDT 24
Finished Mar 24 01:16:31 PM PDT 24
Peak memory 202020 kb
Host smart-69fa1d24-054e-47f4-93d1-e490be415377
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906187189 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ct
rl_edge_detect.3906187189
Directory /workspace/18.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.661681469
Short name T776
Test name
Test status
Simulation time 2651660022 ps
CPU time 1.83 seconds
Started Mar 24 01:15:28 PM PDT 24
Finished Mar 24 01:15:30 PM PDT 24
Peak memory 202032 kb
Host smart-f80dac7c-49cd-465a-b13b-110c66988898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661681469 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_flash_wr_prot_out.661681469
Directory /workspace/18.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.376717485
Short name T465
Test name
Test status
Simulation time 2465770758 ps
CPU time 2.36 seconds
Started Mar 24 01:15:31 PM PDT 24
Finished Mar 24 01:15:34 PM PDT 24
Peak memory 202020 kb
Host smart-77f6bad0-d8df-403d-b343-dfced265c77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376717485 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_in_out_inverted.376717485
Directory /workspace/18.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_access_test.1355059360
Short name T528
Test name
Test status
Simulation time 2141230031 ps
CPU time 5.8 seconds
Started Mar 24 01:15:26 PM PDT 24
Finished Mar 24 01:15:32 PM PDT 24
Peak memory 201940 kb
Host smart-6a940924-1af2-4913-85a7-bd8a47b70b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355059360 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_access_test.1355059360
Directory /workspace/18.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_override_test.4141770075
Short name T703
Test name
Test status
Simulation time 2512106931 ps
CPU time 7.27 seconds
Started Mar 24 01:15:28 PM PDT 24
Finished Mar 24 01:15:36 PM PDT 24
Peak memory 202068 kb
Host smart-a8318c52-65ee-4d40-ac2d-c648914a8678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141770075 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_override_test.4141770075
Directory /workspace/18.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_smoke.2306944382
Short name T154
Test name
Test status
Simulation time 2113360046 ps
CPU time 6.5 seconds
Started Mar 24 01:15:32 PM PDT 24
Finished Mar 24 01:15:39 PM PDT 24
Peak memory 201872 kb
Host smart-06cb3426-e5d8-47a7-88c5-7e4dec2afe39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306944382 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_smoke.2306944382
Directory /workspace/18.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all.2535186163
Short name T477
Test name
Test status
Simulation time 11077582649 ps
CPU time 7.09 seconds
Started Mar 24 01:15:27 PM PDT 24
Finished Mar 24 01:15:34 PM PDT 24
Peak memory 202060 kb
Host smart-eb0dce32-fc1c-454d-8ed1-d70442fadcaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535186163 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_s
tress_all.2535186163
Directory /workspace/18.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.3110723806
Short name T172
Test name
Test status
Simulation time 77653655468 ps
CPU time 37.95 seconds
Started Mar 24 01:15:29 PM PDT 24
Finished Mar 24 01:16:07 PM PDT 24
Peak memory 210696 kb
Host smart-8ec526e2-df01-463a-878c-ce7354398d50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110723806 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_stress_all_with_rand_reset.3110723806
Directory /workspace/18.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.1341515856
Short name T690
Test name
Test status
Simulation time 7789576748 ps
CPU time 3.32 seconds
Started Mar 24 01:15:27 PM PDT 24
Finished Mar 24 01:15:30 PM PDT 24
Peak memory 202036 kb
Host smart-ba7099cd-cc6b-4667-b19e-79018329e7ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341515856 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_ultra_low_pwr.1341515856
Directory /workspace/18.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_alert_test.3323017345
Short name T709
Test name
Test status
Simulation time 2023027301 ps
CPU time 1.95 seconds
Started Mar 24 01:15:37 PM PDT 24
Finished Mar 24 01:15:39 PM PDT 24
Peak memory 202080 kb
Host smart-eeb7498b-c1de-4462-982f-85eaff2a4815
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323017345 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_alert_te
st.3323017345
Directory /workspace/19.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.3635902428
Short name T279
Test name
Test status
Simulation time 3598093923 ps
CPU time 9.65 seconds
Started Mar 24 01:15:32 PM PDT 24
Finished Mar 24 01:15:42 PM PDT 24
Peak memory 202100 kb
Host smart-05005065-271d-4553-ab75-02701865590c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635902428 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_auto_blk_key_output.3
635902428
Directory /workspace/19.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect.4233983877
Short name T735
Test name
Test status
Simulation time 160614078635 ps
CPU time 216.76 seconds
Started Mar 24 01:15:37 PM PDT 24
Finished Mar 24 01:19:13 PM PDT 24
Peak memory 202264 kb
Host smart-4f7bdbab-e2a3-4d22-834e-7e4c289658dc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233983877 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_c
trl_combo_detect.4233983877
Directory /workspace/19.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.1278749284
Short name T361
Test name
Test status
Simulation time 61540840711 ps
CPU time 86.48 seconds
Started Mar 24 01:15:35 PM PDT 24
Finished Mar 24 01:17:02 PM PDT 24
Peak memory 202296 kb
Host smart-d39eef1e-e0de-48d9-9b53-ac33aa60ab57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278749284 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect_w
ith_pre_cond.1278749284
Directory /workspace/19.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.1498049999
Short name T304
Test name
Test status
Simulation time 4050549332 ps
CPU time 11.39 seconds
Started Mar 24 01:15:31 PM PDT 24
Finished Mar 24 01:15:43 PM PDT 24
Peak memory 202032 kb
Host smart-d20c42cb-4f91-4a41-ace6-ce330fb911c1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498049999 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_ec_pwr_on_rst.1498049999
Directory /workspace/19.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_edge_detect.2483626992
Short name T7
Test name
Test status
Simulation time 4537017078 ps
CPU time 1.1 seconds
Started Mar 24 01:15:36 PM PDT 24
Finished Mar 24 01:15:37 PM PDT 24
Peak memory 202084 kb
Host smart-ed1824da-caf2-47f3-bc4c-e0988ef6a769
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483626992 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ct
rl_edge_detect.2483626992
Directory /workspace/19.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.1182976202
Short name T580
Test name
Test status
Simulation time 2612142791 ps
CPU time 7.52 seconds
Started Mar 24 01:15:31 PM PDT 24
Finished Mar 24 01:15:38 PM PDT 24
Peak memory 202116 kb
Host smart-feb04105-a486-4059-9b21-d1f16b4aa766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182976202 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_flash_wr_prot_out.1182976202
Directory /workspace/19.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.1240247988
Short name T23
Test name
Test status
Simulation time 2448560115 ps
CPU time 7.36 seconds
Started Mar 24 01:15:33 PM PDT 24
Finished Mar 24 01:15:40 PM PDT 24
Peak memory 202044 kb
Host smart-563a5a1d-aeb5-4a0a-a1c6-200566f92cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240247988 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_in_out_inverted.1240247988
Directory /workspace/19.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_access_test.2951095733
Short name T289
Test name
Test status
Simulation time 2235613532 ps
CPU time 3.26 seconds
Started Mar 24 01:15:32 PM PDT 24
Finished Mar 24 01:15:35 PM PDT 24
Peak memory 202016 kb
Host smart-dd2dabe3-93d1-49e1-a48a-2c5b4e9cb3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951095733 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_access_test.2951095733
Directory /workspace/19.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_override_test.944557668
Short name T493
Test name
Test status
Simulation time 2601248818 ps
CPU time 1.26 seconds
Started Mar 24 01:15:27 PM PDT 24
Finished Mar 24 01:15:28 PM PDT 24
Peak memory 202032 kb
Host smart-f66b7694-3f57-47e2-9d86-b156d4542252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944557668 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_override_test.944557668
Directory /workspace/19.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_smoke.614377480
Short name T652
Test name
Test status
Simulation time 2134019134 ps
CPU time 1.87 seconds
Started Mar 24 01:15:29 PM PDT 24
Finished Mar 24 01:15:31 PM PDT 24
Peak memory 201876 kb
Host smart-32813a45-f371-4076-8ece-821ec906d6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614377480 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_smoke.614377480
Directory /workspace/19.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all.1808355221
Short name T9
Test name
Test status
Simulation time 617143579323 ps
CPU time 32.44 seconds
Started Mar 24 01:15:29 PM PDT 24
Finished Mar 24 01:16:01 PM PDT 24
Peak memory 202296 kb
Host smart-eea0dda0-34ee-4421-a8cf-bf13de18b376
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808355221 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_s
tress_all.1808355221
Directory /workspace/19.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.2496156437
Short name T134
Test name
Test status
Simulation time 77755820918 ps
CPU time 183.29 seconds
Started Mar 24 01:15:38 PM PDT 24
Finished Mar 24 01:18:41 PM PDT 24
Peak memory 215324 kb
Host smart-908daba5-f9a9-4b5b-b60d-50a01323f15f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496156437 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_stress_all_with_rand_reset.2496156437
Directory /workspace/19.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.2952591432
Short name T290
Test name
Test status
Simulation time 2451018660 ps
CPU time 2.24 seconds
Started Mar 24 01:15:00 PM PDT 24
Finished Mar 24 01:15:03 PM PDT 24
Peak memory 201824 kb
Host smart-6235b494-4f5d-479e-8ec9-ba2b46a4d75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952591432 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst.2952591432
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3173142311
Short name T441
Test name
Test status
Simulation time 2311932345 ps
CPU time 2.08 seconds
Started Mar 24 01:14:50 PM PDT 24
Finished Mar 24 01:14:53 PM PDT 24
Peak memory 202012 kb
Host smart-90c9b330-4db6-4a3b-83ff-759702f0d6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173142311 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.3173142311
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.980513731
Short name T562
Test name
Test status
Simulation time 2737641328 ps
CPU time 1.88 seconds
Started Mar 24 01:14:53 PM PDT 24
Finished Mar 24 01:14:56 PM PDT 24
Peak memory 202048 kb
Host smart-7c8daca0-8a7a-466f-bd9c-1614e1146f96
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980513731 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ct
rl_ec_pwr_on_rst.980513731
Directory /workspace/2.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_edge_detect.3531315781
Short name T638
Test name
Test status
Simulation time 2789450945 ps
CPU time 2.33 seconds
Started Mar 24 01:14:55 PM PDT 24
Finished Mar 24 01:14:58 PM PDT 24
Peak memory 202092 kb
Host smart-cfd442a6-f7ea-403e-9fb3-9a7285c3757d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531315781 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctr
l_edge_detect.3531315781
Directory /workspace/2.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.3584621835
Short name T559
Test name
Test status
Simulation time 2620562851 ps
CPU time 2.41 seconds
Started Mar 24 01:14:49 PM PDT 24
Finished Mar 24 01:14:53 PM PDT 24
Peak memory 202056 kb
Host smart-f3ffab6c-b7b9-4924-8881-888b2b68008a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584621835 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_flash_wr_prot_out.3584621835
Directory /workspace/2.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_in_out_inverted.3498260153
Short name T452
Test name
Test status
Simulation time 2461231574 ps
CPU time 7.35 seconds
Started Mar 24 01:14:50 PM PDT 24
Finished Mar 24 01:14:58 PM PDT 24
Peak memory 202056 kb
Host smart-00f395c1-9f41-4f11-b8c5-5a0d3d59da3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498260153 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_in_out_inverted.3498260153
Directory /workspace/2.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_access_test.2035202113
Short name T694
Test name
Test status
Simulation time 2234059762 ps
CPU time 2.21 seconds
Started Mar 24 01:14:54 PM PDT 24
Finished Mar 24 01:14:56 PM PDT 24
Peak memory 202056 kb
Host smart-86f90255-89e0-4fa4-a40c-555295c8301c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035202113 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_access_test.2035202113
Directory /workspace/2.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_override_test.646504767
Short name T660
Test name
Test status
Simulation time 2540201301 ps
CPU time 2.1 seconds
Started Mar 24 01:14:50 PM PDT 24
Finished Mar 24 01:14:53 PM PDT 24
Peak memory 202024 kb
Host smart-ea635817-91f0-4df0-847d-97ca8a55abfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646504767 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_override_test.646504767
Directory /workspace/2.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_sec_cm.2628766916
Short name T261
Test name
Test status
Simulation time 22070978839 ps
CPU time 15.62 seconds
Started Mar 24 01:14:47 PM PDT 24
Finished Mar 24 01:15:03 PM PDT 24
Peak memory 221884 kb
Host smart-d6c27730-9ed5-4d32-b8c5-a30993d00dd9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628766916 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_sec_cm.2628766916
Directory /workspace/2.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_smoke.1309318948
Short name T132
Test name
Test status
Simulation time 2124551735 ps
CPU time 1.98 seconds
Started Mar 24 01:14:52 PM PDT 24
Finished Mar 24 01:14:54 PM PDT 24
Peak memory 201900 kb
Host smart-fd179619-5e39-4212-a6a9-57fb36cc5e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309318948 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_smoke.1309318948
Directory /workspace/2.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all.1309452197
Short name T763
Test name
Test status
Simulation time 233182853838 ps
CPU time 632.7 seconds
Started Mar 24 01:15:00 PM PDT 24
Finished Mar 24 01:25:33 PM PDT 24
Peak memory 202300 kb
Host smart-ff39a23e-e233-4f02-bc85-a9e10d4bf098
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309452197 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_st
ress_all.1309452197
Directory /workspace/2.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.2189379614
Short name T206
Test name
Test status
Simulation time 1151160415140 ps
CPU time 336.94 seconds
Started Mar 24 01:14:49 PM PDT 24
Finished Mar 24 01:20:27 PM PDT 24
Peak memory 218544 kb
Host smart-071b0c3c-0212-4681-adf6-2f92c1082674
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189379614 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_stress_all_with_rand_reset.2189379614
Directory /workspace/2.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.2611927659
Short name T61
Test name
Test status
Simulation time 6504983139 ps
CPU time 8.81 seconds
Started Mar 24 01:15:00 PM PDT 24
Finished Mar 24 01:15:09 PM PDT 24
Peak memory 202100 kb
Host smart-283eb3a4-6fdc-4b91-8e81-e808ad11fb46
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611927659 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_ultra_low_pwr.2611927659
Directory /workspace/2.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_alert_test.2635016763
Short name T127
Test name
Test status
Simulation time 2013625981 ps
CPU time 5.84 seconds
Started Mar 24 01:15:41 PM PDT 24
Finished Mar 24 01:15:47 PM PDT 24
Peak memory 202020 kb
Host smart-860795f1-343d-4a95-be29-569b3e952803
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635016763 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_alert_te
st.2635016763
Directory /workspace/20.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.1207555453
Short name T109
Test name
Test status
Simulation time 83912262177 ps
CPU time 166.08 seconds
Started Mar 24 01:15:28 PM PDT 24
Finished Mar 24 01:18:14 PM PDT 24
Peak memory 202144 kb
Host smart-1a04b383-d3c1-4d42-9afe-9f33a6668c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207555453 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_auto_blk_key_output.1
207555453
Directory /workspace/20.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect.2560353709
Short name T6
Test name
Test status
Simulation time 80071335049 ps
CPU time 17.69 seconds
Started Mar 24 01:15:34 PM PDT 24
Finished Mar 24 01:15:52 PM PDT 24
Peak memory 202304 kb
Host smart-0ad8a230-0257-436a-ab3c-8b71292c797f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560353709 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_c
trl_combo_detect.2560353709
Directory /workspace/20.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.4204091627
Short name T612
Test name
Test status
Simulation time 3135006131 ps
CPU time 8.38 seconds
Started Mar 24 01:15:29 PM PDT 24
Finished Mar 24 01:15:37 PM PDT 24
Peak memory 202044 kb
Host smart-2ba00040-5c31-483d-b097-fb7baae15283
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204091627 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_
ctrl_ec_pwr_on_rst.4204091627
Directory /workspace/20.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_edge_detect.569977487
Short name T228
Test name
Test status
Simulation time 3338192848 ps
CPU time 9.62 seconds
Started Mar 24 01:15:35 PM PDT 24
Finished Mar 24 01:15:45 PM PDT 24
Peak memory 201932 kb
Host smart-3dd0bace-7730-4ad4-a580-9ae21277e2c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569977487 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctr
l_edge_detect.569977487
Directory /workspace/20.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.414914211
Short name T759
Test name
Test status
Simulation time 2608983555 ps
CPU time 6.81 seconds
Started Mar 24 01:15:41 PM PDT 24
Finished Mar 24 01:15:48 PM PDT 24
Peak memory 202020 kb
Host smart-911f0862-6495-4952-af03-fc9b9b1a142d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414914211 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_flash_wr_prot_out.414914211
Directory /workspace/20.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.3180990703
Short name T538
Test name
Test status
Simulation time 2450498438 ps
CPU time 7.89 seconds
Started Mar 24 01:15:40 PM PDT 24
Finished Mar 24 01:15:48 PM PDT 24
Peak memory 202076 kb
Host smart-e8420f91-6b8d-4d74-b3d7-612c2f14d60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180990703 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_in_out_inverted.3180990703
Directory /workspace/20.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_access_test.925604232
Short name T284
Test name
Test status
Simulation time 2126036476 ps
CPU time 2.02 seconds
Started Mar 24 01:15:42 PM PDT 24
Finished Mar 24 01:15:44 PM PDT 24
Peak memory 201832 kb
Host smart-8c8de993-3048-41bd-8d92-5184bb4b83e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925604232 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_access_test.925604232
Directory /workspace/20.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_override_test.1951332322
Short name T656
Test name
Test status
Simulation time 2536525559 ps
CPU time 1.66 seconds
Started Mar 24 01:15:34 PM PDT 24
Finished Mar 24 01:15:36 PM PDT 24
Peak memory 202072 kb
Host smart-bf3c081d-2b2c-4fbe-b5c1-000e58d9446b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951332322 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_override_test.1951332322
Directory /workspace/20.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_smoke.2276700701
Short name T577
Test name
Test status
Simulation time 2116440700 ps
CPU time 3.56 seconds
Started Mar 24 01:15:44 PM PDT 24
Finished Mar 24 01:15:47 PM PDT 24
Peak memory 201868 kb
Host smart-03e0258f-736c-4a6f-aa24-8b16ea03ed69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276700701 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_smoke.2276700701
Directory /workspace/20.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all.3031088769
Short name T567
Test name
Test status
Simulation time 6565838180 ps
CPU time 3.72 seconds
Started Mar 24 01:15:41 PM PDT 24
Finished Mar 24 01:15:45 PM PDT 24
Peak memory 202024 kb
Host smart-b96baa54-0d23-4bdd-8469-131de3da9afc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031088769 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_s
tress_all.3031088769
Directory /workspace/20.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.448386843
Short name T118
Test name
Test status
Simulation time 38431358384 ps
CPU time 55.14 seconds
Started Mar 24 01:15:39 PM PDT 24
Finished Mar 24 01:16:34 PM PDT 24
Peak memory 218860 kb
Host smart-d59e149e-d803-4b80-b9eb-e8fdfde32700
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448386843 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_stress_all_with_rand_reset.448386843
Directory /workspace/20.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_alert_test.2958047289
Short name T203
Test name
Test status
Simulation time 2011946030 ps
CPU time 5.92 seconds
Started Mar 24 01:15:41 PM PDT 24
Finished Mar 24 01:15:47 PM PDT 24
Peak memory 202060 kb
Host smart-1d37b260-adda-400e-bf3e-5c5844b66efc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958047289 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_alert_te
st.2958047289
Directory /workspace/21.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_auto_blk_key_output.1990058258
Short name T52
Test name
Test status
Simulation time 37277576376 ps
CPU time 103.41 seconds
Started Mar 24 01:15:36 PM PDT 24
Finished Mar 24 01:17:19 PM PDT 24
Peak memory 202100 kb
Host smart-eeb77a76-a4d3-4731-887d-16fd58cc52e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990058258 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_auto_blk_key_output.1
990058258
Directory /workspace/21.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect.3506034995
Short name T630
Test name
Test status
Simulation time 87431292836 ps
CPU time 36.41 seconds
Started Mar 24 01:15:42 PM PDT 24
Finished Mar 24 01:16:18 PM PDT 24
Peak memory 202272 kb
Host smart-6f1b6e62-3615-44b0-89cd-790b6c668dfa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506034995 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_c
trl_combo_detect.3506034995
Directory /workspace/21.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.3334020039
Short name T384
Test name
Test status
Simulation time 102856665085 ps
CPU time 42.6 seconds
Started Mar 24 01:15:39 PM PDT 24
Finished Mar 24 01:16:21 PM PDT 24
Peak memory 202280 kb
Host smart-2a7277c7-d887-428e-991b-0058e82a8903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334020039 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect_w
ith_pre_cond.3334020039
Directory /workspace/21.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.3059642665
Short name T524
Test name
Test status
Simulation time 3317379695 ps
CPU time 8.81 seconds
Started Mar 24 01:15:44 PM PDT 24
Finished Mar 24 01:15:53 PM PDT 24
Peak memory 201924 kb
Host smart-794643f8-5bcb-451f-9faf-d982cde41e61
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059642665 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_
ctrl_ec_pwr_on_rst.3059642665
Directory /workspace/21.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_edge_detect.2609181694
Short name T616
Test name
Test status
Simulation time 4683423945 ps
CPU time 2.18 seconds
Started Mar 24 01:15:38 PM PDT 24
Finished Mar 24 01:15:40 PM PDT 24
Peak memory 202008 kb
Host smart-72a2c830-03d3-4455-a6ae-81be82363710
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609181694 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ct
rl_edge_detect.2609181694
Directory /workspace/21.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.3496134615
Short name T403
Test name
Test status
Simulation time 2607877770 ps
CPU time 7.49 seconds
Started Mar 24 01:15:41 PM PDT 24
Finished Mar 24 01:15:49 PM PDT 24
Peak memory 201800 kb
Host smart-61fd688e-2b16-47cd-bae1-bfeb1534f3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496134615 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_flash_wr_prot_out.3496134615
Directory /workspace/21.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_in_out_inverted.2738861537
Short name T748
Test name
Test status
Simulation time 2457577544 ps
CPU time 3.56 seconds
Started Mar 24 01:15:40 PM PDT 24
Finished Mar 24 01:15:44 PM PDT 24
Peak memory 202024 kb
Host smart-e1c81232-f736-46af-99f7-89b02eda50e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738861537 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_in_out_inverted.2738861537
Directory /workspace/21.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_access_test.3975874306
Short name T506
Test name
Test status
Simulation time 2186235579 ps
CPU time 6.43 seconds
Started Mar 24 01:15:39 PM PDT 24
Finished Mar 24 01:15:45 PM PDT 24
Peak memory 202032 kb
Host smart-cebd6c27-dbf3-4d7c-869b-8569984e503f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975874306 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_access_test.3975874306
Directory /workspace/21.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_override_test.2891416188
Short name T734
Test name
Test status
Simulation time 2516877187 ps
CPU time 4.22 seconds
Started Mar 24 01:15:30 PM PDT 24
Finished Mar 24 01:15:34 PM PDT 24
Peak memory 202060 kb
Host smart-bfbd86bb-7762-47e8-a698-9d2694b0692f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891416188 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_override_test.2891416188
Directory /workspace/21.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_smoke.2514270927
Short name T507
Test name
Test status
Simulation time 2122750139 ps
CPU time 2.21 seconds
Started Mar 24 01:15:41 PM PDT 24
Finished Mar 24 01:15:43 PM PDT 24
Peak memory 201876 kb
Host smart-628b7dbe-1671-47ef-8a5f-593fc24e72ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514270927 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_smoke.2514270927
Directory /workspace/21.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all.3391731676
Short name T311
Test name
Test status
Simulation time 10008701183 ps
CPU time 26.71 seconds
Started Mar 24 01:15:32 PM PDT 24
Finished Mar 24 01:15:59 PM PDT 24
Peak memory 202064 kb
Host smart-cca30b3d-73f9-42e4-8bbe-de5a18b1b995
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391731676 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_s
tress_all.3391731676
Directory /workspace/21.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ultra_low_pwr.1506980610
Short name T639
Test name
Test status
Simulation time 5223952442 ps
CPU time 7.6 seconds
Started Mar 24 01:15:29 PM PDT 24
Finished Mar 24 01:15:37 PM PDT 24
Peak memory 202024 kb
Host smart-a180211f-d390-40fa-8dec-2e288f52d17d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506980610 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_
ctrl_ultra_low_pwr.1506980610
Directory /workspace/21.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_alert_test.376885698
Short name T555
Test name
Test status
Simulation time 2049484670 ps
CPU time 1.49 seconds
Started Mar 24 01:15:39 PM PDT 24
Finished Mar 24 01:15:41 PM PDT 24
Peak memory 202104 kb
Host smart-48077e04-24f0-4874-86e8-5aeab01693e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376885698 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_alert_tes
t.376885698
Directory /workspace/22.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.1089893993
Short name T303
Test name
Test status
Simulation time 3301227430 ps
CPU time 4.74 seconds
Started Mar 24 01:15:41 PM PDT 24
Finished Mar 24 01:15:46 PM PDT 24
Peak memory 202080 kb
Host smart-5d2f4c39-2095-463a-8d64-c229fa1b6c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089893993 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_auto_blk_key_output.1
089893993
Directory /workspace/22.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect.3591419565
Short name T712
Test name
Test status
Simulation time 114523910295 ps
CPU time 314.86 seconds
Started Mar 24 01:15:39 PM PDT 24
Finished Mar 24 01:20:54 PM PDT 24
Peak memory 202328 kb
Host smart-c7b0f124-2c5b-4486-854a-7d1a83aafa66
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591419565 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_c
trl_combo_detect.3591419565
Directory /workspace/22.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.541885769
Short name T481
Test name
Test status
Simulation time 2755784835 ps
CPU time 7.46 seconds
Started Mar 24 01:15:38 PM PDT 24
Finished Mar 24 01:15:46 PM PDT 24
Peak memory 202028 kb
Host smart-ebce7e22-9154-41cf-8ae4-fbf72cb733bc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541885769 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_c
trl_ec_pwr_on_rst.541885769
Directory /workspace/22.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_edge_detect.2143900111
Short name T689
Test name
Test status
Simulation time 3143809286 ps
CPU time 8.33 seconds
Started Mar 24 01:15:31 PM PDT 24
Finished Mar 24 01:15:39 PM PDT 24
Peak memory 202072 kb
Host smart-431391ac-f55c-4b32-8f02-03cbfd00032c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143900111 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ct
rl_edge_detect.2143900111
Directory /workspace/22.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.4220133101
Short name T408
Test name
Test status
Simulation time 2614403253 ps
CPU time 6.85 seconds
Started Mar 24 01:15:37 PM PDT 24
Finished Mar 24 01:15:43 PM PDT 24
Peak memory 202056 kb
Host smart-912285b5-c47d-4547-9d94-d0f27ba4e322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220133101 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_flash_wr_prot_out.4220133101
Directory /workspace/22.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.1715091741
Short name T460
Test name
Test status
Simulation time 2465657690 ps
CPU time 3.76 seconds
Started Mar 24 01:15:32 PM PDT 24
Finished Mar 24 01:15:37 PM PDT 24
Peak memory 202056 kb
Host smart-2f73e2e6-ef32-453a-8f9e-827a37a7f8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715091741 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_in_out_inverted.1715091741
Directory /workspace/22.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_access_test.1180149801
Short name T424
Test name
Test status
Simulation time 2155473009 ps
CPU time 6.05 seconds
Started Mar 24 01:15:39 PM PDT 24
Finished Mar 24 01:15:45 PM PDT 24
Peak memory 202048 kb
Host smart-2df0f2eb-c14b-4f8a-8e0e-ff3d82be24fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180149801 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_access_test.1180149801
Directory /workspace/22.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_override_test.1102953385
Short name T421
Test name
Test status
Simulation time 2511782505 ps
CPU time 7.1 seconds
Started Mar 24 01:15:39 PM PDT 24
Finished Mar 24 01:15:46 PM PDT 24
Peak memory 202096 kb
Host smart-479a91c4-7959-4140-9081-c48c151b5ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102953385 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_override_test.1102953385
Directory /workspace/22.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_smoke.237791638
Short name T594
Test name
Test status
Simulation time 2135750962 ps
CPU time 1.36 seconds
Started Mar 24 01:15:43 PM PDT 24
Finished Mar 24 01:15:45 PM PDT 24
Peak memory 201896 kb
Host smart-03fa8713-9a9c-4d88-aaf2-acd0ca94f63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237791638 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_smoke.237791638
Directory /workspace/22.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all.778371473
Short name T522
Test name
Test status
Simulation time 8882420762 ps
CPU time 11.69 seconds
Started Mar 24 01:15:41 PM PDT 24
Finished Mar 24 01:15:53 PM PDT 24
Peak memory 202064 kb
Host smart-e053ac44-4a2b-483e-8d24-2c1a26684eb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778371473 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_st
ress_all.778371473
Directory /workspace/22.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.2079743901
Short name T151
Test name
Test status
Simulation time 73579992984 ps
CPU time 42.44 seconds
Started Mar 24 01:15:40 PM PDT 24
Finished Mar 24 01:16:23 PM PDT 24
Peak memory 218020 kb
Host smart-3252f076-46e9-480f-b7dc-0d8778cc76b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079743901 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_stress_all_with_rand_reset.2079743901
Directory /workspace/22.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.2860021593
Short name T582
Test name
Test status
Simulation time 4092614746 ps
CPU time 1.42 seconds
Started Mar 24 01:15:40 PM PDT 24
Finished Mar 24 01:15:42 PM PDT 24
Peak memory 202028 kb
Host smart-17228849-1b27-4aca-8815-eb06bf5f40e7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860021593 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_
ctrl_ultra_low_pwr.2860021593
Directory /workspace/22.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_alert_test.4240561806
Short name T487
Test name
Test status
Simulation time 2021819438 ps
CPU time 3.28 seconds
Started Mar 24 01:15:39 PM PDT 24
Finished Mar 24 01:15:43 PM PDT 24
Peak memory 201996 kb
Host smart-ddb688fd-a2ea-4076-be04-7073fef91627
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240561806 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_alert_te
st.4240561806
Directory /workspace/23.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.2421386370
Short name T225
Test name
Test status
Simulation time 3301930558 ps
CPU time 9.84 seconds
Started Mar 24 01:15:44 PM PDT 24
Finished Mar 24 01:15:55 PM PDT 24
Peak memory 202096 kb
Host smart-5c9f14b9-04f7-41f0-8b2f-3da7d296312a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421386370 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_auto_blk_key_output.2
421386370
Directory /workspace/23.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.2051538809
Short name T375
Test name
Test status
Simulation time 65965825088 ps
CPU time 50.64 seconds
Started Mar 24 01:15:41 PM PDT 24
Finished Mar 24 01:16:32 PM PDT 24
Peak memory 202204 kb
Host smart-69a490c2-1329-4775-8d73-66e82319c5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051538809 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect_w
ith_pre_cond.2051538809
Directory /workspace/23.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.3511300323
Short name T667
Test name
Test status
Simulation time 3166405769 ps
CPU time 2.15 seconds
Started Mar 24 01:15:41 PM PDT 24
Finished Mar 24 01:15:44 PM PDT 24
Peak memory 202036 kb
Host smart-6b209dde-c750-44cc-b9df-604a020c0704
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511300323 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_
ctrl_ec_pwr_on_rst.3511300323
Directory /workspace/23.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_edge_detect.3142157432
Short name T104
Test name
Test status
Simulation time 3252832098 ps
CPU time 2.09 seconds
Started Mar 24 01:15:44 PM PDT 24
Finished Mar 24 01:15:47 PM PDT 24
Peak memory 202072 kb
Host smart-e03657ad-d09d-47ff-919e-3336ca2930e1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142157432 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ct
rl_edge_detect.3142157432
Directory /workspace/23.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.3973201850
Short name T701
Test name
Test status
Simulation time 2620684130 ps
CPU time 4.14 seconds
Started Mar 24 01:15:36 PM PDT 24
Finished Mar 24 01:15:40 PM PDT 24
Peak memory 202024 kb
Host smart-a1cae39a-1b5a-4a7c-b8dc-111b3528e91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973201850 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_flash_wr_prot_out.3973201850
Directory /workspace/23.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_in_out_inverted.1635461783
Short name T782
Test name
Test status
Simulation time 2477703164 ps
CPU time 2.13 seconds
Started Mar 24 01:15:42 PM PDT 24
Finished Mar 24 01:15:44 PM PDT 24
Peak memory 202052 kb
Host smart-886456bd-9ae3-43c4-935e-f8611f6ce275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635461783 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_in_out_inverted.1635461783
Directory /workspace/23.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_access_test.1865316710
Short name T236
Test name
Test status
Simulation time 2025834297 ps
CPU time 6.18 seconds
Started Mar 24 01:15:47 PM PDT 24
Finished Mar 24 01:15:58 PM PDT 24
Peak memory 201796 kb
Host smart-1b566064-5d3d-40d0-ac41-26bd7f00441d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865316710 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_access_test.1865316710
Directory /workspace/23.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_override_test.1750494258
Short name T17
Test name
Test status
Simulation time 2512079005 ps
CPU time 4.03 seconds
Started Mar 24 01:15:39 PM PDT 24
Finished Mar 24 01:15:43 PM PDT 24
Peak memory 202064 kb
Host smart-45348b41-d1fe-4f35-9eef-6ceec0f22125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750494258 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_override_test.1750494258
Directory /workspace/23.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_smoke.754679516
Short name T775
Test name
Test status
Simulation time 2115008416 ps
CPU time 3.37 seconds
Started Mar 24 01:15:45 PM PDT 24
Finished Mar 24 01:15:49 PM PDT 24
Peak memory 201956 kb
Host smart-78d99f19-d7e6-4aba-a57d-e7dffb7d079c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754679516 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_smoke.754679516
Directory /workspace/23.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.82601771
Short name T186
Test name
Test status
Simulation time 39650701369 ps
CPU time 25.1 seconds
Started Mar 24 01:15:39 PM PDT 24
Finished Mar 24 01:16:04 PM PDT 24
Peak memory 210544 kb
Host smart-990b5540-3bb5-4b36-a802-aeaf41f6e253
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82601771 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_stress_all_with_rand_reset.82601771
Directory /workspace/23.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.756046655
Short name T60
Test name
Test status
Simulation time 6497051285 ps
CPU time 7.97 seconds
Started Mar 24 01:15:42 PM PDT 24
Finished Mar 24 01:15:50 PM PDT 24
Peak memory 202080 kb
Host smart-0d7f97f0-f24d-4513-86c3-5734822d0f17
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756046655 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_c
trl_ultra_low_pwr.756046655
Directory /workspace/23.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_alert_test.227434886
Short name T138
Test name
Test status
Simulation time 2030854007 ps
CPU time 1.92 seconds
Started Mar 24 01:15:41 PM PDT 24
Finished Mar 24 01:15:43 PM PDT 24
Peak memory 202148 kb
Host smart-fa0d6469-c73f-4512-b6e2-a5966580c2ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227434886 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_alert_tes
t.227434886
Directory /workspace/24.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.3143923599
Short name T440
Test name
Test status
Simulation time 231465602522 ps
CPU time 86.21 seconds
Started Mar 24 01:15:38 PM PDT 24
Finished Mar 24 01:17:04 PM PDT 24
Peak memory 202112 kb
Host smart-a4d0ea05-e9d6-4d0f-ba33-c642193622f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143923599 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_auto_blk_key_output.3
143923599
Directory /workspace/24.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect.2371850988
Short name T340
Test name
Test status
Simulation time 178273389646 ps
CPU time 123.13 seconds
Started Mar 24 01:15:37 PM PDT 24
Finished Mar 24 01:17:40 PM PDT 24
Peak memory 202248 kb
Host smart-e6a53043-46b9-4581-9021-36cb6a82f58f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371850988 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_c
trl_combo_detect.2371850988
Directory /workspace/24.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.4266986601
Short name T540
Test name
Test status
Simulation time 25590510614 ps
CPU time 31.88 seconds
Started Mar 24 01:15:41 PM PDT 24
Finished Mar 24 01:16:13 PM PDT 24
Peak memory 202284 kb
Host smart-8836a4cf-d175-4c90-ad2b-09d4b87b281f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266986601 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect_w
ith_pre_cond.4266986601
Directory /workspace/24.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.424058221
Short name T625
Test name
Test status
Simulation time 3215395170 ps
CPU time 9.53 seconds
Started Mar 24 01:15:42 PM PDT 24
Finished Mar 24 01:15:51 PM PDT 24
Peak memory 202048 kb
Host smart-a0cb3750-a3bf-42a0-ac55-710c84d2ebd3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424058221 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_c
trl_ec_pwr_on_rst.424058221
Directory /workspace/24.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_edge_detect.966558247
Short name T150
Test name
Test status
Simulation time 3390642649 ps
CPU time 3.86 seconds
Started Mar 24 01:15:43 PM PDT 24
Finished Mar 24 01:15:47 PM PDT 24
Peak memory 202032 kb
Host smart-b8cb9b94-1416-41ef-a016-584cdd7237ac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966558247 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctr
l_edge_detect.966558247
Directory /workspace/24.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.2912834239
Short name T676
Test name
Test status
Simulation time 2626949742 ps
CPU time 2.4 seconds
Started Mar 24 01:15:41 PM PDT 24
Finished Mar 24 01:15:44 PM PDT 24
Peak memory 202024 kb
Host smart-f091956a-6b68-4d00-a3c4-f58af265707d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912834239 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_flash_wr_prot_out.2912834239
Directory /workspace/24.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.3319998330
Short name T399
Test name
Test status
Simulation time 2470066339 ps
CPU time 2.13 seconds
Started Mar 24 01:15:34 PM PDT 24
Finished Mar 24 01:15:37 PM PDT 24
Peak memory 202072 kb
Host smart-e24182c3-e42c-46f5-aa0e-f26fce48ad09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319998330 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_in_out_inverted.3319998330
Directory /workspace/24.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_access_test.3508669519
Short name T739
Test name
Test status
Simulation time 2138394823 ps
CPU time 3.5 seconds
Started Mar 24 01:15:41 PM PDT 24
Finished Mar 24 01:15:45 PM PDT 24
Peak memory 201660 kb
Host smart-e337a17d-1e77-4488-8abb-93d37eb92b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508669519 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_access_test.3508669519
Directory /workspace/24.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_override_test.2269416135
Short name T537
Test name
Test status
Simulation time 2518249279 ps
CPU time 3.77 seconds
Started Mar 24 01:15:42 PM PDT 24
Finished Mar 24 01:15:45 PM PDT 24
Peak memory 202024 kb
Host smart-eef9e9ee-8975-4b2f-8aaf-25b44195e42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269416135 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_override_test.2269416135
Directory /workspace/24.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_smoke.4030001876
Short name T784
Test name
Test status
Simulation time 2122937481 ps
CPU time 2.11 seconds
Started Mar 24 01:15:41 PM PDT 24
Finished Mar 24 01:15:44 PM PDT 24
Peak memory 201888 kb
Host smart-c2f77179-9111-42c8-bffe-3a86d1de186d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030001876 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_smoke.4030001876
Directory /workspace/24.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all.354532497
Short name T671
Test name
Test status
Simulation time 8729260390 ps
CPU time 11.44 seconds
Started Mar 24 01:15:39 PM PDT 24
Finished Mar 24 01:15:50 PM PDT 24
Peak memory 202036 kb
Host smart-ed2beb65-8800-47ce-8580-50a03ef0beca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354532497 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_st
ress_all.354532497
Directory /workspace/24.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.66739457
Short name T196
Test name
Test status
Simulation time 20300810983 ps
CPU time 50.21 seconds
Started Mar 24 01:15:39 PM PDT 24
Finished Mar 24 01:16:29 PM PDT 24
Peak memory 211728 kb
Host smart-103d0d96-35bd-404e-b423-bece6b9ad9cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66739457 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_stress_all_with_rand_reset.66739457
Directory /workspace/24.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.3862808510
Short name T137
Test name
Test status
Simulation time 1871257351014 ps
CPU time 574.48 seconds
Started Mar 24 01:15:41 PM PDT 24
Finished Mar 24 01:25:16 PM PDT 24
Peak memory 202052 kb
Host smart-d103333d-22aa-4e7d-aa0a-8995b123d4f2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862808510 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_
ctrl_ultra_low_pwr.3862808510
Directory /workspace/24.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_alert_test.406261687
Short name T444
Test name
Test status
Simulation time 2032022850 ps
CPU time 2.21 seconds
Started Mar 24 01:15:41 PM PDT 24
Finished Mar 24 01:15:43 PM PDT 24
Peak memory 202108 kb
Host smart-c36988f6-6288-439b-8773-d68df5ea6e3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406261687 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_alert_tes
t.406261687
Directory /workspace/25.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.678539716
Short name T628
Test name
Test status
Simulation time 3050818619 ps
CPU time 2.11 seconds
Started Mar 24 01:15:39 PM PDT 24
Finished Mar 24 01:15:41 PM PDT 24
Peak memory 202128 kb
Host smart-64b6d778-0133-4e8f-b34a-7b74a3799365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678539716 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_auto_blk_key_output.678539716
Directory /workspace/25.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect.2893852335
Short name T251
Test name
Test status
Simulation time 186464888358 ps
CPU time 124.43 seconds
Started Mar 24 01:15:43 PM PDT 24
Finished Mar 24 01:17:48 PM PDT 24
Peak memory 202264 kb
Host smart-4c84ed31-a526-49f3-93bb-9abe7761fb41
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893852335 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_c
trl_combo_detect.2893852335
Directory /workspace/25.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.3791577861
Short name T484
Test name
Test status
Simulation time 3171032629 ps
CPU time 2.53 seconds
Started Mar 24 01:15:41 PM PDT 24
Finished Mar 24 01:15:44 PM PDT 24
Peak memory 202000 kb
Host smart-a5c2af49-0c28-4acc-b828-5c4bb15c027d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791577861 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_
ctrl_ec_pwr_on_rst.3791577861
Directory /workspace/25.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_edge_detect.2778113591
Short name T155
Test name
Test status
Simulation time 4952557362 ps
CPU time 1.11 seconds
Started Mar 24 01:15:47 PM PDT 24
Finished Mar 24 01:15:48 PM PDT 24
Peak memory 201936 kb
Host smart-e884c77d-16d6-4e7a-8eb7-bd0101cefd4b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778113591 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ct
rl_edge_detect.2778113591
Directory /workspace/25.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.1751357780
Short name T56
Test name
Test status
Simulation time 2623239352 ps
CPU time 2.46 seconds
Started Mar 24 01:15:37 PM PDT 24
Finished Mar 24 01:15:39 PM PDT 24
Peak memory 202056 kb
Host smart-cde20e8f-1004-4f41-86c0-c26a11fd8266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751357780 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_flash_wr_prot_out.1751357780
Directory /workspace/25.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.1513450388
Short name T66
Test name
Test status
Simulation time 2476520902 ps
CPU time 8.28 seconds
Started Mar 24 01:15:42 PM PDT 24
Finished Mar 24 01:15:50 PM PDT 24
Peak memory 202056 kb
Host smart-d186e156-1bab-4c0a-8393-6271c8522481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513450388 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_in_out_inverted.1513450388
Directory /workspace/25.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_access_test.2836288532
Short name T202
Test name
Test status
Simulation time 2054326051 ps
CPU time 5.91 seconds
Started Mar 24 01:15:40 PM PDT 24
Finished Mar 24 01:15:46 PM PDT 24
Peak memory 201932 kb
Host smart-3659c797-a128-4975-ae2d-7cd83f946b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836288532 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_access_test.2836288532
Directory /workspace/25.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_override_test.2260800745
Short name T296
Test name
Test status
Simulation time 2524992417 ps
CPU time 2.25 seconds
Started Mar 24 01:15:37 PM PDT 24
Finished Mar 24 01:15:39 PM PDT 24
Peak memory 201952 kb
Host smart-9e03b997-ef58-4c9d-ad0d-e7efe6aacb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260800745 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_override_test.2260800745
Directory /workspace/25.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_smoke.3856249037
Short name T648
Test name
Test status
Simulation time 2110674260 ps
CPU time 6.38 seconds
Started Mar 24 01:15:41 PM PDT 24
Finished Mar 24 01:15:48 PM PDT 24
Peak memory 201908 kb
Host smart-abf1ea69-77fb-4aba-8302-596d9d651eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856249037 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_smoke.3856249037
Directory /workspace/25.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all.2579417553
Short name T213
Test name
Test status
Simulation time 8154545554 ps
CPU time 11.66 seconds
Started Mar 24 01:15:51 PM PDT 24
Finished Mar 24 01:16:02 PM PDT 24
Peak memory 201988 kb
Host smart-361ffaa0-8363-4c71-8a54-ee3b0da55009
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579417553 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_s
tress_all.2579417553
Directory /workspace/25.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.425541001
Short name T121
Test name
Test status
Simulation time 69121570949 ps
CPU time 76.63 seconds
Started Mar 24 01:15:42 PM PDT 24
Finished Mar 24 01:16:59 PM PDT 24
Peak memory 210588 kb
Host smart-06812b83-6e15-477c-af1a-f1e152100d09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425541001 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_stress_all_with_rand_reset.425541001
Directory /workspace/25.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.2968917484
Short name T771
Test name
Test status
Simulation time 2750412588 ps
CPU time 6.28 seconds
Started Mar 24 01:15:42 PM PDT 24
Finished Mar 24 01:15:48 PM PDT 24
Peak memory 202064 kb
Host smart-a9c5ff14-5d1f-48aa-a116-ea63c4f24181
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968917484 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_
ctrl_ultra_low_pwr.2968917484
Directory /workspace/25.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_alert_test.446725940
Short name T550
Test name
Test status
Simulation time 2010197826 ps
CPU time 5.94 seconds
Started Mar 24 01:15:47 PM PDT 24
Finished Mar 24 01:15:53 PM PDT 24
Peak memory 202064 kb
Host smart-092796bf-e280-4882-9747-f0fe6b832107
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446725940 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_alert_tes
t.446725940
Directory /workspace/26.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.261509321
Short name T425
Test name
Test status
Simulation time 3565131888 ps
CPU time 10.23 seconds
Started Mar 24 01:15:41 PM PDT 24
Finished Mar 24 01:15:51 PM PDT 24
Peak memory 202116 kb
Host smart-9670d71f-7cbd-49c6-95fd-6e7829cc8d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261509321 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_auto_blk_key_output.261509321
Directory /workspace/26.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect.392635868
Short name T341
Test name
Test status
Simulation time 124556971227 ps
CPU time 152.64 seconds
Started Mar 24 01:15:44 PM PDT 24
Finished Mar 24 01:18:17 PM PDT 24
Peak memory 202212 kb
Host smart-a6a2241b-dcf0-46a5-8e74-77b2a87a7e1d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392635868 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ct
rl_combo_detect.392635868
Directory /workspace/26.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.1738021197
Short name T592
Test name
Test status
Simulation time 70455451106 ps
CPU time 47.72 seconds
Started Mar 24 01:15:47 PM PDT 24
Finished Mar 24 01:16:35 PM PDT 24
Peak memory 202200 kb
Host smart-cdec133d-1f6c-4139-9d7f-67f935ee9e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738021197 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect_w
ith_pre_cond.1738021197
Directory /workspace/26.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.3141697556
Short name T717
Test name
Test status
Simulation time 253635647290 ps
CPU time 157.13 seconds
Started Mar 24 01:15:41 PM PDT 24
Finished Mar 24 01:18:18 PM PDT 24
Peak memory 202028 kb
Host smart-20240ceb-e833-4f58-9873-fe055185f3bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141697556 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_
ctrl_ec_pwr_on_rst.3141697556
Directory /workspace/26.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_edge_detect.2891191090
Short name T142
Test name
Test status
Simulation time 4413592838 ps
CPU time 7.74 seconds
Started Mar 24 01:15:44 PM PDT 24
Finished Mar 24 01:15:53 PM PDT 24
Peak memory 202060 kb
Host smart-a92b106d-be4b-4ed6-b613-83d10303579a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891191090 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ct
rl_edge_detect.2891191090
Directory /workspace/26.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.1367942666
Short name T584
Test name
Test status
Simulation time 2644105180 ps
CPU time 2.17 seconds
Started Mar 24 01:15:44 PM PDT 24
Finished Mar 24 01:15:49 PM PDT 24
Peak memory 201932 kb
Host smart-c3035145-48dd-4780-908b-d16cd6a0072f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367942666 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_flash_wr_prot_out.1367942666
Directory /workspace/26.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.3882389103
Short name T210
Test name
Test status
Simulation time 2449484220 ps
CPU time 6.72 seconds
Started Mar 24 01:15:46 PM PDT 24
Finished Mar 24 01:15:54 PM PDT 24
Peak memory 202068 kb
Host smart-197d667b-9165-445a-bd06-3f8cad9b1233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882389103 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_in_out_inverted.3882389103
Directory /workspace/26.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_access_test.2036119186
Short name T420
Test name
Test status
Simulation time 2024242618 ps
CPU time 6.19 seconds
Started Mar 24 01:15:45 PM PDT 24
Finished Mar 24 01:15:52 PM PDT 24
Peak memory 201912 kb
Host smart-62f6cf53-a244-482b-903e-15999641f9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036119186 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_access_test.2036119186
Directory /workspace/26.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_override_test.2243195290
Short name T755
Test name
Test status
Simulation time 2557108579 ps
CPU time 1.73 seconds
Started Mar 24 01:15:42 PM PDT 24
Finished Mar 24 01:15:44 PM PDT 24
Peak memory 202072 kb
Host smart-f2e81bb7-3914-440e-9c0b-aa6040e2051a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243195290 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_override_test.2243195290
Directory /workspace/26.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_smoke.1102348623
Short name T526
Test name
Test status
Simulation time 2119727111 ps
CPU time 3.19 seconds
Started Mar 24 01:15:46 PM PDT 24
Finished Mar 24 01:15:49 PM PDT 24
Peak memory 201952 kb
Host smart-dd589596-f450-47aa-a4ed-dbadd17e6712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102348623 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_smoke.1102348623
Directory /workspace/26.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all.2540162366
Short name T110
Test name
Test status
Simulation time 106818485866 ps
CPU time 145.09 seconds
Started Mar 24 01:15:41 PM PDT 24
Finished Mar 24 01:18:07 PM PDT 24
Peak memory 202120 kb
Host smart-7d2ab7e1-30e6-4dac-9393-e28691cb054f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540162366 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_s
tress_all.2540162366
Directory /workspace/26.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.556725669
Short name T772
Test name
Test status
Simulation time 1840972792261 ps
CPU time 452.43 seconds
Started Mar 24 01:15:46 PM PDT 24
Finished Mar 24 01:23:19 PM PDT 24
Peak memory 201964 kb
Host smart-3f0fa119-b4f6-4825-bd7c-a2bc35d41c15
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556725669 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_c
trl_ultra_low_pwr.556725669
Directory /workspace/26.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_alert_test.1052528933
Short name T235
Test name
Test status
Simulation time 2109952958 ps
CPU time 1.01 seconds
Started Mar 24 01:15:40 PM PDT 24
Finished Mar 24 01:15:42 PM PDT 24
Peak memory 202020 kb
Host smart-21f3a17c-3b90-4ea4-9b46-1f4be2d41303
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052528933 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_alert_te
st.1052528933
Directory /workspace/27.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.2681769168
Short name T583
Test name
Test status
Simulation time 3488063539 ps
CPU time 8.61 seconds
Started Mar 24 01:15:42 PM PDT 24
Finished Mar 24 01:15:51 PM PDT 24
Peak memory 202116 kb
Host smart-dda6a066-de12-49dc-9e10-0c20035ded41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681769168 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_auto_blk_key_output.2
681769168
Directory /workspace/27.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect.3488545924
Short name T675
Test name
Test status
Simulation time 90987211400 ps
CPU time 57.53 seconds
Started Mar 24 01:15:49 PM PDT 24
Finished Mar 24 01:16:47 PM PDT 24
Peak memory 202188 kb
Host smart-e9009dda-4339-487f-8edd-603e1f675bb2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488545924 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_c
trl_combo_detect.3488545924
Directory /workspace/27.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.580631517
Short name T754
Test name
Test status
Simulation time 3209872647 ps
CPU time 2.77 seconds
Started Mar 24 01:15:46 PM PDT 24
Finished Mar 24 01:15:49 PM PDT 24
Peak memory 202040 kb
Host smart-fac1c839-f724-40fb-91f8-c56ab413acb9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580631517 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_c
trl_ec_pwr_on_rst.580631517
Directory /workspace/27.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_edge_detect.505259783
Short name T179
Test name
Test status
Simulation time 2616903999 ps
CPU time 2.12 seconds
Started Mar 24 01:15:41 PM PDT 24
Finished Mar 24 01:15:43 PM PDT 24
Peak memory 202048 kb
Host smart-8cc7845f-9ce6-4d99-bafb-04a6047d8ded
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505259783 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctr
l_edge_detect.505259783
Directory /workspace/27.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.3750463951
Short name T417
Test name
Test status
Simulation time 2637927860 ps
CPU time 2.27 seconds
Started Mar 24 01:15:44 PM PDT 24
Finished Mar 24 01:15:46 PM PDT 24
Peak memory 202024 kb
Host smart-9e0912b4-47d6-4988-8573-a4773b01f125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750463951 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_flash_wr_prot_out.3750463951
Directory /workspace/27.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.1969963360
Short name T67
Test name
Test status
Simulation time 2451846477 ps
CPU time 5.87 seconds
Started Mar 24 01:15:43 PM PDT 24
Finished Mar 24 01:15:49 PM PDT 24
Peak memory 202052 kb
Host smart-1d894051-07b9-41b3-aa3c-665ca90b9491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969963360 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_in_out_inverted.1969963360
Directory /workspace/27.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_access_test.1017132217
Short name T617
Test name
Test status
Simulation time 2049924739 ps
CPU time 3.68 seconds
Started Mar 24 01:15:47 PM PDT 24
Finished Mar 24 01:15:51 PM PDT 24
Peak memory 201912 kb
Host smart-1e90328b-e729-43ad-ad8b-1916686dfc73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017132217 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_access_test.1017132217
Directory /workspace/27.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_override_test.4021745445
Short name T71
Test name
Test status
Simulation time 2510468458 ps
CPU time 7.25 seconds
Started Mar 24 01:15:46 PM PDT 24
Finished Mar 24 01:15:53 PM PDT 24
Peak memory 202092 kb
Host smart-fe84ab43-fdf6-43dc-96e9-1177e7e75764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021745445 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_override_test.4021745445
Directory /workspace/27.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_smoke.2137328973
Short name T443
Test name
Test status
Simulation time 2192679322 ps
CPU time 0.93 seconds
Started Mar 24 01:15:47 PM PDT 24
Finished Mar 24 01:15:48 PM PDT 24
Peak memory 201916 kb
Host smart-52a49d74-bd5e-488c-9908-6ef8c9f539b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137328973 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_smoke.2137328973
Directory /workspace/27.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all.1227318698
Short name T278
Test name
Test status
Simulation time 10092585640 ps
CPU time 7.23 seconds
Started Mar 24 01:15:45 PM PDT 24
Finished Mar 24 01:15:52 PM PDT 24
Peak memory 202140 kb
Host smart-c84aa4b6-b59e-41c1-b69f-c39663196039
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227318698 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_s
tress_all.1227318698
Directory /workspace/27.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.3810618196
Short name T455
Test name
Test status
Simulation time 7957418757 ps
CPU time 7.7 seconds
Started Mar 24 01:15:45 PM PDT 24
Finished Mar 24 01:15:53 PM PDT 24
Peak memory 202084 kb
Host smart-acd6ed9c-d65f-424d-b4a8-29a83e11f3ac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810618196 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_
ctrl_ultra_low_pwr.3810618196
Directory /workspace/27.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_alert_test.332476975
Short name T742
Test name
Test status
Simulation time 2010903543 ps
CPU time 6.02 seconds
Started Mar 24 01:15:44 PM PDT 24
Finished Mar 24 01:15:50 PM PDT 24
Peak memory 202072 kb
Host smart-3d0ac22d-07ad-4b5b-931f-46dc2f0a3c33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332476975 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_alert_tes
t.332476975
Directory /workspace/28.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect.955179042
Short name T337
Test name
Test status
Simulation time 127711952745 ps
CPU time 150.85 seconds
Started Mar 24 01:15:45 PM PDT 24
Finished Mar 24 01:18:18 PM PDT 24
Peak memory 202264 kb
Host smart-e2c62784-6a09-4dc3-a580-a0d54003df1f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955179042 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ct
rl_combo_detect.955179042
Directory /workspace/28.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.192412294
Short name T128
Test name
Test status
Simulation time 24349961585 ps
CPU time 19.41 seconds
Started Mar 24 01:15:44 PM PDT 24
Finished Mar 24 01:16:04 PM PDT 24
Peak memory 202308 kb
Host smart-7d01f719-e74c-46d7-8478-ebdeaf9854b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192412294 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect_wi
th_pre_cond.192412294
Directory /workspace/28.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.3232345198
Short name T131
Test name
Test status
Simulation time 2742121744 ps
CPU time 7.59 seconds
Started Mar 24 01:15:43 PM PDT 24
Finished Mar 24 01:15:51 PM PDT 24
Peak memory 202060 kb
Host smart-494be5ae-2433-4842-bd92-5e65d70f63cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232345198 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_
ctrl_ec_pwr_on_rst.3232345198
Directory /workspace/28.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_edge_detect.4062326685
Short name T422
Test name
Test status
Simulation time 336629008065 ps
CPU time 900.21 seconds
Started Mar 24 01:15:45 PM PDT 24
Finished Mar 24 01:30:47 PM PDT 24
Peak memory 202084 kb
Host smart-91c27059-5662-4c65-b63c-c3583eea1bb5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062326685 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ct
rl_edge_detect.4062326685
Directory /workspace/28.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.2910395265
Short name T519
Test name
Test status
Simulation time 2610516831 ps
CPU time 7.54 seconds
Started Mar 24 01:15:50 PM PDT 24
Finished Mar 24 01:15:58 PM PDT 24
Peak memory 201996 kb
Host smart-c1cd93c3-07f1-40bb-8695-8e889a553fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910395265 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_flash_wr_prot_out.2910395265
Directory /workspace/28.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_in_out_inverted.2386528313
Short name T437
Test name
Test status
Simulation time 2461287296 ps
CPU time 6.81 seconds
Started Mar 24 01:15:50 PM PDT 24
Finished Mar 24 01:15:57 PM PDT 24
Peak memory 202016 kb
Host smart-6f435999-8549-4e6e-96de-6479d45b85da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386528313 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_in_out_inverted.2386528313
Directory /workspace/28.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_access_test.726402096
Short name T394
Test name
Test status
Simulation time 2138601828 ps
CPU time 2.05 seconds
Started Mar 24 01:15:44 PM PDT 24
Finished Mar 24 01:15:47 PM PDT 24
Peak memory 201948 kb
Host smart-a909e494-5b37-4a4d-bb09-35def1db1f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726402096 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_access_test.726402096
Directory /workspace/28.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_override_test.808736490
Short name T496
Test name
Test status
Simulation time 2518820030 ps
CPU time 3.76 seconds
Started Mar 24 01:15:47 PM PDT 24
Finished Mar 24 01:15:51 PM PDT 24
Peak memory 202048 kb
Host smart-6085faa6-ecea-4b72-9ceb-d2acf9833f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808736490 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_override_test.808736490
Directory /workspace/28.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_smoke.2816899784
Short name T560
Test name
Test status
Simulation time 2108609582 ps
CPU time 5.96 seconds
Started Mar 24 01:15:46 PM PDT 24
Finished Mar 24 01:15:52 PM PDT 24
Peak memory 201936 kb
Host smart-d0bddd99-c88b-41a9-9b97-7f4a0b8f19d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816899784 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_smoke.2816899784
Directory /workspace/28.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all.3267359245
Short name T458
Test name
Test status
Simulation time 14558025245 ps
CPU time 40.37 seconds
Started Mar 24 01:15:43 PM PDT 24
Finished Mar 24 01:16:24 PM PDT 24
Peak memory 202100 kb
Host smart-a9582597-15cf-4ede-9bfd-0b71defa9912
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267359245 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_s
tress_all.3267359245
Directory /workspace/28.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ultra_low_pwr.987827896
Short name T516
Test name
Test status
Simulation time 10248537409 ps
CPU time 9.29 seconds
Started Mar 24 01:15:43 PM PDT 24
Finished Mar 24 01:15:52 PM PDT 24
Peak memory 202020 kb
Host smart-fe6441a1-91e0-478d-9c56-f5eb252961e0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987827896 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_c
trl_ultra_low_pwr.987827896
Directory /workspace/28.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_alert_test.2425404269
Short name T434
Test name
Test status
Simulation time 2026155572 ps
CPU time 2.07 seconds
Started Mar 24 01:15:52 PM PDT 24
Finished Mar 24 01:15:54 PM PDT 24
Peak memory 202012 kb
Host smart-cc4d643a-f9c1-456c-83c4-fe00fd232002
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425404269 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_alert_te
st.2425404269
Directory /workspace/29.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.1853480395
Short name T462
Test name
Test status
Simulation time 3652350070 ps
CPU time 2.95 seconds
Started Mar 24 01:15:46 PM PDT 24
Finished Mar 24 01:15:49 PM PDT 24
Peak memory 202120 kb
Host smart-2853a2c0-0058-4db3-9c10-4d8eec32b183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853480395 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_auto_blk_key_output.1
853480395
Directory /workspace/29.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect.3610390960
Short name T108
Test name
Test status
Simulation time 130873098668 ps
CPU time 84.87 seconds
Started Mar 24 01:15:52 PM PDT 24
Finished Mar 24 01:17:17 PM PDT 24
Peak memory 202288 kb
Host smart-dd5131ef-2f86-4630-9490-9a9c7ce20b07
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610390960 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_c
trl_combo_detect.3610390960
Directory /workspace/29.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.3262805893
Short name T719
Test name
Test status
Simulation time 22331668670 ps
CPU time 55.94 seconds
Started Mar 24 01:15:54 PM PDT 24
Finished Mar 24 01:16:50 PM PDT 24
Peak memory 202312 kb
Host smart-5bdad888-4b42-4447-89c1-ccbf2e4e04f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262805893 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect_w
ith_pre_cond.3262805893
Directory /workspace/29.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.3498529180
Short name T430
Test name
Test status
Simulation time 4267131817 ps
CPU time 2.16 seconds
Started Mar 24 01:15:45 PM PDT 24
Finished Mar 24 01:15:47 PM PDT 24
Peak memory 202004 kb
Host smart-0376266f-2e15-4339-90fc-0393170081e2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498529180 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_
ctrl_ec_pwr_on_rst.3498529180
Directory /workspace/29.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_edge_detect.1616693126
Short name T11
Test name
Test status
Simulation time 3263612888 ps
CPU time 3.19 seconds
Started Mar 24 01:15:55 PM PDT 24
Finished Mar 24 01:15:58 PM PDT 24
Peak memory 202044 kb
Host smart-662eb607-b561-4910-a78d-d02d2d3ba1aa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616693126 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ct
rl_edge_detect.1616693126
Directory /workspace/29.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.1343710940
Short name T449
Test name
Test status
Simulation time 2610515974 ps
CPU time 8.1 seconds
Started Mar 24 01:15:43 PM PDT 24
Finished Mar 24 01:15:52 PM PDT 24
Peak memory 201952 kb
Host smart-5a3a3340-7728-44c2-b40c-93e1d88544bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343710940 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_flash_wr_prot_out.1343710940
Directory /workspace/29.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_in_out_inverted.2664521584
Short name T587
Test name
Test status
Simulation time 2461914687 ps
CPU time 2.46 seconds
Started Mar 24 01:15:48 PM PDT 24
Finished Mar 24 01:15:50 PM PDT 24
Peak memory 202036 kb
Host smart-0c0c9d12-84a6-4514-8f94-152c9e4b6cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664521584 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_in_out_inverted.2664521584
Directory /workspace/29.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_access_test.3195343261
Short name T113
Test name
Test status
Simulation time 2222387940 ps
CPU time 3.52 seconds
Started Mar 24 01:15:50 PM PDT 24
Finished Mar 24 01:15:54 PM PDT 24
Peak memory 201940 kb
Host smart-82f928e7-5a1c-44ae-b292-d51aa827065e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195343261 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_access_test.3195343261
Directory /workspace/29.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_override_test.2520148262
Short name T681
Test name
Test status
Simulation time 2568824031 ps
CPU time 1.26 seconds
Started Mar 24 01:15:43 PM PDT 24
Finished Mar 24 01:15:44 PM PDT 24
Peak memory 202052 kb
Host smart-5d8e9578-2cd0-4a3b-882e-f7f57d47f4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520148262 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_override_test.2520148262
Directory /workspace/29.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_smoke.4073143114
Short name T230
Test name
Test status
Simulation time 2120648237 ps
CPU time 3.36 seconds
Started Mar 24 01:15:49 PM PDT 24
Finished Mar 24 01:15:53 PM PDT 24
Peak memory 201868 kb
Host smart-1263a562-2877-42f1-8621-8b99a9af93ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073143114 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_smoke.4073143114
Directory /workspace/29.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all.1347450754
Short name T657
Test name
Test status
Simulation time 137936185236 ps
CPU time 103.54 seconds
Started Mar 24 01:15:52 PM PDT 24
Finished Mar 24 01:17:36 PM PDT 24
Peak memory 202204 kb
Host smart-e79be5df-a7d7-44c3-b352-d459677385a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347450754 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_s
tress_all.1347450754
Directory /workspace/29.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ultra_low_pwr.2752297412
Short name T622
Test name
Test status
Simulation time 1994374447495 ps
CPU time 102.24 seconds
Started Mar 24 01:15:53 PM PDT 24
Finished Mar 24 01:17:35 PM PDT 24
Peak memory 201976 kb
Host smart-660554df-4721-458f-a426-23c84814c286
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752297412 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_
ctrl_ultra_low_pwr.2752297412
Directory /workspace/29.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_alert_test.3784020913
Short name T606
Test name
Test status
Simulation time 2015264009 ps
CPU time 3.32 seconds
Started Mar 24 01:14:54 PM PDT 24
Finished Mar 24 01:14:58 PM PDT 24
Peak memory 202092 kb
Host smart-e98b2413-639d-42e9-bcce-523cc5905665
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784020913 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_alert_tes
t.3784020913
Directory /workspace/3.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.3619007154
Short name T626
Test name
Test status
Simulation time 3829081790 ps
CPU time 3.7 seconds
Started Mar 24 01:14:49 PM PDT 24
Finished Mar 24 01:14:54 PM PDT 24
Peak memory 202132 kb
Host smart-18342ef0-45ba-4ed6-ac81-92c5d9fe5cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619007154 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_auto_blk_key_output.3619007154
Directory /workspace/3.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.2588381017
Short name T47
Test name
Test status
Simulation time 2214828133 ps
CPU time 1.28 seconds
Started Mar 24 01:14:48 PM PDT 24
Finished Mar 24 01:14:50 PM PDT 24
Peak memory 202008 kb
Host smart-4edbcc4d-1113-40a2-b219-1f9bddb99c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588381017 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst.2588381017
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2558393343
Short name T466
Test name
Test status
Simulation time 2522634262 ps
CPU time 6.98 seconds
Started Mar 24 01:14:48 PM PDT 24
Finished Mar 24 01:14:55 PM PDT 24
Peak memory 202016 kb
Host smart-2e3c5609-2366-4f60-976a-7fca58df7baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558393343 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.2558393343
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.2119277404
Short name T175
Test name
Test status
Simulation time 25581015974 ps
CPU time 69.25 seconds
Started Mar 24 01:14:53 PM PDT 24
Finished Mar 24 01:16:03 PM PDT 24
Peak memory 202296 kb
Host smart-03a90cba-94e9-4d82-9d2d-72d225700656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119277404 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_wi
th_pre_cond.2119277404
Directory /workspace/3.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.1750935928
Short name T306
Test name
Test status
Simulation time 3186013433 ps
CPU time 8.8 seconds
Started Mar 24 01:14:49 PM PDT 24
Finished Mar 24 01:14:58 PM PDT 24
Peak memory 202040 kb
Host smart-003cd37f-f2d4-4e7f-8c6d-0e8b1b6c8bdf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750935928 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_ec_pwr_on_rst.1750935928
Directory /workspace/3.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_edge_detect.1135016316
Short name T621
Test name
Test status
Simulation time 2813985451 ps
CPU time 1.55 seconds
Started Mar 24 01:14:48 PM PDT 24
Finished Mar 24 01:14:50 PM PDT 24
Peak memory 202044 kb
Host smart-22e297ea-d1a2-4abd-a7e9-6d88cf623636
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135016316 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctr
l_edge_detect.1135016316
Directory /workspace/3.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.1999712237
Short name T768
Test name
Test status
Simulation time 2649499171 ps
CPU time 1.91 seconds
Started Mar 24 01:15:00 PM PDT 24
Finished Mar 24 01:15:02 PM PDT 24
Peak memory 202068 kb
Host smart-a6b0c7e2-be6b-448b-a83e-d135b57e6d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999712237 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_flash_wr_prot_out.1999712237
Directory /workspace/3.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.3011984306
Short name T695
Test name
Test status
Simulation time 2471031306 ps
CPU time 4.21 seconds
Started Mar 24 01:14:50 PM PDT 24
Finished Mar 24 01:14:55 PM PDT 24
Peak memory 202000 kb
Host smart-6418cd18-514a-4954-8b54-b269a1457a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011984306 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_in_out_inverted.3011984306
Directory /workspace/3.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_access_test.3314134455
Short name T188
Test name
Test status
Simulation time 2176626355 ps
CPU time 1.88 seconds
Started Mar 24 01:14:49 PM PDT 24
Finished Mar 24 01:14:52 PM PDT 24
Peak memory 201996 kb
Host smart-bc440ce5-41b2-4e45-98c9-4812527ea54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314134455 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_access_test.3314134455
Directory /workspace/3.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_override_test.2966809909
Short name T544
Test name
Test status
Simulation time 2516374212 ps
CPU time 4.07 seconds
Started Mar 24 01:14:46 PM PDT 24
Finished Mar 24 01:14:50 PM PDT 24
Peak memory 202048 kb
Host smart-0786e687-21e6-4d85-94b3-a5c43f5e6a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966809909 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_override_test.2966809909
Directory /workspace/3.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_sec_cm.2772007502
Short name T223
Test name
Test status
Simulation time 22045725994 ps
CPU time 14.99 seconds
Started Mar 24 01:14:59 PM PDT 24
Finished Mar 24 01:15:14 PM PDT 24
Peak memory 221824 kb
Host smart-a28a2278-b57a-4ad1-b50a-fd6069ea13bf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772007502 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_sec_cm.2772007502
Directory /workspace/3.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_smoke.2475643217
Short name T282
Test name
Test status
Simulation time 2115048206 ps
CPU time 5.91 seconds
Started Mar 24 01:14:55 PM PDT 24
Finished Mar 24 01:15:01 PM PDT 24
Peak memory 201916 kb
Host smart-d8ea7e68-79d1-408c-b806-a128396dc9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475643217 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_smoke.2475643217
Directory /workspace/3.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all.2213272147
Short name T42
Test name
Test status
Simulation time 9567655012 ps
CPU time 23.96 seconds
Started Mar 24 01:14:54 PM PDT 24
Finished Mar 24 01:15:19 PM PDT 24
Peak memory 202052 kb
Host smart-a5d8a8e5-aada-4ebf-b0cc-252edefb1041
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213272147 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_st
ress_all.2213272147
Directory /workspace/3.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.3347434579
Short name T254
Test name
Test status
Simulation time 80503106225 ps
CPU time 70.76 seconds
Started Mar 24 01:14:53 PM PDT 24
Finished Mar 24 01:16:04 PM PDT 24
Peak memory 210700 kb
Host smart-1763d156-18be-4703-abf3-6fd69b8f0c6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347434579 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_stress_all_with_rand_reset.3347434579
Directory /workspace/3.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.4161710957
Short name T74
Test name
Test status
Simulation time 7071840420 ps
CPU time 6.65 seconds
Started Mar 24 01:14:47 PM PDT 24
Finished Mar 24 01:14:54 PM PDT 24
Peak memory 202036 kb
Host smart-f59e8a07-2b39-4ae6-80ba-4ba0353f4c3d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161710957 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_ultra_low_pwr.4161710957
Directory /workspace/3.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_alert_test.3326745203
Short name T495
Test name
Test status
Simulation time 2110572833 ps
CPU time 1.53 seconds
Started Mar 24 01:15:53 PM PDT 24
Finished Mar 24 01:15:54 PM PDT 24
Peak memory 202056 kb
Host smart-9b2cf599-21cd-4bc3-9618-65e7076d6d67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326745203 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_alert_te
st.3326745203
Directory /workspace/30.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.690618061
Short name T50
Test name
Test status
Simulation time 2978350522 ps
CPU time 2.39 seconds
Started Mar 24 01:15:54 PM PDT 24
Finished Mar 24 01:15:57 PM PDT 24
Peak memory 202128 kb
Host smart-3e366511-728d-4e7a-8864-ed05af46e5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690618061 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_auto_blk_key_output.690618061
Directory /workspace/30.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect.3507368938
Short name T336
Test name
Test status
Simulation time 115924668341 ps
CPU time 303.06 seconds
Started Mar 24 01:15:56 PM PDT 24
Finished Mar 24 01:21:00 PM PDT 24
Peak memory 202260 kb
Host smart-8d062398-86be-4581-aab5-b7ed1a85033a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507368938 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_c
trl_combo_detect.3507368938
Directory /workspace/30.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.1940436004
Short name T364
Test name
Test status
Simulation time 199212181589 ps
CPU time 536.68 seconds
Started Mar 24 01:15:50 PM PDT 24
Finished Mar 24 01:24:46 PM PDT 24
Peak memory 202296 kb
Host smart-e7cd9797-92fc-4280-ab98-bbd8b01718e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940436004 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect_w
ith_pre_cond.1940436004
Directory /workspace/30.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.2536767776
Short name T608
Test name
Test status
Simulation time 3033254556 ps
CPU time 4.56 seconds
Started Mar 24 01:15:52 PM PDT 24
Finished Mar 24 01:15:57 PM PDT 24
Peak memory 202048 kb
Host smart-fd57fc90-f1c2-419e-b5fb-51ec0b6ba173
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536767776 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_
ctrl_ec_pwr_on_rst.2536767776
Directory /workspace/30.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_edge_detect.1908666961
Short name T160
Test name
Test status
Simulation time 2914724977 ps
CPU time 8.37 seconds
Started Mar 24 01:15:57 PM PDT 24
Finished Mar 24 01:16:06 PM PDT 24
Peak memory 202032 kb
Host smart-b36ef7a0-74dd-479d-8ed6-b475c1505f77
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908666961 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ct
rl_edge_detect.1908666961
Directory /workspace/30.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.1444775819
Short name T423
Test name
Test status
Simulation time 2614098341 ps
CPU time 4.32 seconds
Started Mar 24 01:15:52 PM PDT 24
Finished Mar 24 01:15:57 PM PDT 24
Peak memory 202052 kb
Host smart-51dc3d7a-9f21-4898-a580-7c3344798fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444775819 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_flash_wr_prot_out.1444775819
Directory /workspace/30.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_in_out_inverted.2187275722
Short name T274
Test name
Test status
Simulation time 2488855551 ps
CPU time 2.18 seconds
Started Mar 24 01:15:55 PM PDT 24
Finished Mar 24 01:15:57 PM PDT 24
Peak memory 202024 kb
Host smart-06c2f426-2f99-4901-af68-3d924e4c1ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187275722 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_in_out_inverted.2187275722
Directory /workspace/30.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_access_test.3910586903
Short name T280
Test name
Test status
Simulation time 2025963073 ps
CPU time 6.26 seconds
Started Mar 24 01:15:51 PM PDT 24
Finished Mar 24 01:15:58 PM PDT 24
Peak memory 201912 kb
Host smart-5e0ae00f-58ec-48bc-867c-a69b7c308790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910586903 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_access_test.3910586903
Directory /workspace/30.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_override_test.1793320434
Short name T174
Test name
Test status
Simulation time 2510157340 ps
CPU time 7.18 seconds
Started Mar 24 01:15:51 PM PDT 24
Finished Mar 24 01:15:59 PM PDT 24
Peak memory 202080 kb
Host smart-e3ecd999-c420-4004-8cac-779e9023ac89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793320434 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_override_test.1793320434
Directory /workspace/30.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_smoke.1768493017
Short name T658
Test name
Test status
Simulation time 2118957575 ps
CPU time 3.46 seconds
Started Mar 24 01:15:52 PM PDT 24
Finished Mar 24 01:15:56 PM PDT 24
Peak memory 201948 kb
Host smart-a16043c0-3671-48e3-9a9a-79db1be4b615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768493017 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_smoke.1768493017
Directory /workspace/30.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all.3843740679
Short name T661
Test name
Test status
Simulation time 11228661828 ps
CPU time 23.26 seconds
Started Mar 24 01:15:55 PM PDT 24
Finished Mar 24 01:16:19 PM PDT 24
Peak memory 202064 kb
Host smart-6e796038-0654-4c22-a858-cd60d073567b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843740679 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_s
tress_all.3843740679
Directory /workspace/30.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.670199920
Short name T133
Test name
Test status
Simulation time 8535088006 ps
CPU time 2.71 seconds
Started Mar 24 01:15:51 PM PDT 24
Finished Mar 24 01:15:54 PM PDT 24
Peak memory 202040 kb
Host smart-ca475dfe-30d5-4bd4-a445-e19ebfb58120
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670199920 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_c
trl_ultra_low_pwr.670199920
Directory /workspace/30.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_alert_test.4014367247
Short name T485
Test name
Test status
Simulation time 2029222036 ps
CPU time 1.84 seconds
Started Mar 24 01:15:55 PM PDT 24
Finished Mar 24 01:15:57 PM PDT 24
Peak memory 202100 kb
Host smart-54066807-936c-45a1-bb9a-bed7516ec29b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014367247 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_alert_te
st.4014367247
Directory /workspace/31.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_auto_blk_key_output.59016573
Short name T781
Test name
Test status
Simulation time 5930987053 ps
CPU time 15.91 seconds
Started Mar 24 01:15:53 PM PDT 24
Finished Mar 24 01:16:09 PM PDT 24
Peak memory 202060 kb
Host smart-43bf6b6e-8a11-40f4-849f-bd05857f47ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59016573 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_auto_blk_key_output.59016573
Directory /workspace/31.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect.39227809
Short name T166
Test name
Test status
Simulation time 164346772658 ps
CPU time 413.48 seconds
Started Mar 24 01:15:55 PM PDT 24
Finished Mar 24 01:22:49 PM PDT 24
Peak memory 202308 kb
Host smart-1f0b58a8-5c53-4206-9dd2-baf8acf8f4dc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39227809 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctr
l_combo_detect.39227809
Directory /workspace/31.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.3716837343
Short name T602
Test name
Test status
Simulation time 51762925668 ps
CPU time 64.86 seconds
Started Mar 24 01:15:56 PM PDT 24
Finished Mar 24 01:17:01 PM PDT 24
Peak memory 202288 kb
Host smart-10e56ab0-e068-4e8d-88fc-fc4a476a5c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716837343 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect_w
ith_pre_cond.3716837343
Directory /workspace/31.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.2686105720
Short name T404
Test name
Test status
Simulation time 3659947817 ps
CPU time 4.67 seconds
Started Mar 24 01:15:52 PM PDT 24
Finished Mar 24 01:15:57 PM PDT 24
Peak memory 202012 kb
Host smart-f2c9058d-475a-4bcf-b195-65003a90b5ae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686105720 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_
ctrl_ec_pwr_on_rst.2686105720
Directory /workspace/31.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_edge_detect.3342520432
Short name T159
Test name
Test status
Simulation time 4211978807 ps
CPU time 2.47 seconds
Started Mar 24 01:15:53 PM PDT 24
Finished Mar 24 01:15:55 PM PDT 24
Peak memory 202060 kb
Host smart-c3021d70-fe34-4e61-b099-09acf990d044
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342520432 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ct
rl_edge_detect.3342520432
Directory /workspace/31.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.3936653873
Short name T483
Test name
Test status
Simulation time 2633427836 ps
CPU time 2.4 seconds
Started Mar 24 01:15:52 PM PDT 24
Finished Mar 24 01:15:55 PM PDT 24
Peak memory 202036 kb
Host smart-d85ce31d-1e43-4e1f-9456-dc7244be5afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936653873 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_flash_wr_prot_out.3936653873
Directory /workspace/31.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.3839801487
Short name T294
Test name
Test status
Simulation time 2484556657 ps
CPU time 2.7 seconds
Started Mar 24 01:15:56 PM PDT 24
Finished Mar 24 01:15:59 PM PDT 24
Peak memory 202072 kb
Host smart-bb533629-d7c4-4224-b81c-e0b83c5cf159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839801487 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_in_out_inverted.3839801487
Directory /workspace/31.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_access_test.1907153326
Short name T749
Test name
Test status
Simulation time 2147591272 ps
CPU time 6.11 seconds
Started Mar 24 01:15:57 PM PDT 24
Finished Mar 24 01:16:03 PM PDT 24
Peak memory 202048 kb
Host smart-30ead27b-c87a-4dc7-beaa-54b6205edf07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907153326 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_access_test.1907153326
Directory /workspace/31.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_override_test.2940209564
Short name T234
Test name
Test status
Simulation time 2515175919 ps
CPU time 7.07 seconds
Started Mar 24 01:15:50 PM PDT 24
Finished Mar 24 01:15:57 PM PDT 24
Peak memory 202096 kb
Host smart-a146c047-db21-41f4-8b35-0d191cd3808d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940209564 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_override_test.2940209564
Directory /workspace/31.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_smoke.3419318696
Short name T546
Test name
Test status
Simulation time 2195325414 ps
CPU time 1.01 seconds
Started Mar 24 01:15:56 PM PDT 24
Finished Mar 24 01:15:57 PM PDT 24
Peak memory 202020 kb
Host smart-645be501-248e-4ed4-86da-adae0a868a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419318696 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_smoke.3419318696
Directory /workspace/31.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all.1117915491
Short name T700
Test name
Test status
Simulation time 15953293792 ps
CPU time 44.3 seconds
Started Mar 24 01:15:56 PM PDT 24
Finished Mar 24 01:16:45 PM PDT 24
Peak memory 202012 kb
Host smart-6ef19b04-c7f3-40b0-a7b9-2c14bdc7f017
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117915491 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_s
tress_all.1117915491
Directory /workspace/31.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_alert_test.133897231
Short name T611
Test name
Test status
Simulation time 2014321941 ps
CPU time 6.11 seconds
Started Mar 24 01:15:56 PM PDT 24
Finished Mar 24 01:16:02 PM PDT 24
Peak memory 202308 kb
Host smart-721bfc7c-094f-401c-9d4b-17ecda00944d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133897231 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_alert_tes
t.133897231
Directory /workspace/32.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.204676188
Short name T482
Test name
Test status
Simulation time 3271810745 ps
CPU time 5.02 seconds
Started Mar 24 01:15:57 PM PDT 24
Finished Mar 24 01:16:02 PM PDT 24
Peak memory 202088 kb
Host smart-fcf58a7a-43f1-4704-a43a-8a0b2f1ea50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204676188 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_auto_blk_key_output.204676188
Directory /workspace/32.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect.2451118515
Short name T8
Test name
Test status
Simulation time 63670772613 ps
CPU time 176.8 seconds
Started Mar 24 01:15:56 PM PDT 24
Finished Mar 24 01:18:53 PM PDT 24
Peak memory 202260 kb
Host smart-58079a1a-1003-40f0-8bb6-19d601800dd7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451118515 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_c
trl_combo_detect.2451118515
Directory /workspace/32.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.3857810402
Short name T32
Test name
Test status
Simulation time 96519370513 ps
CPU time 244.17 seconds
Started Mar 24 01:15:56 PM PDT 24
Finished Mar 24 01:20:01 PM PDT 24
Peak memory 202180 kb
Host smart-65e38192-fca8-4866-84e2-bb64d49f4ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857810402 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect_w
ith_pre_cond.3857810402
Directory /workspace/32.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.1406139745
Short name T498
Test name
Test status
Simulation time 2818759391 ps
CPU time 4.37 seconds
Started Mar 24 01:15:58 PM PDT 24
Finished Mar 24 01:16:02 PM PDT 24
Peak memory 202044 kb
Host smart-e37c0f47-ccfa-47e5-9fca-409aa6871a9b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406139745 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_
ctrl_ec_pwr_on_rst.1406139745
Directory /workspace/32.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_edge_detect.2517982037
Short name T162
Test name
Test status
Simulation time 3046916096 ps
CPU time 2.7 seconds
Started Mar 24 01:16:01 PM PDT 24
Finished Mar 24 01:16:04 PM PDT 24
Peak memory 202004 kb
Host smart-e618fc5a-124d-4d19-802d-9f5b939ae7d6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517982037 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ct
rl_edge_detect.2517982037
Directory /workspace/32.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.379771564
Short name T451
Test name
Test status
Simulation time 2639027944 ps
CPU time 2.17 seconds
Started Mar 24 01:15:54 PM PDT 24
Finished Mar 24 01:15:56 PM PDT 24
Peak memory 202052 kb
Host smart-f09bdc47-f6c1-4f4e-a4db-970f77914546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379771564 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_flash_wr_prot_out.379771564
Directory /workspace/32.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_in_out_inverted.3030319387
Short name T413
Test name
Test status
Simulation time 2461805842 ps
CPU time 7.37 seconds
Started Mar 24 01:15:55 PM PDT 24
Finished Mar 24 01:16:03 PM PDT 24
Peak memory 202048 kb
Host smart-7fbee46e-5564-4805-8a61-fc1ab1367f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030319387 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_in_out_inverted.3030319387
Directory /workspace/32.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_access_test.3047015461
Short name T571
Test name
Test status
Simulation time 2156986301 ps
CPU time 2.13 seconds
Started Mar 24 01:16:04 PM PDT 24
Finished Mar 24 01:16:07 PM PDT 24
Peak memory 201956 kb
Host smart-6c99105f-cf85-4e77-b16b-74163a0f390c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047015461 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_access_test.3047015461
Directory /workspace/32.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_override_test.1924286389
Short name T523
Test name
Test status
Simulation time 2535655258 ps
CPU time 2.37 seconds
Started Mar 24 01:15:55 PM PDT 24
Finished Mar 24 01:15:58 PM PDT 24
Peak memory 202080 kb
Host smart-8aa78c1f-5f97-440a-9fe7-27d781bf3528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924286389 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_override_test.1924286389
Directory /workspace/32.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_smoke.1330762024
Short name T610
Test name
Test status
Simulation time 2112154277 ps
CPU time 6.13 seconds
Started Mar 24 01:15:57 PM PDT 24
Finished Mar 24 01:16:03 PM PDT 24
Peak memory 201884 kb
Host smart-f32bc90e-fae5-4cd1-8d5a-9cb17692d1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330762024 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_smoke.1330762024
Directory /workspace/32.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all.2360629710
Short name T663
Test name
Test status
Simulation time 13253658402 ps
CPU time 35.17 seconds
Started Mar 24 01:15:53 PM PDT 24
Finished Mar 24 01:16:29 PM PDT 24
Peak memory 202124 kb
Host smart-ae67ed48-0fd6-4fd6-b0f7-08481ac5c75c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360629710 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_s
tress_all.2360629710
Directory /workspace/32.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.861231101
Short name T730
Test name
Test status
Simulation time 62760705098 ps
CPU time 38.42 seconds
Started Mar 24 01:15:57 PM PDT 24
Finished Mar 24 01:16:36 PM PDT 24
Peak memory 218756 kb
Host smart-d7c0151f-6757-4620-ba9f-7ca90af1dafb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861231101 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_stress_all_with_rand_reset.861231101
Directory /workspace/32.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ultra_low_pwr.2792258424
Short name T390
Test name
Test status
Simulation time 554631760222 ps
CPU time 84.21 seconds
Started Mar 24 01:15:56 PM PDT 24
Finished Mar 24 01:17:21 PM PDT 24
Peak memory 201968 kb
Host smart-03ce7df6-55c1-42c3-9ae3-a5998b7467db
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792258424 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_
ctrl_ultra_low_pwr.2792258424
Directory /workspace/32.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_alert_test.2551417978
Short name T448
Test name
Test status
Simulation time 2047804806 ps
CPU time 1.9 seconds
Started Mar 24 01:16:00 PM PDT 24
Finished Mar 24 01:16:02 PM PDT 24
Peak memory 202064 kb
Host smart-8c3b368e-aed8-4936-9631-213225f6ba58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551417978 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_alert_te
st.2551417978
Directory /workspace/33.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.3697323121
Short name T527
Test name
Test status
Simulation time 2894174696 ps
CPU time 7.9 seconds
Started Mar 24 01:15:59 PM PDT 24
Finished Mar 24 01:16:07 PM PDT 24
Peak memory 202112 kb
Host smart-2f6462d7-8d65-4ea5-b40a-196d5f37a6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697323121 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_auto_blk_key_output.3
697323121
Directory /workspace/33.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect.1993050192
Short name T97
Test name
Test status
Simulation time 169437283038 ps
CPU time 475.98 seconds
Started Mar 24 01:15:55 PM PDT 24
Finished Mar 24 01:23:51 PM PDT 24
Peak memory 202272 kb
Host smart-73bf32a1-06e9-4556-b2d7-b346797f3f20
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993050192 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_c
trl_combo_detect.1993050192
Directory /workspace/33.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.962663096
Short name T309
Test name
Test status
Simulation time 189829052331 ps
CPU time 260.75 seconds
Started Mar 24 01:16:14 PM PDT 24
Finished Mar 24 01:20:35 PM PDT 24
Peak memory 202272 kb
Host smart-2c3e5fb3-38a1-4aec-9033-95ed71c6725e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962663096 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect_wi
th_pre_cond.962663096
Directory /workspace/33.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.1154387054
Short name T494
Test name
Test status
Simulation time 2752348009 ps
CPU time 1.28 seconds
Started Mar 24 01:15:58 PM PDT 24
Finished Mar 24 01:16:00 PM PDT 24
Peak memory 202032 kb
Host smart-2cad6bb3-7683-491c-9833-3060cc11b801
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154387054 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_
ctrl_ec_pwr_on_rst.1154387054
Directory /workspace/33.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_edge_detect.3267299603
Short name T688
Test name
Test status
Simulation time 3225803893 ps
CPU time 2.15 seconds
Started Mar 24 01:16:24 PM PDT 24
Finished Mar 24 01:16:26 PM PDT 24
Peak memory 201940 kb
Host smart-7ed6415b-ed35-4fcb-ade7-1c74413f81e9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267299603 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ct
rl_edge_detect.3267299603
Directory /workspace/33.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.3125144654
Short name T450
Test name
Test status
Simulation time 2615055837 ps
CPU time 7.09 seconds
Started Mar 24 01:15:55 PM PDT 24
Finished Mar 24 01:16:03 PM PDT 24
Peak memory 201960 kb
Host smart-d03badd7-63da-4f2c-82e2-ee50bfebec69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125144654 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_flash_wr_prot_out.3125144654
Directory /workspace/33.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.1827641445
Short name T604
Test name
Test status
Simulation time 2462889535 ps
CPU time 2.29 seconds
Started Mar 24 01:15:54 PM PDT 24
Finished Mar 24 01:15:57 PM PDT 24
Peak memory 202056 kb
Host smart-a1b316fe-5597-4195-af41-d67e53afc174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827641445 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_in_out_inverted.1827641445
Directory /workspace/33.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_access_test.895847280
Short name T627
Test name
Test status
Simulation time 2120374615 ps
CPU time 5.89 seconds
Started Mar 24 01:15:57 PM PDT 24
Finished Mar 24 01:16:03 PM PDT 24
Peak memory 202180 kb
Host smart-64aa3482-6966-4a55-84c7-82fdd76a1f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895847280 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_access_test.895847280
Directory /workspace/33.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_override_test.2177007639
Short name T298
Test name
Test status
Simulation time 2513994721 ps
CPU time 7.33 seconds
Started Mar 24 01:15:55 PM PDT 24
Finished Mar 24 01:16:02 PM PDT 24
Peak memory 202048 kb
Host smart-bc019b22-357f-4b9d-9371-321363bf72c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177007639 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_override_test.2177007639
Directory /workspace/33.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_smoke.1010016999
Short name T428
Test name
Test status
Simulation time 2145493270 ps
CPU time 1.19 seconds
Started Mar 24 01:15:57 PM PDT 24
Finished Mar 24 01:15:58 PM PDT 24
Peak memory 201888 kb
Host smart-cc863ac4-ad68-4b96-8c8d-7c3818e5ba27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010016999 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_smoke.1010016999
Directory /workspace/33.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all.1236919332
Short name T181
Test name
Test status
Simulation time 14519605173 ps
CPU time 7.61 seconds
Started Mar 24 01:16:00 PM PDT 24
Finished Mar 24 01:16:08 PM PDT 24
Peak memory 202044 kb
Host smart-42c65384-213b-4ed3-bbcd-fae94ed061f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236919332 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_s
tress_all.1236919332
Directory /workspace/33.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ultra_low_pwr.2220724881
Short name T117
Test name
Test status
Simulation time 3147162681719 ps
CPU time 565.84 seconds
Started Mar 24 01:15:56 PM PDT 24
Finished Mar 24 01:25:22 PM PDT 24
Peak memory 202040 kb
Host smart-6a137670-6c9b-45b4-8daa-2388f98fde1e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220724881 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_
ctrl_ultra_low_pwr.2220724881
Directory /workspace/33.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_alert_test.571678287
Short name T595
Test name
Test status
Simulation time 2182316815 ps
CPU time 0.94 seconds
Started Mar 24 01:16:04 PM PDT 24
Finished Mar 24 01:16:06 PM PDT 24
Peak memory 202180 kb
Host smart-ffacfd78-f8b2-42d3-a80d-a355732ce77e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571678287 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_alert_tes
t.571678287
Directory /workspace/34.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.2353615543
Short name T618
Test name
Test status
Simulation time 3026642870 ps
CPU time 3.08 seconds
Started Mar 24 01:16:14 PM PDT 24
Finished Mar 24 01:16:17 PM PDT 24
Peak memory 202092 kb
Host smart-da9a2624-c8fd-4f9f-9af1-ede70981a2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353615543 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_auto_blk_key_output.2
353615543
Directory /workspace/34.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect.2243338121
Short name T330
Test name
Test status
Simulation time 128820919168 ps
CPU time 177.03 seconds
Started Mar 24 01:16:15 PM PDT 24
Finished Mar 24 01:19:12 PM PDT 24
Peak memory 202212 kb
Host smart-ae5de802-5850-42c8-a5f3-df05bf314c5d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243338121 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_c
trl_combo_detect.2243338121
Directory /workspace/34.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.20026715
Short name T75
Test name
Test status
Simulation time 32402123674 ps
CPU time 88.46 seconds
Started Mar 24 01:16:03 PM PDT 24
Finished Mar 24 01:17:33 PM PDT 24
Peak memory 202260 kb
Host smart-00a83544-7f21-40b9-ac5c-d8862cf6345d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20026715 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect_wit
h_pre_cond.20026715
Directory /workspace/34.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.507911881
Short name T164
Test name
Test status
Simulation time 4773827196 ps
CPU time 8.46 seconds
Started Mar 24 01:16:02 PM PDT 24
Finished Mar 24 01:16:10 PM PDT 24
Peak memory 202028 kb
Host smart-facb0e31-f732-4921-863f-36c9974be2fd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507911881 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_c
trl_ec_pwr_on_rst.507911881
Directory /workspace/34.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_edge_detect.1030002626
Short name T706
Test name
Test status
Simulation time 2920816007 ps
CPU time 2.27 seconds
Started Mar 24 01:16:03 PM PDT 24
Finished Mar 24 01:16:06 PM PDT 24
Peak memory 202052 kb
Host smart-523d5bb4-87df-4add-9c23-f5ac50aa6260
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030002626 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ct
rl_edge_detect.1030002626
Directory /workspace/34.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.2755540017
Short name T716
Test name
Test status
Simulation time 2618570008 ps
CPU time 3.55 seconds
Started Mar 24 01:16:03 PM PDT 24
Finished Mar 24 01:16:08 PM PDT 24
Peak memory 202088 kb
Host smart-e356681d-05cd-41ca-8fc4-bd7bc559bd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755540017 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_flash_wr_prot_out.2755540017
Directory /workspace/34.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.2842791662
Short name T615
Test name
Test status
Simulation time 2473483609 ps
CPU time 2.26 seconds
Started Mar 24 01:16:01 PM PDT 24
Finished Mar 24 01:16:04 PM PDT 24
Peak memory 202068 kb
Host smart-1cb0d3c9-967e-4d39-b7e5-48f64d7f8dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842791662 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_in_out_inverted.2842791662
Directory /workspace/34.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_access_test.2471828478
Short name T239
Test name
Test status
Simulation time 2078951245 ps
CPU time 1.97 seconds
Started Mar 24 01:16:12 PM PDT 24
Finished Mar 24 01:16:14 PM PDT 24
Peak memory 201644 kb
Host smart-21f0aa6a-73c2-49a3-824d-4b0afe11f05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471828478 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_access_test.2471828478
Directory /workspace/34.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_override_test.3764663676
Short name T14
Test name
Test status
Simulation time 2509967428 ps
CPU time 7.53 seconds
Started Mar 24 01:16:12 PM PDT 24
Finished Mar 24 01:16:19 PM PDT 24
Peak memory 201884 kb
Host smart-25bedf6e-ac1e-4946-bb07-d6d58433bd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764663676 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_override_test.3764663676
Directory /workspace/34.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_smoke.480856805
Short name T114
Test name
Test status
Simulation time 2109616701 ps
CPU time 5.87 seconds
Started Mar 24 01:16:18 PM PDT 24
Finished Mar 24 01:16:24 PM PDT 24
Peak memory 201888 kb
Host smart-f941c8df-c355-4a7b-8aa1-df5ff497402e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480856805 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_smoke.480856805
Directory /workspace/34.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all.1266132206
Short name T552
Test name
Test status
Simulation time 8295054678 ps
CPU time 20.45 seconds
Started Mar 24 01:16:17 PM PDT 24
Finished Mar 24 01:16:38 PM PDT 24
Peak memory 202012 kb
Host smart-aa6603ec-7e47-4130-9d77-1fc26945308f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266132206 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_s
tress_all.1266132206
Directory /workspace/34.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.954661980
Short name T533
Test name
Test status
Simulation time 49007590526 ps
CPU time 121.96 seconds
Started Mar 24 01:16:12 PM PDT 24
Finished Mar 24 01:18:15 PM PDT 24
Peak memory 210652 kb
Host smart-077f8fa2-d826-4c75-96e6-335fe84d3a02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954661980 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_stress_all_with_rand_reset.954661980
Directory /workspace/34.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.582430373
Short name T574
Test name
Test status
Simulation time 7989678481 ps
CPU time 7.44 seconds
Started Mar 24 01:16:01 PM PDT 24
Finished Mar 24 01:16:09 PM PDT 24
Peak memory 202076 kb
Host smart-ef941447-9a83-4ffa-8436-88f0c2d60525
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582430373 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_c
trl_ultra_low_pwr.582430373
Directory /workspace/34.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_alert_test.1003456997
Short name T691
Test name
Test status
Simulation time 2038962193 ps
CPU time 1.95 seconds
Started Mar 24 01:16:21 PM PDT 24
Finished Mar 24 01:16:23 PM PDT 24
Peak memory 202080 kb
Host smart-1e349643-5b7a-4aff-ac97-501d23db985f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003456997 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_alert_te
st.1003456997
Directory /workspace/35.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_auto_blk_key_output.3426359899
Short name T231
Test name
Test status
Simulation time 3673751282 ps
CPU time 10.23 seconds
Started Mar 24 01:16:05 PM PDT 24
Finished Mar 24 01:16:15 PM PDT 24
Peak memory 202132 kb
Host smart-94bdb597-8647-4754-a2b8-30f086468c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426359899 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_auto_blk_key_output.3
426359899
Directory /workspace/35.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect.916197939
Short name T253
Test name
Test status
Simulation time 79674855548 ps
CPU time 46.84 seconds
Started Mar 24 01:16:20 PM PDT 24
Finished Mar 24 01:17:07 PM PDT 24
Peak memory 202244 kb
Host smart-bdc1eb93-973b-4b31-a85d-76217b363fd4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916197939 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ct
rl_combo_detect.916197939
Directory /workspace/35.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.214223407
Short name T342
Test name
Test status
Simulation time 76896636726 ps
CPU time 51.71 seconds
Started Mar 24 01:16:07 PM PDT 24
Finished Mar 24 01:16:59 PM PDT 24
Peak memory 202276 kb
Host smart-a2ca4435-77e9-4ea6-8e4a-c23ec18340c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214223407 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect_wi
th_pre_cond.214223407
Directory /workspace/35.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.2769797772
Short name T69
Test name
Test status
Simulation time 4485945531 ps
CPU time 1.36 seconds
Started Mar 24 01:16:22 PM PDT 24
Finished Mar 24 01:16:23 PM PDT 24
Peak memory 202040 kb
Host smart-237abb02-db1a-4f10-8d70-dcef0cf74564
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769797772 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_
ctrl_ec_pwr_on_rst.2769797772
Directory /workspace/35.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_edge_detect.2132578563
Short name T37
Test name
Test status
Simulation time 3190671853 ps
CPU time 4.63 seconds
Started Mar 24 01:16:16 PM PDT 24
Finished Mar 24 01:16:21 PM PDT 24
Peak memory 202036 kb
Host smart-fb040a14-34cf-4873-b40c-083f6f03d4e9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132578563 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ct
rl_edge_detect.2132578563
Directory /workspace/35.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.2481581560
Short name T285
Test name
Test status
Simulation time 2645214577 ps
CPU time 2.01 seconds
Started Mar 24 01:16:04 PM PDT 24
Finished Mar 24 01:16:07 PM PDT 24
Peak memory 202060 kb
Host smart-d8cf80fa-2281-4ebc-afcb-8640a5608595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481581560 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_flash_wr_prot_out.2481581560
Directory /workspace/35.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_in_out_inverted.2651708422
Short name T760
Test name
Test status
Simulation time 2542801189 ps
CPU time 1.46 seconds
Started Mar 24 01:16:03 PM PDT 24
Finished Mar 24 01:16:05 PM PDT 24
Peak memory 202036 kb
Host smart-c9471fb2-433a-48a8-a959-f11dfd95662c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651708422 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_in_out_inverted.2651708422
Directory /workspace/35.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_access_test.3037766058
Short name T705
Test name
Test status
Simulation time 2210420570 ps
CPU time 2.1 seconds
Started Mar 24 01:16:03 PM PDT 24
Finished Mar 24 01:16:06 PM PDT 24
Peak memory 202072 kb
Host smart-b41bc3df-7ef0-4850-a96c-38a7d3df67b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037766058 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_access_test.3037766058
Directory /workspace/35.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_override_test.1553164096
Short name T696
Test name
Test status
Simulation time 2528931602 ps
CPU time 2.34 seconds
Started Mar 24 01:16:05 PM PDT 24
Finished Mar 24 01:16:08 PM PDT 24
Peak memory 202024 kb
Host smart-832208ed-deea-4aa5-95ee-0a8bf0bcb77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553164096 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_override_test.1553164096
Directory /workspace/35.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_smoke.1111234206
Short name T601
Test name
Test status
Simulation time 2125943929 ps
CPU time 2.11 seconds
Started Mar 24 01:16:17 PM PDT 24
Finished Mar 24 01:16:19 PM PDT 24
Peak memory 201800 kb
Host smart-26bdfd48-4071-4537-9b0c-ad397fb9c644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111234206 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_smoke.1111234206
Directory /workspace/35.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all.3066296163
Short name T221
Test name
Test status
Simulation time 13539161738 ps
CPU time 36.97 seconds
Started Mar 24 01:16:05 PM PDT 24
Finished Mar 24 01:16:42 PM PDT 24
Peak memory 202076 kb
Host smart-d32fc55b-59bb-4650-a579-97242160f906
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066296163 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_s
tress_all.3066296163
Directory /workspace/35.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_alert_test.270306480
Short name T153
Test name
Test status
Simulation time 2015212652 ps
CPU time 5.88 seconds
Started Mar 24 01:16:05 PM PDT 24
Finished Mar 24 01:16:11 PM PDT 24
Peak memory 201976 kb
Host smart-54a15270-d685-42a7-abb3-4a134de52a3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270306480 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_alert_tes
t.270306480
Directory /workspace/36.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_auto_blk_key_output.1056065159
Short name T557
Test name
Test status
Simulation time 3222409963 ps
CPU time 1.06 seconds
Started Mar 24 01:16:14 PM PDT 24
Finished Mar 24 01:16:16 PM PDT 24
Peak memory 202112 kb
Host smart-77b51d87-0972-4ffd-bf01-5c2097e2f0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056065159 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_auto_blk_key_output.1
056065159
Directory /workspace/36.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect.101666887
Short name T31
Test name
Test status
Simulation time 89078842511 ps
CPU time 114.91 seconds
Started Mar 24 01:16:04 PM PDT 24
Finished Mar 24 01:18:00 PM PDT 24
Peak memory 202228 kb
Host smart-e5fb1310-986f-43e7-80f9-c2a3271d4ec7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101666887 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ct
rl_combo_detect.101666887
Directory /workspace/36.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.4163000386
Short name T33
Test name
Test status
Simulation time 54655651100 ps
CPU time 73.32 seconds
Started Mar 24 01:16:19 PM PDT 24
Finished Mar 24 01:17:32 PM PDT 24
Peak memory 202316 kb
Host smart-66e7331b-38b8-485b-a599-5be43794261b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163000386 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect_w
ith_pre_cond.4163000386
Directory /workspace/36.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.1374429089
Short name T508
Test name
Test status
Simulation time 4112444851 ps
CPU time 12 seconds
Started Mar 24 01:16:07 PM PDT 24
Finished Mar 24 01:16:19 PM PDT 24
Peak memory 201984 kb
Host smart-8584a39f-2114-4455-9685-461650c666ff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374429089 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_
ctrl_ec_pwr_on_rst.1374429089
Directory /workspace/36.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_edge_detect.1032997247
Short name T143
Test name
Test status
Simulation time 3655514657 ps
CPU time 6.3 seconds
Started Mar 24 01:16:10 PM PDT 24
Finished Mar 24 01:16:17 PM PDT 24
Peak memory 202040 kb
Host smart-678bbbad-5e38-4647-a0cf-66fc6b8972d8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032997247 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ct
rl_edge_detect.1032997247
Directory /workspace/36.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.3503565663
Short name T157
Test name
Test status
Simulation time 2611274545 ps
CPU time 7.83 seconds
Started Mar 24 01:16:17 PM PDT 24
Finished Mar 24 01:16:25 PM PDT 24
Peak memory 202048 kb
Host smart-4e130ab4-f5a0-47e7-9bbe-c397281e22fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503565663 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_flash_wr_prot_out.3503565663
Directory /workspace/36.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.1114304186
Short name T718
Test name
Test status
Simulation time 2458825413 ps
CPU time 7.46 seconds
Started Mar 24 01:16:18 PM PDT 24
Finished Mar 24 01:16:25 PM PDT 24
Peak memory 202072 kb
Host smart-ef053d45-64db-4597-889f-646d1407ea17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114304186 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_in_out_inverted.1114304186
Directory /workspace/36.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_access_test.284892150
Short name T102
Test name
Test status
Simulation time 2215854442 ps
CPU time 6.06 seconds
Started Mar 24 01:16:07 PM PDT 24
Finished Mar 24 01:16:13 PM PDT 24
Peak memory 201996 kb
Host smart-7a838c34-c51b-4b85-88fd-7bbaf768a666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284892150 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_access_test.284892150
Directory /workspace/36.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_override_test.3321552090
Short name T418
Test name
Test status
Simulation time 2513132350 ps
CPU time 7.08 seconds
Started Mar 24 01:16:07 PM PDT 24
Finished Mar 24 01:16:14 PM PDT 24
Peak memory 202024 kb
Host smart-f305f75b-5462-4efb-8bb4-72f458d96cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321552090 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_override_test.3321552090
Directory /workspace/36.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_smoke.1835631500
Short name T446
Test name
Test status
Simulation time 2122118503 ps
CPU time 3.44 seconds
Started Mar 24 01:16:20 PM PDT 24
Finished Mar 24 01:16:23 PM PDT 24
Peak memory 201832 kb
Host smart-b8dc9a05-607e-484c-92c5-8c1c1e168bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835631500 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_smoke.1835631500
Directory /workspace/36.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all.262906766
Short name T600
Test name
Test status
Simulation time 12316274223 ps
CPU time 16.85 seconds
Started Mar 24 01:16:14 PM PDT 24
Finished Mar 24 01:16:32 PM PDT 24
Peak memory 202056 kb
Host smart-1948595f-b18e-4ae9-bbd3-d02bdb7d623d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262906766 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_st
ress_all.262906766
Directory /workspace/36.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ultra_low_pwr.2163986625
Short name T561
Test name
Test status
Simulation time 14448101034 ps
CPU time 1.22 seconds
Started Mar 24 01:16:09 PM PDT 24
Finished Mar 24 01:16:10 PM PDT 24
Peak memory 202036 kb
Host smart-730c436c-c1fb-4f55-a55f-b4f55a5a4246
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163986625 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_
ctrl_ultra_low_pwr.2163986625
Directory /workspace/36.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_alert_test.826364284
Short name T724
Test name
Test status
Simulation time 2182527031 ps
CPU time 0.88 seconds
Started Mar 24 01:16:06 PM PDT 24
Finished Mar 24 01:16:07 PM PDT 24
Peak memory 202144 kb
Host smart-18e27dea-3012-4621-8ebb-5095c4301ed3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826364284 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_alert_tes
t.826364284
Directory /workspace/37.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.3106974930
Short name T503
Test name
Test status
Simulation time 3119785027 ps
CPU time 2.39 seconds
Started Mar 24 01:16:07 PM PDT 24
Finished Mar 24 01:16:10 PM PDT 24
Peak memory 202140 kb
Host smart-0bf1b745-360b-49d8-9cf5-3b917f1b9eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106974930 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_auto_blk_key_output.3
106974930
Directory /workspace/37.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect.2904865504
Short name T649
Test name
Test status
Simulation time 66844943785 ps
CPU time 160.02 seconds
Started Mar 24 01:16:20 PM PDT 24
Finished Mar 24 01:19:00 PM PDT 24
Peak memory 202232 kb
Host smart-18dcbdab-7a18-41a7-aeed-608557b219f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904865504 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_c
trl_combo_detect.2904865504
Directory /workspace/37.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.3913366079
Short name T727
Test name
Test status
Simulation time 26864273416 ps
CPU time 13.4 seconds
Started Mar 24 01:16:05 PM PDT 24
Finished Mar 24 01:16:18 PM PDT 24
Peak memory 202280 kb
Host smart-bf00d2ac-31d8-4c87-a79b-4b9e0223e0a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913366079 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect_w
ith_pre_cond.3913366079
Directory /workspace/37.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.2224581949
Short name T491
Test name
Test status
Simulation time 566872406428 ps
CPU time 1547.87 seconds
Started Mar 24 01:16:07 PM PDT 24
Finished Mar 24 01:41:55 PM PDT 24
Peak memory 202080 kb
Host smart-07e0f1e1-55e0-425e-9127-ab7d523ef9b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224581949 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_
ctrl_ec_pwr_on_rst.2224581949
Directory /workspace/37.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_edge_detect.781921005
Short name T182
Test name
Test status
Simulation time 2949807349 ps
CPU time 1.36 seconds
Started Mar 24 01:16:06 PM PDT 24
Finished Mar 24 01:16:08 PM PDT 24
Peak memory 201972 kb
Host smart-7c8d09eb-3a9b-4f63-acae-827d3245c93a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781921005 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctr
l_edge_detect.781921005
Directory /workspace/37.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.3451952660
Short name T597
Test name
Test status
Simulation time 2619297640 ps
CPU time 3.77 seconds
Started Mar 24 01:16:21 PM PDT 24
Finished Mar 24 01:16:25 PM PDT 24
Peak memory 202060 kb
Host smart-19782294-9be1-4045-a5de-1247645e234b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451952660 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_flash_wr_prot_out.3451952660
Directory /workspace/37.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.2632934913
Short name T549
Test name
Test status
Simulation time 2470398370 ps
CPU time 2.47 seconds
Started Mar 24 01:16:18 PM PDT 24
Finished Mar 24 01:16:20 PM PDT 24
Peak memory 202036 kb
Host smart-dfe98279-a314-4e34-befd-888145186fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632934913 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_in_out_inverted.2632934913
Directory /workspace/37.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_access_test.3357821319
Short name T70
Test name
Test status
Simulation time 2058118231 ps
CPU time 1.95 seconds
Started Mar 24 01:16:21 PM PDT 24
Finished Mar 24 01:16:23 PM PDT 24
Peak memory 201912 kb
Host smart-ebdf0853-fb04-471d-b386-25c07f28ddca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357821319 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_access_test.3357821319
Directory /workspace/37.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_override_test.3308573302
Short name T291
Test name
Test status
Simulation time 2511108976 ps
CPU time 6.56 seconds
Started Mar 24 01:16:09 PM PDT 24
Finished Mar 24 01:16:16 PM PDT 24
Peak memory 202040 kb
Host smart-5d19cfe4-fd5d-4a85-a0f5-9c9aa0e40c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308573302 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_override_test.3308573302
Directory /workspace/37.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_smoke.2256026400
Short name T5
Test name
Test status
Simulation time 2109052926 ps
CPU time 6.18 seconds
Started Mar 24 01:16:21 PM PDT 24
Finished Mar 24 01:16:27 PM PDT 24
Peak memory 201920 kb
Host smart-307c322e-f076-4160-a737-a78a444ac512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256026400 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_smoke.2256026400
Directory /workspace/37.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all.2667565723
Short name T380
Test name
Test status
Simulation time 79358707677 ps
CPU time 109.83 seconds
Started Mar 24 01:16:07 PM PDT 24
Finished Mar 24 01:17:57 PM PDT 24
Peak memory 202300 kb
Host smart-29a91762-2895-4f25-b0ec-068d1f37e65a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667565723 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_s
tress_all.2667565723
Directory /workspace/37.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.2769100728
Short name T122
Test name
Test status
Simulation time 54155224084 ps
CPU time 37.27 seconds
Started Mar 24 01:16:08 PM PDT 24
Finished Mar 24 01:16:45 PM PDT 24
Peak memory 213064 kb
Host smart-8fba8566-80c4-42c5-b6a5-40e57224ac10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769100728 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_stress_all_with_rand_reset.2769100728
Directory /workspace/37.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.4099359348
Short name T476
Test name
Test status
Simulation time 8972939699 ps
CPU time 8.47 seconds
Started Mar 24 01:16:15 PM PDT 24
Finished Mar 24 01:16:24 PM PDT 24
Peak memory 202072 kb
Host smart-35dd7172-7789-40e1-ab4f-d2678ad3faae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099359348 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_
ctrl_ultra_low_pwr.4099359348
Directory /workspace/37.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_alert_test.3921497785
Short name T541
Test name
Test status
Simulation time 2020400727 ps
CPU time 2.83 seconds
Started Mar 24 01:16:21 PM PDT 24
Finished Mar 24 01:16:24 PM PDT 24
Peak memory 202076 kb
Host smart-3d096edd-9714-4be8-ad41-267b2e8ba56a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921497785 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_alert_te
st.3921497785
Directory /workspace/38.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.977400538
Short name T226
Test name
Test status
Simulation time 3545960321 ps
CPU time 1.07 seconds
Started Mar 24 01:16:14 PM PDT 24
Finished Mar 24 01:16:16 PM PDT 24
Peak memory 202124 kb
Host smart-846836b1-c347-4516-ac31-80585e06f1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977400538 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_auto_blk_key_output.977400538
Directory /workspace/38.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect.2331195044
Short name T551
Test name
Test status
Simulation time 74601961546 ps
CPU time 45.49 seconds
Started Mar 24 01:16:11 PM PDT 24
Finished Mar 24 01:16:57 PM PDT 24
Peak memory 202300 kb
Host smart-518fe9f3-e337-4281-81e8-61cf29ce8006
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331195044 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_c
trl_combo_detect.2331195044
Directory /workspace/38.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.2472269878
Short name T512
Test name
Test status
Simulation time 26582382414 ps
CPU time 71.43 seconds
Started Mar 24 01:16:12 PM PDT 24
Finished Mar 24 01:17:24 PM PDT 24
Peak memory 202272 kb
Host smart-d01ee9df-b2bd-48ac-bdae-433c38353eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472269878 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect_w
ith_pre_cond.2472269878
Directory /workspace/38.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.728772706
Short name T165
Test name
Test status
Simulation time 2999265749 ps
CPU time 2.3 seconds
Started Mar 24 01:16:20 PM PDT 24
Finished Mar 24 01:16:22 PM PDT 24
Peak memory 202044 kb
Host smart-f3cc3265-3655-4d9f-996f-e7d40a36cedf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728772706 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_c
trl_ec_pwr_on_rst.728772706
Directory /workspace/38.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_edge_detect.319777663
Short name T163
Test name
Test status
Simulation time 2823872460 ps
CPU time 2.26 seconds
Started Mar 24 01:16:14 PM PDT 24
Finished Mar 24 01:16:17 PM PDT 24
Peak memory 202072 kb
Host smart-51c181e5-0283-4dfa-a500-0f16dbc80885
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319777663 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctr
l_edge_detect.319777663
Directory /workspace/38.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.2690560826
Short name T542
Test name
Test status
Simulation time 2631393936 ps
CPU time 2.13 seconds
Started Mar 24 01:16:23 PM PDT 24
Finished Mar 24 01:16:25 PM PDT 24
Peak memory 202028 kb
Host smart-2d2866e1-3e69-4d0f-988f-603c44a913d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690560826 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_flash_wr_prot_out.2690560826
Directory /workspace/38.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.3336490738
Short name T432
Test name
Test status
Simulation time 2467326123 ps
CPU time 7.09 seconds
Started Mar 24 01:16:05 PM PDT 24
Finished Mar 24 01:16:12 PM PDT 24
Peak memory 202056 kb
Host smart-c904ce7a-ca97-4c8e-8387-5a9484c12fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336490738 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_in_out_inverted.3336490738
Directory /workspace/38.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_access_test.1793485521
Short name T732
Test name
Test status
Simulation time 2180972169 ps
CPU time 6.4 seconds
Started Mar 24 01:16:04 PM PDT 24
Finished Mar 24 01:16:11 PM PDT 24
Peak memory 202068 kb
Host smart-6a1010c3-80bb-46e1-a3b7-f2892a8a86ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793485521 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_access_test.1793485521
Directory /workspace/38.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_override_test.4148817121
Short name T699
Test name
Test status
Simulation time 2562282559 ps
CPU time 1.34 seconds
Started Mar 24 01:16:23 PM PDT 24
Finished Mar 24 01:16:25 PM PDT 24
Peak memory 202080 kb
Host smart-81c7d909-e872-4b75-90a2-01ae702bdc4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148817121 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_override_test.4148817121
Directory /workspace/38.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_smoke.2242730335
Short name T682
Test name
Test status
Simulation time 2122723714 ps
CPU time 3.27 seconds
Started Mar 24 01:16:09 PM PDT 24
Finished Mar 24 01:16:12 PM PDT 24
Peak memory 201904 kb
Host smart-25e75afc-394f-493c-899a-b13fe91dfcc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242730335 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_smoke.2242730335
Directory /workspace/38.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all.2807249052
Short name T525
Test name
Test status
Simulation time 15072303880 ps
CPU time 20.93 seconds
Started Mar 24 01:16:08 PM PDT 24
Finished Mar 24 01:16:29 PM PDT 24
Peak memory 202132 kb
Host smart-ede21f26-809e-4ab7-8710-652c05e1167f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807249052 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_s
tress_all.2807249052
Directory /workspace/38.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.1169449553
Short name T141
Test name
Test status
Simulation time 72783621177 ps
CPU time 44.63 seconds
Started Mar 24 01:16:09 PM PDT 24
Finished Mar 24 01:16:53 PM PDT 24
Peak memory 210608 kb
Host smart-f1dd60a5-973b-45b9-97ec-de85106c79f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169449553 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_stress_all_with_rand_reset.1169449553
Directory /workspace/38.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_alert_test.4140234121
Short name T673
Test name
Test status
Simulation time 2012884800 ps
CPU time 5.12 seconds
Started Mar 24 01:16:16 PM PDT 24
Finished Mar 24 01:16:21 PM PDT 24
Peak memory 202068 kb
Host smart-3bb36e13-7c52-4ef0-9f8f-1c1f3c410b1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140234121 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_alert_te
st.4140234121
Directory /workspace/39.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.3920169874
Short name T214
Test name
Test status
Simulation time 325209875229 ps
CPU time 199.26 seconds
Started Mar 24 01:16:23 PM PDT 24
Finished Mar 24 01:19:43 PM PDT 24
Peak memory 202116 kb
Host smart-7deb0ce9-5f9d-4807-b509-eba99497da6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920169874 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_auto_blk_key_output.3
920169874
Directory /workspace/39.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.598424483
Short name T467
Test name
Test status
Simulation time 3304184839 ps
CPU time 4.73 seconds
Started Mar 24 01:16:21 PM PDT 24
Finished Mar 24 01:16:26 PM PDT 24
Peak memory 202276 kb
Host smart-8b71dad2-1b10-4625-98c8-3950dccec298
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598424483 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_c
trl_ec_pwr_on_rst.598424483
Directory /workspace/39.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_edge_detect.1100751880
Short name T40
Test name
Test status
Simulation time 2737618550 ps
CPU time 2.71 seconds
Started Mar 24 01:16:10 PM PDT 24
Finished Mar 24 01:16:12 PM PDT 24
Peak memory 202068 kb
Host smart-54d8ca2b-fd0b-4017-890d-3adb428c5d6f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100751880 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ct
rl_edge_detect.1100751880
Directory /workspace/39.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.2138781062
Short name T497
Test name
Test status
Simulation time 2615720217 ps
CPU time 4.1 seconds
Started Mar 24 01:16:11 PM PDT 24
Finished Mar 24 01:16:16 PM PDT 24
Peak memory 202044 kb
Host smart-7dfd41aa-5710-4db7-97dc-0bc72e073b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138781062 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_flash_wr_prot_out.2138781062
Directory /workspace/39.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.2478933712
Short name T436
Test name
Test status
Simulation time 2456788165 ps
CPU time 1.99 seconds
Started Mar 24 01:16:14 PM PDT 24
Finished Mar 24 01:16:17 PM PDT 24
Peak memory 201980 kb
Host smart-78a76667-b8d8-4798-b286-9d857f6324ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478933712 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_in_out_inverted.2478933712
Directory /workspace/39.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_access_test.1377390468
Short name T107
Test name
Test status
Simulation time 2076726604 ps
CPU time 5.89 seconds
Started Mar 24 01:16:10 PM PDT 24
Finished Mar 24 01:16:16 PM PDT 24
Peak memory 201912 kb
Host smart-4c7d8139-4226-47d5-b06a-b0d1f97546ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377390468 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_access_test.1377390468
Directory /workspace/39.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_override_test.1676411432
Short name T548
Test name
Test status
Simulation time 2509952247 ps
CPU time 7.39 seconds
Started Mar 24 01:16:17 PM PDT 24
Finished Mar 24 01:16:25 PM PDT 24
Peak memory 202052 kb
Host smart-5f144ac0-1bb8-44c2-91ee-519f549fddd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676411432 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_override_test.1676411432
Directory /workspace/39.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_smoke.503913230
Short name T173
Test name
Test status
Simulation time 2110886781 ps
CPU time 6.07 seconds
Started Mar 24 01:16:07 PM PDT 24
Finished Mar 24 01:16:14 PM PDT 24
Peak memory 201872 kb
Host smart-4e98c738-6fde-462d-a651-bda1fd291695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503913230 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_smoke.503913230
Directory /workspace/39.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all.658780503
Short name T34
Test name
Test status
Simulation time 13907017524 ps
CPU time 18.09 seconds
Started Mar 24 01:16:16 PM PDT 24
Finished Mar 24 01:16:34 PM PDT 24
Peak memory 202072 kb
Host smart-ca20bf46-658a-4849-8a9e-014afe30e16c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658780503 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_st
ress_all.658780503
Directory /workspace/39.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.1173869085
Short name T62
Test name
Test status
Simulation time 5490117837 ps
CPU time 6.58 seconds
Started Mar 24 01:16:21 PM PDT 24
Finished Mar 24 01:16:28 PM PDT 24
Peak memory 202084 kb
Host smart-c64ec270-01f9-44e4-bb59-3a295363697f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173869085 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_
ctrl_ultra_low_pwr.1173869085
Directory /workspace/39.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_alert_test.1815688899
Short name T453
Test name
Test status
Simulation time 2011731250 ps
CPU time 6 seconds
Started Mar 24 01:14:59 PM PDT 24
Finished Mar 24 01:15:06 PM PDT 24
Peak memory 202060 kb
Host smart-b304b9ef-5a3b-4db4-8b9d-6a975742c3a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815688899 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_alert_tes
t.1815688899
Directory /workspace/4.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.3221943446
Short name T590
Test name
Test status
Simulation time 3252035331 ps
CPU time 9.25 seconds
Started Mar 24 01:14:56 PM PDT 24
Finished Mar 24 01:15:05 PM PDT 24
Peak memory 202144 kb
Host smart-0a3f13b8-4145-4b78-9f35-8b6aedc613b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221943446 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_auto_blk_key_output.3221943446
Directory /workspace/4.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect.3732452395
Short name T377
Test name
Test status
Simulation time 173519632956 ps
CPU time 459.08 seconds
Started Mar 24 01:14:58 PM PDT 24
Finished Mar 24 01:22:38 PM PDT 24
Peak memory 202248 kb
Host smart-8acf1c5b-a4ba-4411-88d5-1cb3495cfa7e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732452395 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ct
rl_combo_detect.3732452395
Directory /workspace/4.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.2626622900
Short name T395
Test name
Test status
Simulation time 2212814284 ps
CPU time 1.96 seconds
Started Mar 24 01:14:52 PM PDT 24
Finished Mar 24 01:14:55 PM PDT 24
Peak memory 202024 kb
Host smart-013c02b9-0e56-4a75-bf5e-bb2742128093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626622900 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst.2626622900
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3515483277
Short name T779
Test name
Test status
Simulation time 2560169199 ps
CPU time 1.38 seconds
Started Mar 24 01:14:52 PM PDT 24
Finished Mar 24 01:14:54 PM PDT 24
Peak memory 202004 kb
Host smart-f7dac7af-01c3-466b-9bee-7d784a5dd4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515483277 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.3515483277
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.3573166252
Short name T530
Test name
Test status
Simulation time 5278377655 ps
CPU time 3.74 seconds
Started Mar 24 01:14:56 PM PDT 24
Finished Mar 24 01:15:00 PM PDT 24
Peak memory 202028 kb
Host smart-9dba4e5e-84d0-41d6-823f-8019044f6bdb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573166252 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_ec_pwr_on_rst.3573166252
Directory /workspace/4.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_edge_detect.3527195791
Short name T576
Test name
Test status
Simulation time 2788349080 ps
CPU time 2.41 seconds
Started Mar 24 01:15:00 PM PDT 24
Finished Mar 24 01:15:03 PM PDT 24
Peak memory 201764 kb
Host smart-00a6fe5d-c694-4f8d-9571-3c6adb31490d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527195791 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctr
l_edge_detect.3527195791
Directory /workspace/4.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.1895304454
Short name T435
Test name
Test status
Simulation time 2617177393 ps
CPU time 4.55 seconds
Started Mar 24 01:14:53 PM PDT 24
Finished Mar 24 01:14:58 PM PDT 24
Peak memory 202052 kb
Host smart-41b23f47-d115-4a3c-aba6-61f7b2ac037e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895304454 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_flash_wr_prot_out.1895304454
Directory /workspace/4.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.1982981376
Short name T63
Test name
Test status
Simulation time 2499027008 ps
CPU time 2.32 seconds
Started Mar 24 01:14:56 PM PDT 24
Finished Mar 24 01:14:58 PM PDT 24
Peak memory 202064 kb
Host smart-104d7428-a68f-4a00-87e3-77103175e0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982981376 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_in_out_inverted.1982981376
Directory /workspace/4.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_access_test.516752052
Short name T273
Test name
Test status
Simulation time 2098209032 ps
CPU time 0.97 seconds
Started Mar 24 01:14:54 PM PDT 24
Finished Mar 24 01:14:55 PM PDT 24
Peak memory 201912 kb
Host smart-570265a3-aa42-4d3c-acf4-0e501c985ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516752052 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_access_test.516752052
Directory /workspace/4.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_override_test.3779602812
Short name T586
Test name
Test status
Simulation time 2511884556 ps
CPU time 7.29 seconds
Started Mar 24 01:14:51 PM PDT 24
Finished Mar 24 01:14:59 PM PDT 24
Peak memory 202044 kb
Host smart-d43fb081-f472-46cf-8298-997f6bcba8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779602812 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_override_test.3779602812
Directory /workspace/4.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_sec_cm.987118108
Short name T262
Test name
Test status
Simulation time 42014140482 ps
CPU time 58.79 seconds
Started Mar 24 01:15:01 PM PDT 24
Finished Mar 24 01:15:59 PM PDT 24
Peak memory 221768 kb
Host smart-c49b4ff9-1fa8-4c6b-ac84-09f88abcd2ed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987118108 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_sec_cm.987118108
Directory /workspace/4.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_smoke.1602485647
Short name T643
Test name
Test status
Simulation time 2112828525 ps
CPU time 5.64 seconds
Started Mar 24 01:14:59 PM PDT 24
Finished Mar 24 01:15:05 PM PDT 24
Peak memory 201932 kb
Host smart-fe14bf7f-fb05-466d-91ed-b27805a78874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602485647 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_smoke.1602485647
Directory /workspace/4.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all.145266519
Short name T189
Test name
Test status
Simulation time 59178330026 ps
CPU time 20.58 seconds
Started Mar 24 01:15:01 PM PDT 24
Finished Mar 24 01:15:22 PM PDT 24
Peak memory 202088 kb
Host smart-e4a95f63-6144-47bc-9096-1ada7fcbedc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145266519 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_str
ess_all.145266519
Directory /workspace/4.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.3059278871
Short name T22
Test name
Test status
Simulation time 951736968685 ps
CPU time 8.92 seconds
Started Mar 24 01:14:52 PM PDT 24
Finished Mar 24 01:15:02 PM PDT 24
Peak memory 202056 kb
Host smart-7d8f36d4-bfe7-4c8b-aa46-f9141d784fa4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059278871 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_ultra_low_pwr.3059278871
Directory /workspace/4.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_alert_test.914723617
Short name T396
Test name
Test status
Simulation time 2010214405 ps
CPU time 6.28 seconds
Started Mar 24 01:16:09 PM PDT 24
Finished Mar 24 01:16:15 PM PDT 24
Peak memory 202036 kb
Host smart-33e81259-902c-4a31-a90c-85260acfb952
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914723617 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_alert_tes
t.914723617
Directory /workspace/40.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.3171488587
Short name T232
Test name
Test status
Simulation time 83933860917 ps
CPU time 76.54 seconds
Started Mar 24 01:16:21 PM PDT 24
Finished Mar 24 01:17:38 PM PDT 24
Peak memory 202108 kb
Host smart-b0294387-f711-4009-b74b-04a20507fec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171488587 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_auto_blk_key_output.3
171488587
Directory /workspace/40.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect.3497582299
Short name T738
Test name
Test status
Simulation time 148604551342 ps
CPU time 367.58 seconds
Started Mar 24 01:16:27 PM PDT 24
Finished Mar 24 01:22:35 PM PDT 24
Peak memory 202288 kb
Host smart-f011141a-5b91-439e-b415-c44ef3ad35ef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497582299 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_c
trl_combo_detect.3497582299
Directory /workspace/40.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.1818434984
Short name T357
Test name
Test status
Simulation time 142863135522 ps
CPU time 376.82 seconds
Started Mar 24 01:16:21 PM PDT 24
Finished Mar 24 01:22:38 PM PDT 24
Peak memory 202240 kb
Host smart-6ff1005c-2c97-4ae4-9e36-a9ca938787b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818434984 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect_w
ith_pre_cond.1818434984
Directory /workspace/40.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.3990931778
Short name T215
Test name
Test status
Simulation time 4274331725 ps
CPU time 3.7 seconds
Started Mar 24 01:16:16 PM PDT 24
Finished Mar 24 01:16:20 PM PDT 24
Peak memory 202056 kb
Host smart-3895fd7b-4d40-4eff-b84b-6848691a14a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990931778 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_
ctrl_ec_pwr_on_rst.3990931778
Directory /workspace/40.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_edge_detect.2059272118
Short name T195
Test name
Test status
Simulation time 4355934290 ps
CPU time 4.9 seconds
Started Mar 24 01:16:27 PM PDT 24
Finished Mar 24 01:16:32 PM PDT 24
Peak memory 202032 kb
Host smart-546f3e0f-0f2b-42cb-8e57-e9fdbfe09270
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059272118 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ct
rl_edge_detect.2059272118
Directory /workspace/40.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.2666829444
Short name T445
Test name
Test status
Simulation time 2614989208 ps
CPU time 4.23 seconds
Started Mar 24 01:16:18 PM PDT 24
Finished Mar 24 01:16:22 PM PDT 24
Peak memory 202028 kb
Host smart-7e4833a9-0c28-4cab-bfdb-2249f31e5f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666829444 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_flash_wr_prot_out.2666829444
Directory /workspace/40.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.3484816208
Short name T293
Test name
Test status
Simulation time 2463952800 ps
CPU time 3.65 seconds
Started Mar 24 01:16:22 PM PDT 24
Finished Mar 24 01:16:25 PM PDT 24
Peak memory 202076 kb
Host smart-a6573e7e-11ae-46b8-b679-d63bc064649b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484816208 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_in_out_inverted.3484816208
Directory /workspace/40.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_access_test.1869833084
Short name T647
Test name
Test status
Simulation time 2209209034 ps
CPU time 6.36 seconds
Started Mar 24 01:16:13 PM PDT 24
Finished Mar 24 01:16:19 PM PDT 24
Peak memory 202024 kb
Host smart-fe5e4cef-0f06-4591-8bb8-a83fde2d3c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869833084 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_access_test.1869833084
Directory /workspace/40.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_override_test.3369799308
Short name T106
Test name
Test status
Simulation time 2510553449 ps
CPU time 7.1 seconds
Started Mar 24 01:16:23 PM PDT 24
Finished Mar 24 01:16:31 PM PDT 24
Peak memory 202072 kb
Host smart-369bbc74-1e32-428c-9de0-3da1abb99416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369799308 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_override_test.3369799308
Directory /workspace/40.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_smoke.1541086295
Short name T693
Test name
Test status
Simulation time 2142518876 ps
CPU time 1.78 seconds
Started Mar 24 01:16:11 PM PDT 24
Finished Mar 24 01:16:13 PM PDT 24
Peak memory 201956 kb
Host smart-9daa680a-1f30-42d4-93c9-9d26d3e93aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541086295 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_smoke.1541086295
Directory /workspace/40.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.1802309756
Short name T276
Test name
Test status
Simulation time 7418823772 ps
CPU time 20.12 seconds
Started Mar 24 01:16:24 PM PDT 24
Finished Mar 24 01:16:44 PM PDT 24
Peak memory 202184 kb
Host smart-06e505e2-9c06-4e33-b9e4-0fe68446e0fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802309756 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_stress_all_with_rand_reset.1802309756
Directory /workspace/40.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.581942873
Short name T388
Test name
Test status
Simulation time 869080571439 ps
CPU time 43.48 seconds
Started Mar 24 01:16:08 PM PDT 24
Finished Mar 24 01:16:52 PM PDT 24
Peak memory 202088 kb
Host smart-c6f9a8f2-3f94-4c4e-95bb-ac6da726fce6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581942873 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_c
trl_ultra_low_pwr.581942873
Directory /workspace/40.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_alert_test.3460733983
Short name T426
Test name
Test status
Simulation time 2018945367 ps
CPU time 3.22 seconds
Started Mar 24 01:16:31 PM PDT 24
Finished Mar 24 01:16:35 PM PDT 24
Peak memory 202060 kb
Host smart-19aba61d-218e-44a9-901d-f70fa93adc4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460733983 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_alert_te
st.3460733983
Directory /workspace/41.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.324304872
Short name T470
Test name
Test status
Simulation time 3122029694 ps
CPU time 2.68 seconds
Started Mar 24 01:16:16 PM PDT 24
Finished Mar 24 01:16:18 PM PDT 24
Peak memory 202116 kb
Host smart-bab33133-0c2a-4617-a4f3-9f2a4a24eeaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324304872 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_auto_blk_key_output.324304872
Directory /workspace/41.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect.1078049960
Short name T256
Test name
Test status
Simulation time 100640313510 ps
CPU time 21.35 seconds
Started Mar 24 01:16:15 PM PDT 24
Finished Mar 24 01:16:37 PM PDT 24
Peak memory 202224 kb
Host smart-67fa9a26-efad-4904-8aa7-9088406d6d25
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078049960 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_c
trl_combo_detect.1078049960
Directory /workspace/41.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.729663614
Short name T769
Test name
Test status
Simulation time 5157683817 ps
CPU time 13.39 seconds
Started Mar 24 01:16:19 PM PDT 24
Finished Mar 24 01:16:33 PM PDT 24
Peak memory 201956 kb
Host smart-d64dc2a5-e352-4e2f-8108-89aa7c1bc720
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729663614 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_c
trl_ec_pwr_on_rst.729663614
Directory /workspace/41.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_edge_detect.997073045
Short name T288
Test name
Test status
Simulation time 4818316160 ps
CPU time 2.54 seconds
Started Mar 24 01:16:30 PM PDT 24
Finished Mar 24 01:16:33 PM PDT 24
Peak memory 202052 kb
Host smart-39238e29-2166-4778-84b5-4187fc46d74e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997073045 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctr
l_edge_detect.997073045
Directory /workspace/41.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.2145123805
Short name T514
Test name
Test status
Simulation time 2609751129 ps
CPU time 8.06 seconds
Started Mar 24 01:16:19 PM PDT 24
Finished Mar 24 01:16:27 PM PDT 24
Peak memory 202052 kb
Host smart-6907cf56-d9af-4fd7-95b4-6504eb387dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145123805 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_flash_wr_prot_out.2145123805
Directory /workspace/41.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.1449040324
Short name T208
Test name
Test status
Simulation time 2492179559 ps
CPU time 2.44 seconds
Started Mar 24 01:16:18 PM PDT 24
Finished Mar 24 01:16:21 PM PDT 24
Peak memory 202044 kb
Host smart-6f27e9c0-09af-4394-9a0c-1d88693c0c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449040324 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_in_out_inverted.1449040324
Directory /workspace/41.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_access_test.2087734841
Short name T400
Test name
Test status
Simulation time 2191828105 ps
CPU time 5.94 seconds
Started Mar 24 01:16:16 PM PDT 24
Finished Mar 24 01:16:22 PM PDT 24
Peak memory 202060 kb
Host smart-0ffff1cb-b61a-48df-b7ca-158dcf20df51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087734841 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_access_test.2087734841
Directory /workspace/41.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_override_test.3147153339
Short name T683
Test name
Test status
Simulation time 2535311257 ps
CPU time 1.78 seconds
Started Mar 24 01:16:15 PM PDT 24
Finished Mar 24 01:16:17 PM PDT 24
Peak memory 201976 kb
Host smart-80509342-130f-4fd5-bb4e-bfc2e5535c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147153339 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_override_test.3147153339
Directory /workspace/41.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_smoke.3070312046
Short name T640
Test name
Test status
Simulation time 2119250578 ps
CPU time 3.65 seconds
Started Mar 24 01:16:09 PM PDT 24
Finished Mar 24 01:16:13 PM PDT 24
Peak memory 201936 kb
Host smart-dce7043e-fcd8-4b39-9ebb-030a698929a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070312046 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_smoke.3070312046
Directory /workspace/41.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all.2215167893
Short name T386
Test name
Test status
Simulation time 198473607767 ps
CPU time 71.98 seconds
Started Mar 24 01:16:29 PM PDT 24
Finished Mar 24 01:17:42 PM PDT 24
Peak memory 202356 kb
Host smart-3c6e85a2-f2ea-4ec8-b34a-f35d479404ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215167893 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_s
tress_all.2215167893
Directory /workspace/41.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.634387152
Short name T140
Test name
Test status
Simulation time 78409217672 ps
CPU time 21.23 seconds
Started Mar 24 01:16:25 PM PDT 24
Finished Mar 24 01:16:46 PM PDT 24
Peak memory 210356 kb
Host smart-5b9eaf89-f416-4bdc-a162-a07c4bcfd3f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634387152 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_stress_all_with_rand_reset.634387152
Directory /workspace/41.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.1772562310
Short name T219
Test name
Test status
Simulation time 5242525384 ps
CPU time 2.11 seconds
Started Mar 24 01:16:34 PM PDT 24
Finished Mar 24 01:16:36 PM PDT 24
Peak memory 202068 kb
Host smart-974dc70b-29a1-4647-9741-7d59030c954d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772562310 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_
ctrl_ultra_low_pwr.1772562310
Directory /workspace/41.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_alert_test.1221797686
Short name T579
Test name
Test status
Simulation time 2040531552 ps
CPU time 2.04 seconds
Started Mar 24 01:16:17 PM PDT 24
Finished Mar 24 01:16:19 PM PDT 24
Peak memory 202068 kb
Host smart-657a8b3d-9a9d-43ba-9f16-655e3d646cbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221797686 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_alert_te
st.1221797686
Directory /workspace/42.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.184638275
Short name T777
Test name
Test status
Simulation time 3540039870 ps
CPU time 2.12 seconds
Started Mar 24 01:16:26 PM PDT 24
Finished Mar 24 01:16:28 PM PDT 24
Peak memory 202108 kb
Host smart-51e0fcb0-9342-40dd-b524-4854b7fefd36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184638275 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_auto_blk_key_output.184638275
Directory /workspace/42.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect.3013787459
Short name T761
Test name
Test status
Simulation time 144929380420 ps
CPU time 284.02 seconds
Started Mar 24 01:16:19 PM PDT 24
Finished Mar 24 01:21:03 PM PDT 24
Peak memory 202260 kb
Host smart-aa9b6299-25cd-46e7-98b9-906068d31c4d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013787459 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_c
trl_combo_detect.3013787459
Directory /workspace/42.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.3181056428
Short name T708
Test name
Test status
Simulation time 2541900023 ps
CPU time 6.69 seconds
Started Mar 24 01:16:17 PM PDT 24
Finished Mar 24 01:16:24 PM PDT 24
Peak memory 202008 kb
Host smart-e33fd0b7-4aa2-4756-b4f3-4d9656f1f598
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181056428 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_
ctrl_ec_pwr_on_rst.3181056428
Directory /workspace/42.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_edge_detect.2930798701
Short name T637
Test name
Test status
Simulation time 4495630301 ps
CPU time 1.45 seconds
Started Mar 24 01:16:25 PM PDT 24
Finished Mar 24 01:16:26 PM PDT 24
Peak memory 202124 kb
Host smart-3d919df6-2b71-42ac-83d7-96398027f0ba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930798701 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ct
rl_edge_detect.2930798701
Directory /workspace/42.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.1146878796
Short name T634
Test name
Test status
Simulation time 2610547085 ps
CPU time 7.46 seconds
Started Mar 24 01:16:14 PM PDT 24
Finished Mar 24 01:16:22 PM PDT 24
Peak memory 202052 kb
Host smart-55640c7f-b583-4c00-a624-3b690a99af19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146878796 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_flash_wr_prot_out.1146878796
Directory /workspace/42.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.3493548585
Short name T539
Test name
Test status
Simulation time 2472320082 ps
CPU time 4.42 seconds
Started Mar 24 01:16:17 PM PDT 24
Finished Mar 24 01:16:22 PM PDT 24
Peak memory 202060 kb
Host smart-3cf3db15-2f13-48ae-b0a6-f35e23ec687a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493548585 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_in_out_inverted.3493548585
Directory /workspace/42.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_access_test.3832145968
Short name T401
Test name
Test status
Simulation time 2078551717 ps
CPU time 2.05 seconds
Started Mar 24 01:16:18 PM PDT 24
Finished Mar 24 01:16:20 PM PDT 24
Peak memory 201928 kb
Host smart-3ccb5b50-dc78-403e-b26e-cadc7ae80a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832145968 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_access_test.3832145968
Directory /workspace/42.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_override_test.4186669406
Short name T416
Test name
Test status
Simulation time 2524104666 ps
CPU time 2.43 seconds
Started Mar 24 01:16:14 PM PDT 24
Finished Mar 24 01:16:17 PM PDT 24
Peak memory 202060 kb
Host smart-5ece526e-58d1-4e5d-81e3-c56ebca50e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186669406 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_override_test.4186669406
Directory /workspace/42.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_smoke.3554877571
Short name T529
Test name
Test status
Simulation time 2214085047 ps
CPU time 0.91 seconds
Started Mar 24 01:16:25 PM PDT 24
Finished Mar 24 01:16:26 PM PDT 24
Peak memory 202036 kb
Host smart-8058ab24-3b93-4dd7-bd14-80b88a5dc950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554877571 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_smoke.3554877571
Directory /workspace/42.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all.1190462233
Short name T475
Test name
Test status
Simulation time 8497865642 ps
CPU time 22.79 seconds
Started Mar 24 01:16:23 PM PDT 24
Finished Mar 24 01:16:47 PM PDT 24
Peak memory 202104 kb
Host smart-a16414a6-c22c-494d-a1cc-37585cde6df1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190462233 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_s
tress_all.1190462233
Directory /workspace/42.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.3123226787
Short name T135
Test name
Test status
Simulation time 7178406793 ps
CPU time 7.59 seconds
Started Mar 24 01:16:17 PM PDT 24
Finished Mar 24 01:16:25 PM PDT 24
Peak memory 202080 kb
Host smart-1a57fbe2-edeb-4d8d-92ef-9c374c904344
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123226787 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_
ctrl_ultra_low_pwr.3123226787
Directory /workspace/42.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_alert_test.2286766142
Short name T227
Test name
Test status
Simulation time 2059255561 ps
CPU time 1.57 seconds
Started Mar 24 01:16:22 PM PDT 24
Finished Mar 24 01:16:23 PM PDT 24
Peak memory 202064 kb
Host smart-1f738891-7271-4cb9-8282-a83a77f11ef1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286766142 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_alert_te
st.2286766142
Directory /workspace/43.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.3528910186
Short name T569
Test name
Test status
Simulation time 3421280812 ps
CPU time 9.36 seconds
Started Mar 24 01:16:25 PM PDT 24
Finished Mar 24 01:16:35 PM PDT 24
Peak memory 202104 kb
Host smart-acba805e-72b5-4c0c-b11f-24a09d21dcea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528910186 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_auto_blk_key_output.3
528910186
Directory /workspace/43.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect.2013102426
Short name T378
Test name
Test status
Simulation time 72821504403 ps
CPU time 101.88 seconds
Started Mar 24 01:16:22 PM PDT 24
Finished Mar 24 01:18:04 PM PDT 24
Peak memory 202260 kb
Host smart-10265e5b-25cc-4bc2-abbe-cf079c48cef6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013102426 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_c
trl_combo_detect.2013102426
Directory /workspace/43.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.962635211
Short name T372
Test name
Test status
Simulation time 107879423576 ps
CPU time 297.41 seconds
Started Mar 24 01:16:29 PM PDT 24
Finished Mar 24 01:21:26 PM PDT 24
Peak memory 202140 kb
Host smart-cffcd0df-6d33-4e59-aef3-c140969452ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962635211 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect_wi
th_pre_cond.962635211
Directory /workspace/43.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.3365536323
Short name T129
Test name
Test status
Simulation time 2617339871 ps
CPU time 7.16 seconds
Started Mar 24 01:16:20 PM PDT 24
Finished Mar 24 01:16:27 PM PDT 24
Peak memory 202048 kb
Host smart-ff9ade70-0b87-42ce-a70e-7e2cd3ec7afb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365536323 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_
ctrl_ec_pwr_on_rst.3365536323
Directory /workspace/43.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_edge_detect.2878860629
Short name T187
Test name
Test status
Simulation time 2620506406 ps
CPU time 7.4 seconds
Started Mar 24 01:16:20 PM PDT 24
Finished Mar 24 01:16:27 PM PDT 24
Peak memory 202068 kb
Host smart-57a16658-5628-4360-9470-97381e6b6076
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878860629 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ct
rl_edge_detect.2878860629
Directory /workspace/43.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.2720860381
Short name T407
Test name
Test status
Simulation time 2611707169 ps
CPU time 7.74 seconds
Started Mar 24 01:16:16 PM PDT 24
Finished Mar 24 01:16:24 PM PDT 24
Peak memory 202072 kb
Host smart-a65571ce-a8ac-414a-8765-d3c046cf6941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720860381 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_flash_wr_prot_out.2720860381
Directory /workspace/43.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.2688054623
Short name T65
Test name
Test status
Simulation time 2530007950 ps
CPU time 1.39 seconds
Started Mar 24 01:16:18 PM PDT 24
Finished Mar 24 01:16:19 PM PDT 24
Peak memory 202052 kb
Host smart-3f75817d-1949-437a-a641-287d9047395a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688054623 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_in_out_inverted.2688054623
Directory /workspace/43.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_access_test.766824390
Short name T591
Test name
Test status
Simulation time 2129542317 ps
CPU time 6.15 seconds
Started Mar 24 01:16:19 PM PDT 24
Finished Mar 24 01:16:26 PM PDT 24
Peak memory 201952 kb
Host smart-cce609db-b88c-4edd-9263-77a8aef6b92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766824390 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_access_test.766824390
Directory /workspace/43.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_override_test.643168412
Short name T746
Test name
Test status
Simulation time 2525860967 ps
CPU time 2.42 seconds
Started Mar 24 01:16:27 PM PDT 24
Finished Mar 24 01:16:30 PM PDT 24
Peak memory 202080 kb
Host smart-61d9b096-0d2d-4c97-92fe-1d2b6f4a4336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643168412 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_override_test.643168412
Directory /workspace/43.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_smoke.686460485
Short name T180
Test name
Test status
Simulation time 2108885295 ps
CPU time 5.75 seconds
Started Mar 24 01:16:19 PM PDT 24
Finished Mar 24 01:16:25 PM PDT 24
Peak memory 201924 kb
Host smart-fd77ef56-c9f8-423e-ac23-0ba786dacf6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686460485 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_smoke.686460485
Directory /workspace/43.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all.1017207267
Short name T185
Test name
Test status
Simulation time 1316991545114 ps
CPU time 855.5 seconds
Started Mar 24 01:16:19 PM PDT 24
Finished Mar 24 01:30:35 PM PDT 24
Peak memory 202044 kb
Host smart-0bfb204c-abf9-4849-9747-c0f4bfb1cb46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017207267 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_s
tress_all.1017207267
Directory /workspace/43.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.2582600507
Short name T94
Test name
Test status
Simulation time 117394505919 ps
CPU time 298.15 seconds
Started Mar 24 01:16:24 PM PDT 24
Finished Mar 24 01:21:22 PM PDT 24
Peak memory 210684 kb
Host smart-18b6ed73-478b-45f2-ba31-976e18191e20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582600507 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_stress_all_with_rand_reset.2582600507
Directory /workspace/43.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.69923111
Short name T299
Test name
Test status
Simulation time 3836147449 ps
CPU time 2.21 seconds
Started Mar 24 01:16:30 PM PDT 24
Finished Mar 24 01:16:32 PM PDT 24
Peak memory 202056 kb
Host smart-c6a8dc94-1cf7-4c09-bd3c-05baf6925275
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69923111 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ct
rl_ultra_low_pwr.69923111
Directory /workspace/43.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_alert_test.843052141
Short name T488
Test name
Test status
Simulation time 2133089899 ps
CPU time 0.93 seconds
Started Mar 24 01:16:21 PM PDT 24
Finished Mar 24 01:16:22 PM PDT 24
Peak memory 202072 kb
Host smart-5fdb1587-6659-4e5b-a0c3-b75536994fd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843052141 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_alert_tes
t.843052141
Directory /workspace/44.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.398031715
Short name T51
Test name
Test status
Simulation time 3572133124 ps
CPU time 1.57 seconds
Started Mar 24 01:16:32 PM PDT 24
Finished Mar 24 01:16:33 PM PDT 24
Peak memory 202100 kb
Host smart-2163a8be-722e-4bde-9707-052d6be8db71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398031715 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_auto_blk_key_output.398031715
Directory /workspace/44.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect.2186892082
Short name T350
Test name
Test status
Simulation time 68052610385 ps
CPU time 85.5 seconds
Started Mar 24 01:16:20 PM PDT 24
Finished Mar 24 01:17:46 PM PDT 24
Peak memory 202304 kb
Host smart-cd3f5aac-ae9c-403c-804c-2206def97d4d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186892082 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_c
trl_combo_detect.2186892082
Directory /workspace/44.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.4128194383
Short name T29
Test name
Test status
Simulation time 28088771342 ps
CPU time 35.98 seconds
Started Mar 24 01:16:26 PM PDT 24
Finished Mar 24 01:17:02 PM PDT 24
Peak memory 202164 kb
Host smart-611aeee4-07f7-4197-83f9-6a116a6c2820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128194383 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect_w
ith_pre_cond.4128194383
Directory /workspace/44.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.2697964448
Short name T479
Test name
Test status
Simulation time 3566626170 ps
CPU time 5.29 seconds
Started Mar 24 01:16:30 PM PDT 24
Finished Mar 24 01:16:35 PM PDT 24
Peak memory 202020 kb
Host smart-45bd71b9-7caf-4ce8-8302-1c1d864aa0ae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697964448 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_
ctrl_ec_pwr_on_rst.2697964448
Directory /workspace/44.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_edge_detect.180999680
Short name T714
Test name
Test status
Simulation time 2834792445 ps
CPU time 2.59 seconds
Started Mar 24 01:16:28 PM PDT 24
Finished Mar 24 01:16:30 PM PDT 24
Peak memory 201972 kb
Host smart-1585118e-2cf6-4782-bf69-640a16174890
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180999680 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctr
l_edge_detect.180999680
Directory /workspace/44.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.3933433912
Short name T308
Test name
Test status
Simulation time 2627053480 ps
CPU time 2.41 seconds
Started Mar 24 01:16:20 PM PDT 24
Finished Mar 24 01:16:23 PM PDT 24
Peak memory 202004 kb
Host smart-93a7576a-158d-4288-a383-fa7ffc91f8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933433912 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_flash_wr_prot_out.3933433912
Directory /workspace/44.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.3882277671
Short name T666
Test name
Test status
Simulation time 2571872269 ps
CPU time 1.11 seconds
Started Mar 24 01:16:21 PM PDT 24
Finished Mar 24 01:16:23 PM PDT 24
Peak memory 202024 kb
Host smart-6ed1ef09-35de-4df0-a3a4-538e25da33b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882277671 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_in_out_inverted.3882277671
Directory /workspace/44.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_access_test.1120026019
Short name T414
Test name
Test status
Simulation time 2323201365 ps
CPU time 1.32 seconds
Started Mar 24 01:16:30 PM PDT 24
Finished Mar 24 01:16:31 PM PDT 24
Peak memory 202016 kb
Host smart-de2cf57b-0d2f-476e-8ff4-ead2671e9fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120026019 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_access_test.1120026019
Directory /workspace/44.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_override_test.2835862813
Short name T16
Test name
Test status
Simulation time 2530906823 ps
CPU time 2.27 seconds
Started Mar 24 01:16:21 PM PDT 24
Finished Mar 24 01:16:23 PM PDT 24
Peak memory 202072 kb
Host smart-ef7281ef-942f-4251-b4f4-5b3e387daa8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835862813 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_override_test.2835862813
Directory /workspace/44.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_smoke.3523408997
Short name T564
Test name
Test status
Simulation time 2131508353 ps
CPU time 2.05 seconds
Started Mar 24 01:16:22 PM PDT 24
Finished Mar 24 01:16:24 PM PDT 24
Peak memory 201940 kb
Host smart-86c7488d-59e4-4efe-b199-3486d14a4af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523408997 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_smoke.3523408997
Directory /workspace/44.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all.1836214471
Short name T692
Test name
Test status
Simulation time 8619660382 ps
CPU time 6.16 seconds
Started Mar 24 01:16:28 PM PDT 24
Finished Mar 24 01:16:34 PM PDT 24
Peak memory 202104 kb
Host smart-b83e247a-b436-4ab9-9be0-07117c370104
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836214471 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_s
tress_all.1836214471
Directory /workspace/44.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.1630173224
Short name T687
Test name
Test status
Simulation time 23439738600 ps
CPU time 57.91 seconds
Started Mar 24 01:16:31 PM PDT 24
Finished Mar 24 01:17:34 PM PDT 24
Peak memory 202480 kb
Host smart-551ba113-d766-4dcb-a389-70d59b5b3554
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630173224 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_stress_all_with_rand_reset.1630173224
Directory /workspace/44.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.75936029
Short name T500
Test name
Test status
Simulation time 4367875217 ps
CPU time 3.52 seconds
Started Mar 24 01:16:25 PM PDT 24
Finished Mar 24 01:16:28 PM PDT 24
Peak memory 202108 kb
Host smart-0b133b50-8ce2-4a63-abe3-522b5488349f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75936029 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ct
rl_ultra_low_pwr.75936029
Directory /workspace/44.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_alert_test.3168050150
Short name T655
Test name
Test status
Simulation time 2011858270 ps
CPU time 5.16 seconds
Started Mar 24 01:16:21 PM PDT 24
Finished Mar 24 01:16:27 PM PDT 24
Peak memory 201956 kb
Host smart-099b3823-92b9-4049-8bd6-8d9dee2470ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168050150 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_alert_te
st.3168050150
Directory /workspace/45.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.4224129681
Short name T171
Test name
Test status
Simulation time 3909554809 ps
CPU time 3.1 seconds
Started Mar 24 01:16:25 PM PDT 24
Finished Mar 24 01:16:29 PM PDT 24
Peak memory 202120 kb
Host smart-3ff89709-7606-4e9a-812a-e7c9b2a6b584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224129681 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_auto_blk_key_output.4
224129681
Directory /workspace/45.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect.814662556
Short name T257
Test name
Test status
Simulation time 74088137682 ps
CPU time 52.24 seconds
Started Mar 24 01:16:32 PM PDT 24
Finished Mar 24 01:17:24 PM PDT 24
Peak memory 202220 kb
Host smart-a840a67e-36e0-4e9d-a6ad-16aa88254c79
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814662556 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ct
rl_combo_detect.814662556
Directory /workspace/45.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.1266068708
Short name T520
Test name
Test status
Simulation time 27088656952 ps
CPU time 33.22 seconds
Started Mar 24 01:16:24 PM PDT 24
Finished Mar 24 01:16:58 PM PDT 24
Peak memory 201928 kb
Host smart-069f49cc-117c-4895-8ec0-7917e2c8a1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266068708 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect_w
ith_pre_cond.1266068708
Directory /workspace/45.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.1900954919
Short name T431
Test name
Test status
Simulation time 4997173464 ps
CPU time 13 seconds
Started Mar 24 01:16:21 PM PDT 24
Finished Mar 24 01:16:34 PM PDT 24
Peak memory 202052 kb
Host smart-4a686f87-7281-4fdc-9d43-daab9a59ff5e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900954919 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_
ctrl_ec_pwr_on_rst.1900954919
Directory /workspace/45.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_edge_detect.440232515
Short name T190
Test name
Test status
Simulation time 3470268344 ps
CPU time 2.19 seconds
Started Mar 24 01:16:31 PM PDT 24
Finished Mar 24 01:16:33 PM PDT 24
Peak memory 202060 kb
Host smart-ee632126-a29c-4082-a7d8-895d516bc8f0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440232515 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctr
l_edge_detect.440232515
Directory /workspace/45.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.2470743205
Short name T442
Test name
Test status
Simulation time 2612323382 ps
CPU time 4.06 seconds
Started Mar 24 01:16:20 PM PDT 24
Finished Mar 24 01:16:24 PM PDT 24
Peak memory 202004 kb
Host smart-278d7576-a223-4562-a667-d9af904f4a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470743205 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_flash_wr_prot_out.2470743205
Directory /workspace/45.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.608753323
Short name T478
Test name
Test status
Simulation time 2450114376 ps
CPU time 6.93 seconds
Started Mar 24 01:16:19 PM PDT 24
Finished Mar 24 01:16:27 PM PDT 24
Peak memory 202068 kb
Host smart-528e5219-8a92-4e2c-a133-36e169e411aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608753323 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_in_out_inverted.608753323
Directory /workspace/45.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_access_test.308779368
Short name T307
Test name
Test status
Simulation time 2102183993 ps
CPU time 3.51 seconds
Started Mar 24 01:16:24 PM PDT 24
Finished Mar 24 01:16:28 PM PDT 24
Peak memory 201500 kb
Host smart-68e5d1ac-1f54-49a2-9d5a-7d0af392655f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308779368 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_access_test.308779368
Directory /workspace/45.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_override_test.3136917729
Short name T415
Test name
Test status
Simulation time 2519136142 ps
CPU time 4.32 seconds
Started Mar 24 01:16:30 PM PDT 24
Finished Mar 24 01:16:35 PM PDT 24
Peak memory 201952 kb
Host smart-8b25b8b9-5495-4dc3-b867-bf7926688ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136917729 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_override_test.3136917729
Directory /workspace/45.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_smoke.974306722
Short name T302
Test name
Test status
Simulation time 2109876835 ps
CPU time 5.94 seconds
Started Mar 24 01:16:26 PM PDT 24
Finished Mar 24 01:16:32 PM PDT 24
Peak memory 201980 kb
Host smart-acba8784-7eae-4b4d-88f8-13e92c9cf9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974306722 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_smoke.974306722
Directory /workspace/45.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all.3260259162
Short name T43
Test name
Test status
Simulation time 16049014395 ps
CPU time 36.21 seconds
Started Mar 24 01:16:24 PM PDT 24
Finished Mar 24 01:17:01 PM PDT 24
Peak memory 202100 kb
Host smart-9292cb6c-65e4-4a13-a252-c5e719fc817f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260259162 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_s
tress_all.3260259162
Directory /workspace/45.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.2977477396
Short name T123
Test name
Test status
Simulation time 28377792342 ps
CPU time 66.95 seconds
Started Mar 24 01:16:24 PM PDT 24
Finished Mar 24 01:17:31 PM PDT 24
Peak memory 211992 kb
Host smart-15ca872f-0c68-407f-a0e0-504c463baeb4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977477396 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_stress_all_with_rand_reset.2977477396
Directory /workspace/45.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.3867518626
Short name T486
Test name
Test status
Simulation time 12946803965 ps
CPU time 4.99 seconds
Started Mar 24 01:16:26 PM PDT 24
Finished Mar 24 01:16:31 PM PDT 24
Peak memory 202136 kb
Host smart-2eb3bbb4-5197-4fa3-82bb-52d9c78b2687
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867518626 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_
ctrl_ultra_low_pwr.3867518626
Directory /workspace/45.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_alert_test.4022378478
Short name T312
Test name
Test status
Simulation time 2032071291 ps
CPU time 1.84 seconds
Started Mar 24 01:16:34 PM PDT 24
Finished Mar 24 01:16:36 PM PDT 24
Peak memory 201964 kb
Host smart-f4f81048-2f05-4bd3-9675-38256a785d36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022378478 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_alert_te
st.4022378478
Directory /workspace/46.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.3516791889
Short name T521
Test name
Test status
Simulation time 4037046053 ps
CPU time 5.93 seconds
Started Mar 24 01:16:34 PM PDT 24
Finished Mar 24 01:16:40 PM PDT 24
Peak memory 201984 kb
Host smart-c7945120-57a6-44f2-b631-a345cd223f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516791889 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_auto_blk_key_output.3
516791889
Directory /workspace/46.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect.2810401095
Short name T96
Test name
Test status
Simulation time 71372896385 ps
CPU time 47.36 seconds
Started Mar 24 01:16:30 PM PDT 24
Finished Mar 24 01:17:17 PM PDT 24
Peak memory 202300 kb
Host smart-46e9fd13-42e4-4c47-978b-921a28c8c26e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810401095 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_c
trl_combo_detect.2810401095
Directory /workspace/46.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.969110725
Short name T89
Test name
Test status
Simulation time 25116515035 ps
CPU time 14.81 seconds
Started Mar 24 01:16:34 PM PDT 24
Finished Mar 24 01:16:49 PM PDT 24
Peak memory 202272 kb
Host smart-ed378fd6-c863-400b-a4a5-f1ba26d14b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969110725 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_combo_detect_wi
th_pre_cond.969110725
Directory /workspace/46.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.2372370240
Short name T393
Test name
Test status
Simulation time 2853699655 ps
CPU time 7.94 seconds
Started Mar 24 01:16:27 PM PDT 24
Finished Mar 24 01:16:35 PM PDT 24
Peak memory 202004 kb
Host smart-605d88e6-c0b8-4d91-88f6-bf73bf34dc7a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372370240 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_
ctrl_ec_pwr_on_rst.2372370240
Directory /workspace/46.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_edge_detect.3193711741
Short name T197
Test name
Test status
Simulation time 3138722956 ps
CPU time 2.65 seconds
Started Mar 24 01:16:28 PM PDT 24
Finished Mar 24 01:16:31 PM PDT 24
Peak memory 202036 kb
Host smart-dd60c482-619a-48b2-88c9-087dffd9bc20
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193711741 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ct
rl_edge_detect.3193711741
Directory /workspace/46.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.612342614
Short name T654
Test name
Test status
Simulation time 2622285138 ps
CPU time 2.35 seconds
Started Mar 24 01:16:25 PM PDT 24
Finished Mar 24 01:16:27 PM PDT 24
Peak memory 201844 kb
Host smart-ca026b27-ddb1-4e7c-8a72-1bbb1560f021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612342614 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_flash_wr_prot_out.612342614
Directory /workspace/46.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.4006617207
Short name T24
Test name
Test status
Simulation time 2493436249 ps
CPU time 2.2 seconds
Started Mar 24 01:16:30 PM PDT 24
Finished Mar 24 01:16:32 PM PDT 24
Peak memory 202044 kb
Host smart-2ad8394f-2227-4402-b4da-f8ae43364644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006617207 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_in_out_inverted.4006617207
Directory /workspace/46.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_access_test.3139299395
Short name T429
Test name
Test status
Simulation time 2138078093 ps
CPU time 5.97 seconds
Started Mar 24 01:16:25 PM PDT 24
Finished Mar 24 01:16:32 PM PDT 24
Peak memory 201932 kb
Host smart-73aa905d-f74f-4d70-92d6-ce9305986d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139299395 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_access_test.3139299395
Directory /workspace/46.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_override_test.1277938740
Short name T297
Test name
Test status
Simulation time 2529069136 ps
CPU time 2.45 seconds
Started Mar 24 01:16:28 PM PDT 24
Finished Mar 24 01:16:31 PM PDT 24
Peak memory 202024 kb
Host smart-e53d8aa0-bf39-46cb-b780-54667d85f886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277938740 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_override_test.1277938740
Directory /workspace/46.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_smoke.4146395882
Short name T765
Test name
Test status
Simulation time 2110115773 ps
CPU time 5.89 seconds
Started Mar 24 01:16:30 PM PDT 24
Finished Mar 24 01:16:36 PM PDT 24
Peak memory 201900 kb
Host smart-dc06f1b8-bcf7-4750-bde6-5743e32c2fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146395882 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_smoke.4146395882
Directory /workspace/46.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all.893196304
Short name T177
Test name
Test status
Simulation time 13645252018 ps
CPU time 8.53 seconds
Started Mar 24 01:16:37 PM PDT 24
Finished Mar 24 01:16:46 PM PDT 24
Peak memory 202084 kb
Host smart-324cd7fa-2dda-46cd-a570-389dbc900b49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893196304 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_st
ress_all.893196304
Directory /workspace/46.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.676215417
Short name T124
Test name
Test status
Simulation time 62515662282 ps
CPU time 15.82 seconds
Started Mar 24 01:16:25 PM PDT 24
Finished Mar 24 01:16:41 PM PDT 24
Peak memory 218612 kb
Host smart-6a072830-7c3c-419d-9335-8ba5e59218c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676215417 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_stress_all_with_rand_reset.676215417
Directory /workspace/46.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.863539612
Short name T492
Test name
Test status
Simulation time 3088777268 ps
CPU time 1.98 seconds
Started Mar 24 01:16:27 PM PDT 24
Finished Mar 24 01:16:29 PM PDT 24
Peak memory 202076 kb
Host smart-f3558a6c-e470-4939-b567-58f5828e3561
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863539612 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_c
trl_ultra_low_pwr.863539612
Directory /workspace/46.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_alert_test.3032890185
Short name T55
Test name
Test status
Simulation time 2010710230 ps
CPU time 5.46 seconds
Started Mar 24 01:16:30 PM PDT 24
Finished Mar 24 01:16:36 PM PDT 24
Peak memory 202076 kb
Host smart-616c0eb5-bb7d-4557-bc9e-c268f5b9369a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032890185 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_alert_te
st.3032890185
Directory /workspace/47.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.2713147750
Short name T670
Test name
Test status
Simulation time 3411266570 ps
CPU time 2.53 seconds
Started Mar 24 01:16:37 PM PDT 24
Finished Mar 24 01:16:40 PM PDT 24
Peak memory 202060 kb
Host smart-edfb7cc0-7913-49df-a6d3-2cbf0c2c7602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713147750 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_auto_blk_key_output.2
713147750
Directory /workspace/47.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect.3757454189
Short name T374
Test name
Test status
Simulation time 52066277008 ps
CPU time 66 seconds
Started Mar 24 01:16:32 PM PDT 24
Finished Mar 24 01:17:38 PM PDT 24
Peak memory 202280 kb
Host smart-a7e7f17f-104b-4569-bdeb-3dfc2f023a77
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757454189 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_c
trl_combo_detect.3757454189
Directory /workspace/47.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.2776659939
Short name T757
Test name
Test status
Simulation time 143062329519 ps
CPU time 65.66 seconds
Started Mar 24 01:16:23 PM PDT 24
Finished Mar 24 01:17:29 PM PDT 24
Peak memory 202188 kb
Host smart-ec209d66-bc5c-42b3-a9b8-3dbbda1ab2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776659939 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect_w
ith_pre_cond.2776659939
Directory /workspace/47.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.3022514863
Short name T510
Test name
Test status
Simulation time 3659646912 ps
CPU time 10.1 seconds
Started Mar 24 01:16:39 PM PDT 24
Finished Mar 24 01:16:49 PM PDT 24
Peak memory 202024 kb
Host smart-1710a52b-d88c-4514-8152-22f4447dda11
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022514863 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_
ctrl_ec_pwr_on_rst.3022514863
Directory /workspace/47.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_edge_detect.2080324835
Short name T36
Test name
Test status
Simulation time 2631788234 ps
CPU time 2.06 seconds
Started Mar 24 01:16:24 PM PDT 24
Finished Mar 24 01:16:27 PM PDT 24
Peak memory 202048 kb
Host smart-fb6e7ac8-ec92-4cde-a1db-03c5309d7cd7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080324835 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ct
rl_edge_detect.2080324835
Directory /workspace/47.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.3940456759
Short name T545
Test name
Test status
Simulation time 2616655610 ps
CPU time 3.99 seconds
Started Mar 24 01:16:25 PM PDT 24
Finished Mar 24 01:16:30 PM PDT 24
Peak memory 202080 kb
Host smart-acbb8897-7dc4-46b8-9912-8037db87bf8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940456759 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_flash_wr_prot_out.3940456759
Directory /workspace/47.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.1837543096
Short name T275
Test name
Test status
Simulation time 2496206782 ps
CPU time 2.22 seconds
Started Mar 24 01:16:34 PM PDT 24
Finished Mar 24 01:16:36 PM PDT 24
Peak memory 202036 kb
Host smart-5288fb6a-b013-4ed9-9c6a-0fd98cff9049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837543096 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_in_out_inverted.1837543096
Directory /workspace/47.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_access_test.3209464280
Short name T659
Test name
Test status
Simulation time 2044678437 ps
CPU time 1.98 seconds
Started Mar 24 01:16:25 PM PDT 24
Finished Mar 24 01:16:27 PM PDT 24
Peak memory 201932 kb
Host smart-1a98b656-2266-445a-83aa-822c0cdbb5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209464280 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_access_test.3209464280
Directory /workspace/47.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_override_test.495879991
Short name T672
Test name
Test status
Simulation time 2510468943 ps
CPU time 7.16 seconds
Started Mar 24 01:16:32 PM PDT 24
Finished Mar 24 01:16:39 PM PDT 24
Peak memory 202064 kb
Host smart-9ba0d26b-283f-4027-baa2-c41a699668fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495879991 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_override_test.495879991
Directory /workspace/47.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_smoke.2521502634
Short name T778
Test name
Test status
Simulation time 2110201276 ps
CPU time 5.75 seconds
Started Mar 24 01:16:34 PM PDT 24
Finished Mar 24 01:16:40 PM PDT 24
Peak memory 201836 kb
Host smart-632ac3f5-b0e7-4b91-aa0f-2c686051ca0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521502634 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_smoke.2521502634
Directory /workspace/47.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all.3384301036
Short name T245
Test name
Test status
Simulation time 50698552947 ps
CPU time 130.33 seconds
Started Mar 24 01:16:36 PM PDT 24
Finished Mar 24 01:18:46 PM PDT 24
Peak memory 202304 kb
Host smart-a209c3eb-0f08-45c3-ace4-040ed30739e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384301036 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_s
tress_all.3384301036
Directory /workspace/47.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.3984308663
Short name T101
Test name
Test status
Simulation time 4653359394608 ps
CPU time 122.78 seconds
Started Mar 24 01:16:37 PM PDT 24
Finished Mar 24 01:18:40 PM PDT 24
Peak memory 202060 kb
Host smart-ee86c450-1efd-4987-b87e-4679c89bbbad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984308663 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_
ctrl_ultra_low_pwr.3984308663
Directory /workspace/47.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_alert_test.1594328191
Short name T704
Test name
Test status
Simulation time 2013004668 ps
CPU time 6.03 seconds
Started Mar 24 01:16:37 PM PDT 24
Finished Mar 24 01:16:43 PM PDT 24
Peak memory 202084 kb
Host smart-6b681e6e-cf3f-45d9-835f-f5a7873154f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594328191 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_alert_te
st.1594328191
Directory /workspace/48.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.1526481548
Short name T49
Test name
Test status
Simulation time 4159838567 ps
CPU time 11.93 seconds
Started Mar 24 01:16:28 PM PDT 24
Finished Mar 24 01:16:40 PM PDT 24
Peak memory 202080 kb
Host smart-88654e6a-7f63-45f4-a55b-6d72c4f451fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526481548 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_auto_blk_key_output.1
526481548
Directory /workspace/48.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect.3458879162
Short name T233
Test name
Test status
Simulation time 118995223326 ps
CPU time 329.81 seconds
Started Mar 24 01:16:36 PM PDT 24
Finished Mar 24 01:22:06 PM PDT 24
Peak memory 202048 kb
Host smart-63eb4f82-bb6f-412c-b0cb-baeb2008ac60
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458879162 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_c
trl_combo_detect.3458879162
Directory /workspace/48.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.630144810
Short name T459
Test name
Test status
Simulation time 34555289815 ps
CPU time 44.72 seconds
Started Mar 24 01:16:25 PM PDT 24
Finished Mar 24 01:17:10 PM PDT 24
Peak memory 202240 kb
Host smart-56a79922-892d-44b2-a95a-b3bd809b3a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630144810 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect_wi
th_pre_cond.630144810
Directory /workspace/48.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.3035983218
Short name T286
Test name
Test status
Simulation time 3791504654 ps
CPU time 1.47 seconds
Started Mar 24 01:16:27 PM PDT 24
Finished Mar 24 01:16:29 PM PDT 24
Peak memory 202004 kb
Host smart-36f668de-70bb-4344-a792-ffd7b1e88967
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035983218 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_
ctrl_ec_pwr_on_rst.3035983218
Directory /workspace/48.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_edge_detect.2969996110
Short name T632
Test name
Test status
Simulation time 3215438659 ps
CPU time 2.42 seconds
Started Mar 24 01:16:32 PM PDT 24
Finished Mar 24 01:16:35 PM PDT 24
Peak memory 202040 kb
Host smart-fd11d8e4-6a37-41ef-9673-5ff1e323c14f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969996110 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ct
rl_edge_detect.2969996110
Directory /workspace/48.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.486181464
Short name T651
Test name
Test status
Simulation time 2622837594 ps
CPU time 2.24 seconds
Started Mar 24 01:16:37 PM PDT 24
Finished Mar 24 01:16:40 PM PDT 24
Peak memory 202052 kb
Host smart-0e58097c-2154-48d8-864a-0a99a7bd5467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486181464 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_flash_wr_prot_out.486181464
Directory /workspace/48.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.1768358484
Short name T25
Test name
Test status
Simulation time 2466884707 ps
CPU time 3.3 seconds
Started Mar 24 01:16:38 PM PDT 24
Finished Mar 24 01:16:42 PM PDT 24
Peak memory 202052 kb
Host smart-374253fd-85da-494c-b25e-119592b82ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768358484 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_in_out_inverted.1768358484
Directory /workspace/48.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_access_test.1568440724
Short name T480
Test name
Test status
Simulation time 2133995218 ps
CPU time 1.82 seconds
Started Mar 24 01:16:29 PM PDT 24
Finished Mar 24 01:16:31 PM PDT 24
Peak memory 201896 kb
Host smart-b0135286-f393-4f91-a8cb-4d7681cd4611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568440724 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_access_test.1568440724
Directory /workspace/48.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_override_test.3400839711
Short name T707
Test name
Test status
Simulation time 2512998283 ps
CPU time 6.61 seconds
Started Mar 24 01:16:29 PM PDT 24
Finished Mar 24 01:16:35 PM PDT 24
Peak memory 202024 kb
Host smart-281f9b36-2583-45a2-9b26-fc1e8e5ba40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400839711 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_override_test.3400839711
Directory /workspace/48.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_smoke.3892789771
Short name T193
Test name
Test status
Simulation time 2128938494 ps
CPU time 1.58 seconds
Started Mar 24 01:16:36 PM PDT 24
Finished Mar 24 01:16:38 PM PDT 24
Peak memory 201712 kb
Host smart-b43334ef-af87-4a8e-a9d5-7d2221e6d474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892789771 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_smoke.3892789771
Directory /workspace/48.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all.1948428730
Short name T98
Test name
Test status
Simulation time 140533560523 ps
CPU time 195.02 seconds
Started Mar 24 01:16:34 PM PDT 24
Finished Mar 24 01:19:49 PM PDT 24
Peak memory 202112 kb
Host smart-b8e56260-9cd0-4a48-8eec-7a150769438c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948428730 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_s
tress_all.1948428730
Directory /workspace/48.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.4131651226
Short name T93
Test name
Test status
Simulation time 59132697797 ps
CPU time 45.09 seconds
Started Mar 24 01:16:39 PM PDT 24
Finished Mar 24 01:17:24 PM PDT 24
Peak memory 210612 kb
Host smart-5b2bf83c-de89-40a1-8be6-70111121a61d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131651226 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_stress_all_with_rand_reset.4131651226
Directory /workspace/48.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.4222113675
Short name T83
Test name
Test status
Simulation time 7507932373 ps
CPU time 2.84 seconds
Started Mar 24 01:16:37 PM PDT 24
Finished Mar 24 01:16:40 PM PDT 24
Peak memory 202052 kb
Host smart-e6a0c942-58ed-425d-976a-cf2e73ad3514
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222113675 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_
ctrl_ultra_low_pwr.4222113675
Directory /workspace/48.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_alert_test.3114878780
Short name T721
Test name
Test status
Simulation time 2064755874 ps
CPU time 1.27 seconds
Started Mar 24 01:16:35 PM PDT 24
Finished Mar 24 01:16:36 PM PDT 24
Peak memory 202064 kb
Host smart-fa835b5e-680a-484a-b768-0f65baf1c8ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114878780 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_alert_te
st.3114878780
Directory /workspace/49.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.644104670
Short name T26
Test name
Test status
Simulation time 2919570177 ps
CPU time 1.23 seconds
Started Mar 24 01:16:34 PM PDT 24
Finished Mar 24 01:16:35 PM PDT 24
Peak memory 202108 kb
Host smart-6f3e150c-8664-4cc8-88a2-24df1c01540d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644104670 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_auto_blk_key_output.644104670
Directory /workspace/49.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect.536318239
Short name T252
Test name
Test status
Simulation time 38322514083 ps
CPU time 27.94 seconds
Started Mar 24 01:16:38 PM PDT 24
Finished Mar 24 01:17:06 PM PDT 24
Peak memory 202216 kb
Host smart-4c3a0ea2-1558-44f5-a25b-7b13dd0bd2be
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536318239 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ct
rl_combo_detect.536318239
Directory /workspace/49.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.739040940
Short name T332
Test name
Test status
Simulation time 68877480030 ps
CPU time 88.97 seconds
Started Mar 24 01:16:31 PM PDT 24
Finished Mar 24 01:18:00 PM PDT 24
Peak memory 202284 kb
Host smart-4dcaa6c9-fbd9-462f-a810-134530d1858d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739040940 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect_wi
th_pre_cond.739040940
Directory /workspace/49.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.1128546763
Short name T596
Test name
Test status
Simulation time 3615874314 ps
CPU time 10.3 seconds
Started Mar 24 01:16:39 PM PDT 24
Finished Mar 24 01:16:50 PM PDT 24
Peak memory 202024 kb
Host smart-71232f56-c1e5-47cf-b21f-5702b8fd3e81
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128546763 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_
ctrl_ec_pwr_on_rst.1128546763
Directory /workspace/49.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_edge_detect.1832793673
Short name T531
Test name
Test status
Simulation time 3163847147 ps
CPU time 2.82 seconds
Started Mar 24 01:16:32 PM PDT 24
Finished Mar 24 01:16:35 PM PDT 24
Peak memory 202084 kb
Host smart-7844ccd4-b0c9-459d-b7c1-46a09c416a0e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832793673 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ct
rl_edge_detect.1832793673
Directory /workspace/49.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.2012337200
Short name T502
Test name
Test status
Simulation time 2638068910 ps
CPU time 1.56 seconds
Started Mar 24 01:16:33 PM PDT 24
Finished Mar 24 01:16:35 PM PDT 24
Peak memory 201940 kb
Host smart-b0ffb0f3-4ba9-4292-8277-8cc85b7acb1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012337200 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_flash_wr_prot_out.2012337200
Directory /workspace/49.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.2563586954
Short name T456
Test name
Test status
Simulation time 2446699665 ps
CPU time 7.28 seconds
Started Mar 24 01:16:23 PM PDT 24
Finished Mar 24 01:16:31 PM PDT 24
Peak memory 202032 kb
Host smart-7c2c871d-51e6-425e-8b69-3f77a74276e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563586954 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_in_out_inverted.2563586954
Directory /workspace/49.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_access_test.1873753197
Short name T237
Test name
Test status
Simulation time 2050648235 ps
CPU time 5.55 seconds
Started Mar 24 01:16:38 PM PDT 24
Finished Mar 24 01:16:43 PM PDT 24
Peak memory 201904 kb
Host smart-d2d81207-da6f-4928-86c5-3266b4d3eca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873753197 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_access_test.1873753197
Directory /workspace/49.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_override_test.1999448686
Short name T636
Test name
Test status
Simulation time 2514208303 ps
CPU time 3.92 seconds
Started Mar 24 01:16:30 PM PDT 24
Finished Mar 24 01:16:34 PM PDT 24
Peak memory 202064 kb
Host smart-aadb2c46-3f3b-470d-9514-ab3b4ce6648b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999448686 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_override_test.1999448686
Directory /workspace/49.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_smoke.1900509746
Short name T406
Test name
Test status
Simulation time 2132192703 ps
CPU time 1.87 seconds
Started Mar 24 01:16:39 PM PDT 24
Finished Mar 24 01:16:41 PM PDT 24
Peak memory 201904 kb
Host smart-772cf80e-5b45-4a2c-b68a-ae9963b9f041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900509746 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_smoke.1900509746
Directory /workspace/49.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.1539909492
Short name T725
Test name
Test status
Simulation time 50074989593 ps
CPU time 131.94 seconds
Started Mar 24 01:16:31 PM PDT 24
Finished Mar 24 01:18:43 PM PDT 24
Peak memory 210452 kb
Host smart-52afb957-ec2c-4bed-a911-8cb0d87438bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539909492 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_stress_all_with_rand_reset.1539909492
Directory /workspace/49.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.2359909705
Short name T733
Test name
Test status
Simulation time 8622469468 ps
CPU time 6.99 seconds
Started Mar 24 01:16:38 PM PDT 24
Finished Mar 24 01:16:45 PM PDT 24
Peak memory 202044 kb
Host smart-276527e8-adc2-4d1e-843f-a756298076ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359909705 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_
ctrl_ultra_low_pwr.2359909705
Directory /workspace/49.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_alert_test.1898990145
Short name T736
Test name
Test status
Simulation time 2018029743 ps
CPU time 3.09 seconds
Started Mar 24 01:15:00 PM PDT 24
Finished Mar 24 01:15:03 PM PDT 24
Peak memory 202060 kb
Host smart-47108bf6-b863-424f-9e2e-7e011037682a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898990145 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_alert_tes
t.1898990145
Directory /workspace/5.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.2432064288
Short name T504
Test name
Test status
Simulation time 3436545128 ps
CPU time 2.9 seconds
Started Mar 24 01:15:05 PM PDT 24
Finished Mar 24 01:15:08 PM PDT 24
Peak memory 202132 kb
Host smart-46ac267c-cfd6-4b33-af54-12428a4edb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432064288 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_auto_blk_key_output.2432064288
Directory /workspace/5.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect.3524856681
Short name T92
Test name
Test status
Simulation time 111777308736 ps
CPU time 264.73 seconds
Started Mar 24 01:14:57 PM PDT 24
Finished Mar 24 01:19:22 PM PDT 24
Peak memory 202260 kb
Host smart-49ddc801-9b71-4143-ad09-2959b685879e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524856681 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ct
rl_combo_detect.3524856681
Directory /workspace/5.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.2572932272
Short name T224
Test name
Test status
Simulation time 110670650410 ps
CPU time 77.44 seconds
Started Mar 24 01:14:59 PM PDT 24
Finished Mar 24 01:16:16 PM PDT 24
Peak memory 202160 kb
Host smart-724bfce5-0399-4e91-bca1-528dcef02fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572932272 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect_wi
th_pre_cond.2572932272
Directory /workspace/5.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.2791100366
Short name T409
Test name
Test status
Simulation time 2634044819 ps
CPU time 2.29 seconds
Started Mar 24 01:14:57 PM PDT 24
Finished Mar 24 01:14:59 PM PDT 24
Peak memory 202040 kb
Host smart-ff37351c-809e-4a4f-bc71-ef714cba3f8a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791100366 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_ec_pwr_on_rst.2791100366
Directory /workspace/5.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_edge_detect.236754328
Short name T41
Test name
Test status
Simulation time 3923967568 ps
CPU time 1.27 seconds
Started Mar 24 01:14:59 PM PDT 24
Finished Mar 24 01:15:00 PM PDT 24
Peak memory 202052 kb
Host smart-3418e466-680e-4b0d-b761-8d9e215d52ae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236754328 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl
_edge_detect.236754328
Directory /workspace/5.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.497231617
Short name T633
Test name
Test status
Simulation time 2607500050 ps
CPU time 7.93 seconds
Started Mar 24 01:14:56 PM PDT 24
Finished Mar 24 01:15:04 PM PDT 24
Peak memory 202020 kb
Host smart-f31c3d29-7fb1-4e04-915d-8f1a98090c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497231617 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_flash_wr_prot_out.497231617
Directory /workspace/5.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.1295507758
Short name T598
Test name
Test status
Simulation time 2476578608 ps
CPU time 2.51 seconds
Started Mar 24 01:14:58 PM PDT 24
Finished Mar 24 01:15:01 PM PDT 24
Peak memory 202048 kb
Host smart-95a9f5e6-95e9-4ef0-be55-5eaa2e2e98a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295507758 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_in_out_inverted.1295507758
Directory /workspace/5.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_access_test.732830257
Short name T668
Test name
Test status
Simulation time 2124180398 ps
CPU time 3.26 seconds
Started Mar 24 01:14:59 PM PDT 24
Finished Mar 24 01:15:03 PM PDT 24
Peak memory 201908 kb
Host smart-fac62b77-7320-4e73-8895-7fc0127d524c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732830257 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_access_test.732830257
Directory /workspace/5.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_override_test.3027978517
Short name T438
Test name
Test status
Simulation time 2527127946 ps
CPU time 2.37 seconds
Started Mar 24 01:15:05 PM PDT 24
Finished Mar 24 01:15:08 PM PDT 24
Peak memory 202060 kb
Host smart-7c9805dc-74d6-4a31-a953-973dcd3a7275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027978517 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_override_test.3027978517
Directory /workspace/5.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_smoke.1389049879
Short name T427
Test name
Test status
Simulation time 2119247159 ps
CPU time 3.29 seconds
Started Mar 24 01:14:56 PM PDT 24
Finished Mar 24 01:14:59 PM PDT 24
Peak memory 201900 kb
Host smart-98c9cfec-5338-4d46-bb0a-702efa60966a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389049879 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_smoke.1389049879
Directory /workspace/5.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all.2668239449
Short name T287
Test name
Test status
Simulation time 9270487917 ps
CPU time 25.6 seconds
Started Mar 24 01:15:00 PM PDT 24
Finished Mar 24 01:15:26 PM PDT 24
Peak memory 201960 kb
Host smart-2d5087e4-b4d7-4cd4-a64a-74940e72d9b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668239449 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_st
ress_all.2668239449
Directory /workspace/5.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.1170339922
Short name T119
Test name
Test status
Simulation time 2738107277 ps
CPU time 3.06 seconds
Started Mar 24 01:14:59 PM PDT 24
Finished Mar 24 01:15:02 PM PDT 24
Peak memory 202032 kb
Host smart-58eff0d8-8522-4efd-8837-de99969d37b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170339922 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_ultra_low_pwr.1170339922
Directory /workspace/5.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.971090383
Short name T362
Test name
Test status
Simulation time 126868551384 ps
CPU time 77.37 seconds
Started Mar 24 01:16:33 PM PDT 24
Finished Mar 24 01:17:50 PM PDT 24
Peak memory 202188 kb
Host smart-388d4215-b4e2-4159-bd18-a3edb2903b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971090383 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.sysrst_ctrl_combo_detect_wi
th_pre_cond.971090383
Directory /workspace/50.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.1443540945
Short name T447
Test name
Test status
Simulation time 28860374250 ps
CPU time 19.26 seconds
Started Mar 24 01:16:32 PM PDT 24
Finished Mar 24 01:16:52 PM PDT 24
Peak memory 202312 kb
Host smart-bab5ef97-e323-473e-a34d-74bda51307c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443540945 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.sysrst_ctrl_combo_detect_w
ith_pre_cond.1443540945
Directory /workspace/51.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.1603878965
Short name T613
Test name
Test status
Simulation time 26080229106 ps
CPU time 66.45 seconds
Started Mar 24 01:16:29 PM PDT 24
Finished Mar 24 01:17:36 PM PDT 24
Peak memory 202320 kb
Host smart-db63091b-be85-4ee8-b00a-b4ef5051fd8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603878965 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.sysrst_ctrl_combo_detect_w
ith_pre_cond.1603878965
Directory /workspace/52.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.3281380858
Short name T381
Test name
Test status
Simulation time 55593463479 ps
CPU time 45.59 seconds
Started Mar 24 01:16:34 PM PDT 24
Finished Mar 24 01:17:19 PM PDT 24
Peak memory 202300 kb
Host smart-d92eea66-f2d0-424f-88c8-d0b98e123b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281380858 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.sysrst_ctrl_combo_detect_w
ith_pre_cond.3281380858
Directory /workspace/53.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.299520106
Short name T10
Test name
Test status
Simulation time 78104899382 ps
CPU time 101.87 seconds
Started Mar 24 01:16:30 PM PDT 24
Finished Mar 24 01:18:12 PM PDT 24
Peak memory 202196 kb
Host smart-3d799bda-cda4-4550-9ba1-802e905c5aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299520106 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.sysrst_ctrl_combo_detect_wi
th_pre_cond.299520106
Directory /workspace/54.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.821754062
Short name T283
Test name
Test status
Simulation time 26089059804 ps
CPU time 33.95 seconds
Started Mar 24 01:16:32 PM PDT 24
Finished Mar 24 01:17:06 PM PDT 24
Peak memory 202296 kb
Host smart-fedfaa25-b059-494e-9d87-c1d8c6792fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821754062 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.sysrst_ctrl_combo_detect_wi
th_pre_cond.821754062
Directory /workspace/55.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.2271457980
Short name T238
Test name
Test status
Simulation time 147625380516 ps
CPU time 408.13 seconds
Started Mar 24 01:16:33 PM PDT 24
Finished Mar 24 01:23:22 PM PDT 24
Peak memory 202296 kb
Host smart-9f512b33-64b2-4d70-827d-5349dd87b865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271457980 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.sysrst_ctrl_combo_detect_w
ith_pre_cond.2271457980
Directory /workspace/56.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.1174044173
Short name T229
Test name
Test status
Simulation time 100904117177 ps
CPU time 26.77 seconds
Started Mar 24 01:16:33 PM PDT 24
Finished Mar 24 01:17:00 PM PDT 24
Peak memory 202248 kb
Host smart-589ccf52-50a6-4eed-94de-9deceff6e47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174044173 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.sysrst_ctrl_combo_detect_w
ith_pre_cond.1174044173
Directory /workspace/57.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.68412564
Short name T747
Test name
Test status
Simulation time 37354556128 ps
CPU time 25.88 seconds
Started Mar 24 01:16:30 PM PDT 24
Finished Mar 24 01:16:56 PM PDT 24
Peak memory 202280 kb
Host smart-6a1879af-d221-4be1-9b1d-1cca25d08056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68412564 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.sysrst_ctrl_combo_detect_wit
h_pre_cond.68412564
Directory /workspace/58.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_alert_test.1148900492
Short name T624
Test name
Test status
Simulation time 2015814743 ps
CPU time 5.68 seconds
Started Mar 24 01:15:04 PM PDT 24
Finished Mar 24 01:15:09 PM PDT 24
Peak memory 202032 kb
Host smart-fb83be0f-ae21-474f-865d-fdc4be950d3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148900492 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_alert_tes
t.1148900492
Directory /workspace/6.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.2294404851
Short name T645
Test name
Test status
Simulation time 2949311477 ps
CPU time 4.39 seconds
Started Mar 24 01:14:59 PM PDT 24
Finished Mar 24 01:15:04 PM PDT 24
Peak memory 202088 kb
Host smart-81b461c7-99b0-4425-97df-65c5becf39a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294404851 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_auto_blk_key_output.2294404851
Directory /workspace/6.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect.2517536525
Short name T258
Test name
Test status
Simulation time 86093060077 ps
CPU time 217.65 seconds
Started Mar 24 01:14:57 PM PDT 24
Finished Mar 24 01:18:35 PM PDT 24
Peak memory 202276 kb
Host smart-71182e2d-9f8f-4b5f-abd5-b83713f55abe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517536525 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ct
rl_combo_detect.2517536525
Directory /workspace/6.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.4158150160
Short name T367
Test name
Test status
Simulation time 85507374174 ps
CPU time 58 seconds
Started Mar 24 01:15:04 PM PDT 24
Finished Mar 24 01:16:02 PM PDT 24
Peak memory 202356 kb
Host smart-cf55f296-334a-41fd-b8b6-5140a010a9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158150160 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_combo_detect_wi
th_pre_cond.4158150160
Directory /workspace/6.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.1896019944
Short name T105
Test name
Test status
Simulation time 6046157058 ps
CPU time 5.31 seconds
Started Mar 24 01:14:58 PM PDT 24
Finished Mar 24 01:15:03 PM PDT 24
Peak memory 201988 kb
Host smart-44160e2a-6b61-426d-8fb6-d590cf30c642
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896019944 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_ec_pwr_on_rst.1896019944
Directory /workspace/6.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_edge_detect.829188724
Short name T740
Test name
Test status
Simulation time 3540651740 ps
CPU time 3 seconds
Started Mar 24 01:15:00 PM PDT 24
Finished Mar 24 01:15:04 PM PDT 24
Peak memory 202036 kb
Host smart-25c33cdf-0de1-4547-a055-1721af005a22
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829188724 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl
_edge_detect.829188724
Directory /workspace/6.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.2410922416
Short name T473
Test name
Test status
Simulation time 2610770178 ps
CPU time 7.74 seconds
Started Mar 24 01:14:58 PM PDT 24
Finished Mar 24 01:15:05 PM PDT 24
Peak memory 202040 kb
Host smart-96163168-f2dd-465a-a685-86bab6c9b1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410922416 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_flash_wr_prot_out.2410922416
Directory /workspace/6.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.1020715740
Short name T439
Test name
Test status
Simulation time 2531050987 ps
CPU time 1.11 seconds
Started Mar 24 01:15:00 PM PDT 24
Finished Mar 24 01:15:02 PM PDT 24
Peak memory 202048 kb
Host smart-178e67a0-2a6b-4827-bafb-2294ed351323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020715740 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_in_out_inverted.1020715740
Directory /workspace/6.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_access_test.3748045151
Short name T419
Test name
Test status
Simulation time 2181448506 ps
CPU time 2.09 seconds
Started Mar 24 01:15:01 PM PDT 24
Finished Mar 24 01:15:03 PM PDT 24
Peak memory 201948 kb
Host smart-f0d336c0-ca81-435e-a6e5-202cbcad2f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748045151 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_access_test.3748045151
Directory /workspace/6.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_override_test.4129245461
Short name T464
Test name
Test status
Simulation time 2602708223 ps
CPU time 1.33 seconds
Started Mar 24 01:15:00 PM PDT 24
Finished Mar 24 01:15:01 PM PDT 24
Peak memory 201996 kb
Host smart-9dec2a1b-0a61-4b22-90d5-4b326f10e51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129245461 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_override_test.4129245461
Directory /workspace/6.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_smoke.541786953
Short name T397
Test name
Test status
Simulation time 2193168830 ps
CPU time 1 seconds
Started Mar 24 01:15:01 PM PDT 24
Finished Mar 24 01:15:02 PM PDT 24
Peak memory 201944 kb
Host smart-0a026cc3-850d-4c2a-83cf-a476cc4892eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541786953 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_smoke.541786953
Directory /workspace/6.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all.1267513326
Short name T169
Test name
Test status
Simulation time 13077223509 ps
CPU time 9.4 seconds
Started Mar 24 01:15:06 PM PDT 24
Finished Mar 24 01:15:15 PM PDT 24
Peak memory 201960 kb
Host smart-848bd2b0-b080-4a18-ab45-f12a0fd8e63a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267513326 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_st
ress_all.1267513326
Directory /workspace/6.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.223807084
Short name T360
Test name
Test status
Simulation time 67493292875 ps
CPU time 28.46 seconds
Started Mar 24 01:16:31 PM PDT 24
Finished Mar 24 01:17:00 PM PDT 24
Peak memory 202112 kb
Host smart-a45eb9b0-7deb-4903-b26f-219a8f458437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223807084 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.sysrst_ctrl_combo_detect_wi
th_pre_cond.223807084
Directory /workspace/60.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.1960656663
Short name T79
Test name
Test status
Simulation time 99223329643 ps
CPU time 252.63 seconds
Started Mar 24 01:16:38 PM PDT 24
Finished Mar 24 01:20:51 PM PDT 24
Peak memory 202272 kb
Host smart-7cafb2ce-3fab-482d-9732-909effa28dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960656663 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.sysrst_ctrl_combo_detect_w
ith_pre_cond.1960656663
Directory /workspace/63.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.2339486591
Short name T376
Test name
Test status
Simulation time 87170118663 ps
CPU time 108.34 seconds
Started Mar 24 01:16:30 PM PDT 24
Finished Mar 24 01:18:19 PM PDT 24
Peak memory 202128 kb
Host smart-198908e3-0a68-4b4b-b21d-d91dcd804376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339486591 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.sysrst_ctrl_combo_detect_w
ith_pre_cond.2339486591
Directory /workspace/64.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.1209135080
Short name T722
Test name
Test status
Simulation time 29081104140 ps
CPU time 79.68 seconds
Started Mar 24 01:16:33 PM PDT 24
Finished Mar 24 01:17:53 PM PDT 24
Peak memory 202164 kb
Host smart-2a89194d-9685-45fd-8993-0de61d03675b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209135080 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.sysrst_ctrl_combo_detect_w
ith_pre_cond.1209135080
Directory /workspace/65.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.1466155449
Short name T344
Test name
Test status
Simulation time 74566563605 ps
CPU time 13.31 seconds
Started Mar 24 01:16:29 PM PDT 24
Finished Mar 24 01:16:43 PM PDT 24
Peak memory 202168 kb
Host smart-1c89bfa8-6e3c-4213-85bf-2960c8552c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466155449 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.sysrst_ctrl_combo_detect_w
ith_pre_cond.1466155449
Directory /workspace/67.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.1407250586
Short name T86
Test name
Test status
Simulation time 26328126346 ps
CPU time 66.89 seconds
Started Mar 24 01:16:30 PM PDT 24
Finished Mar 24 01:17:37 PM PDT 24
Peak memory 202280 kb
Host smart-d94d5aef-83b5-469e-a85e-bbe45cf71c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407250586 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.sysrst_ctrl_combo_detect_w
ith_pre_cond.1407250586
Directory /workspace/68.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_alert_test.1598055457
Short name T191
Test name
Test status
Simulation time 2024470494 ps
CPU time 1.99 seconds
Started Mar 24 01:15:05 PM PDT 24
Finished Mar 24 01:15:07 PM PDT 24
Peak memory 202128 kb
Host smart-3e41741e-9eb7-4ed4-91a9-542158818d31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598055457 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_alert_tes
t.1598055457
Directory /workspace/7.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.2814982200
Short name T726
Test name
Test status
Simulation time 3743768106 ps
CPU time 2.45 seconds
Started Mar 24 01:15:07 PM PDT 24
Finished Mar 24 01:15:09 PM PDT 24
Peak memory 202028 kb
Host smart-78fe4603-09f8-4973-81ff-cb0607bb452a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814982200 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_auto_blk_key_output.2814982200
Directory /workspace/7.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect.578019207
Short name T710
Test name
Test status
Simulation time 65081688631 ps
CPU time 14.47 seconds
Started Mar 24 01:15:04 PM PDT 24
Finished Mar 24 01:15:19 PM PDT 24
Peak memory 202248 kb
Host smart-08204aae-20b4-423f-b1a6-ef9a30ddb80e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578019207 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctr
l_combo_detect.578019207
Directory /workspace/7.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.281823189
Short name T54
Test name
Test status
Simulation time 3759542820 ps
CPU time 1.1 seconds
Started Mar 24 01:15:03 PM PDT 24
Finished Mar 24 01:15:05 PM PDT 24
Peak memory 202048 kb
Host smart-bc19e1b7-6ff3-4a4a-a6c5-446ed6ecd63b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281823189 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ct
rl_ec_pwr_on_rst.281823189
Directory /workspace/7.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_edge_detect.1300116980
Short name T39
Test name
Test status
Simulation time 6167693322 ps
CPU time 1.5 seconds
Started Mar 24 01:15:04 PM PDT 24
Finished Mar 24 01:15:06 PM PDT 24
Peak memory 202080 kb
Host smart-4d5ca46f-2fef-4ea7-b53a-05882c5c60ed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300116980 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctr
l_edge_detect.1300116980
Directory /workspace/7.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.2150785827
Short name T665
Test name
Test status
Simulation time 2612715272 ps
CPU time 7.55 seconds
Started Mar 24 01:15:07 PM PDT 24
Finished Mar 24 01:15:15 PM PDT 24
Peak memory 202064 kb
Host smart-caec2021-53b3-4184-a757-911ec7da40ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150785827 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_flash_wr_prot_out.2150785827
Directory /workspace/7.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.2896937246
Short name T728
Test name
Test status
Simulation time 2488508236 ps
CPU time 1.61 seconds
Started Mar 24 01:15:06 PM PDT 24
Finished Mar 24 01:15:08 PM PDT 24
Peak memory 202044 kb
Host smart-c5affd47-2d4a-49e4-ae95-fb445f744baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896937246 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_in_out_inverted.2896937246
Directory /workspace/7.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_access_test.3118196423
Short name T536
Test name
Test status
Simulation time 2049515923 ps
CPU time 5.95 seconds
Started Mar 24 01:15:04 PM PDT 24
Finished Mar 24 01:15:10 PM PDT 24
Peak memory 201912 kb
Host smart-1fc24402-b530-44c9-b391-e8a42b7c8d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118196423 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_access_test.3118196423
Directory /workspace/7.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_override_test.1165168124
Short name T702
Test name
Test status
Simulation time 2510258926 ps
CPU time 7.59 seconds
Started Mar 24 01:15:03 PM PDT 24
Finished Mar 24 01:15:11 PM PDT 24
Peak memory 202000 kb
Host smart-d2a7c126-488e-4525-b4d4-ff6ab5863f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165168124 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_override_test.1165168124
Directory /workspace/7.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_smoke.949961222
Short name T100
Test name
Test status
Simulation time 2108664891 ps
CPU time 6.24 seconds
Started Mar 24 01:15:04 PM PDT 24
Finished Mar 24 01:15:11 PM PDT 24
Peak memory 201916 kb
Host smart-de4c7b5b-7103-43de-b471-340e3468bc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949961222 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_smoke.949961222
Directory /workspace/7.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all.2612955920
Short name T139
Test name
Test status
Simulation time 14219281123 ps
CPU time 8.55 seconds
Started Mar 24 01:15:03 PM PDT 24
Finished Mar 24 01:15:12 PM PDT 24
Peak memory 202016 kb
Host smart-4035433c-cdfb-41f6-9475-a3c51c0b52ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612955920 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_st
ress_all.2612955920
Directory /workspace/7.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.964678310
Short name T764
Test name
Test status
Simulation time 91557919580 ps
CPU time 57.87 seconds
Started Mar 24 01:15:08 PM PDT 24
Finished Mar 24 01:16:06 PM PDT 24
Peak memory 210528 kb
Host smart-90022d22-a16a-4215-8a56-75e4d31d5153
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964678310 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_stress_all_with_rand_reset.964678310
Directory /workspace/7.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.2751897984
Short name T120
Test name
Test status
Simulation time 10131196835 ps
CPU time 4.07 seconds
Started Mar 24 01:15:07 PM PDT 24
Finished Mar 24 01:15:11 PM PDT 24
Peak memory 202100 kb
Host smart-21551aba-3780-4a8b-89bd-d8a0e7956cb3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751897984 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_ultra_low_pwr.2751897984
Directory /workspace/7.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.3578227687
Short name T240
Test name
Test status
Simulation time 65044774559 ps
CPU time 92.07 seconds
Started Mar 24 01:16:34 PM PDT 24
Finished Mar 24 01:18:06 PM PDT 24
Peak memory 202308 kb
Host smart-28d3f551-e46c-4677-bfbe-c00eb3fc095e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578227687 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.sysrst_ctrl_combo_detect_w
ith_pre_cond.3578227687
Directory /workspace/70.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.712995556
Short name T565
Test name
Test status
Simulation time 44702662054 ps
CPU time 31.8 seconds
Started Mar 24 01:16:35 PM PDT 24
Finished Mar 24 01:17:07 PM PDT 24
Peak memory 202312 kb
Host smart-120a7bdd-5629-4d66-872f-3427234c067e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712995556 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.sysrst_ctrl_combo_detect_wi
th_pre_cond.712995556
Directory /workspace/72.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.3972445794
Short name T250
Test name
Test status
Simulation time 25853231225 ps
CPU time 19.19 seconds
Started Mar 24 01:16:34 PM PDT 24
Finished Mar 24 01:16:53 PM PDT 24
Peak memory 202168 kb
Host smart-bdb8cdd1-2e00-433f-9cde-7e33665880e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972445794 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.sysrst_ctrl_combo_detect_w
ith_pre_cond.3972445794
Directory /workspace/74.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.4062545150
Short name T85
Test name
Test status
Simulation time 43867899239 ps
CPU time 14.41 seconds
Started Mar 24 01:16:34 PM PDT 24
Finished Mar 24 01:16:48 PM PDT 24
Peak memory 202192 kb
Host smart-73eb574b-dbb1-4706-9a56-d5e3b12ea06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062545150 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.sysrst_ctrl_combo_detect_w
ith_pre_cond.4062545150
Directory /workspace/75.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.2157508421
Short name T45
Test name
Test status
Simulation time 44079096289 ps
CPU time 114.07 seconds
Started Mar 24 01:16:36 PM PDT 24
Finished Mar 24 01:18:30 PM PDT 24
Peak memory 202336 kb
Host smart-397d9093-6aef-47e7-8e45-7daa0dfa6bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157508421 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.sysrst_ctrl_combo_detect_w
ith_pre_cond.2157508421
Directory /workspace/76.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_alert_test.2554320821
Short name T204
Test name
Test status
Simulation time 2014001539 ps
CPU time 6.04 seconds
Started Mar 24 01:15:11 PM PDT 24
Finished Mar 24 01:15:17 PM PDT 24
Peak memory 202080 kb
Host smart-0ab45417-c289-4d7d-906f-9dc26102b646
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554320821 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_alert_tes
t.2554320821
Directory /workspace/8.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.2449799427
Short name T111
Test name
Test status
Simulation time 3306749535 ps
CPU time 4.47 seconds
Started Mar 24 01:15:08 PM PDT 24
Finished Mar 24 01:15:13 PM PDT 24
Peak memory 202144 kb
Host smart-2e6b2289-2b66-4ba5-b04c-e77081ba2fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449799427 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_auto_blk_key_output.2449799427
Directory /workspace/8.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect.258099343
Short name T88
Test name
Test status
Simulation time 61734942314 ps
CPU time 86.33 seconds
Started Mar 24 01:15:08 PM PDT 24
Finished Mar 24 01:16:40 PM PDT 24
Peak memory 202212 kb
Host smart-d14ab686-98c6-4d5b-b40a-b840a4a608bf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258099343 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctr
l_combo_detect.258099343
Directory /workspace/8.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.4236569603
Short name T715
Test name
Test status
Simulation time 84689374202 ps
CPU time 99.45 seconds
Started Mar 24 01:15:18 PM PDT 24
Finished Mar 24 01:16:58 PM PDT 24
Peak memory 202320 kb
Host smart-b3091beb-2485-438f-9ef4-e063f1cf8f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236569603 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect_wi
th_pre_cond.4236569603
Directory /workspace/8.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.3958865882
Short name T211
Test name
Test status
Simulation time 3525489772 ps
CPU time 2.7 seconds
Started Mar 24 01:15:09 PM PDT 24
Finished Mar 24 01:15:12 PM PDT 24
Peak memory 201944 kb
Host smart-377e0813-1e8f-428f-969f-bee6f2fe80ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958865882 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_ec_pwr_on_rst.3958865882
Directory /workspace/8.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_edge_detect.2031464862
Short name T144
Test name
Test status
Simulation time 3703832281 ps
CPU time 10.15 seconds
Started Mar 24 01:15:11 PM PDT 24
Finished Mar 24 01:15:21 PM PDT 24
Peak memory 202032 kb
Host smart-91149770-477e-412e-a2f8-05aed1fd2ab2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031464862 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctr
l_edge_detect.2031464862
Directory /workspace/8.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.138531798
Short name T509
Test name
Test status
Simulation time 2620414178 ps
CPU time 2.34 seconds
Started Mar 24 01:15:07 PM PDT 24
Finished Mar 24 01:15:09 PM PDT 24
Peak memory 201948 kb
Host smart-a265d24b-a7fd-4614-8206-59f65acd9b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138531798 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_flash_wr_prot_out.138531798
Directory /workspace/8.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.1249356980
Short name T532
Test name
Test status
Simulation time 2461915034 ps
CPU time 2.08 seconds
Started Mar 24 01:15:09 PM PDT 24
Finished Mar 24 01:15:11 PM PDT 24
Peak memory 201960 kb
Host smart-718e4f97-a6b7-46bd-854b-2cd77e30ecae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249356980 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_in_out_inverted.1249356980
Directory /workspace/8.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_access_test.3600713996
Short name T305
Test name
Test status
Simulation time 2159333443 ps
CPU time 6.08 seconds
Started Mar 24 01:15:09 PM PDT 24
Finished Mar 24 01:15:15 PM PDT 24
Peak memory 202032 kb
Host smart-9a82b580-a269-4bd5-ab99-60b444098a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600713996 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_access_test.3600713996
Directory /workspace/8.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_override_test.1381440526
Short name T744
Test name
Test status
Simulation time 2516888291 ps
CPU time 4.2 seconds
Started Mar 24 01:15:10 PM PDT 24
Finished Mar 24 01:15:15 PM PDT 24
Peak memory 202068 kb
Host smart-eac4bb15-775a-4781-9d89-6866aabee450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381440526 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_override_test.1381440526
Directory /workspace/8.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_smoke.4266553747
Short name T501
Test name
Test status
Simulation time 2113186684 ps
CPU time 5.71 seconds
Started Mar 24 01:15:05 PM PDT 24
Finished Mar 24 01:15:10 PM PDT 24
Peak memory 201888 kb
Host smart-23639d71-5c49-4650-bb2e-6cefc25a4928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266553747 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_smoke.4266553747
Directory /workspace/8.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all.647702469
Short name T46
Test name
Test status
Simulation time 13374648548 ps
CPU time 9.05 seconds
Started Mar 24 01:15:30 PM PDT 24
Finished Mar 24 01:15:39 PM PDT 24
Peak memory 202052 kb
Host smart-06f212d7-5204-4cdc-b571-989b55b29510
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647702469 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_str
ess_all.647702469
Directory /workspace/8.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.2918357063
Short name T300
Test name
Test status
Simulation time 4400970402 ps
CPU time 7.03 seconds
Started Mar 24 01:15:24 PM PDT 24
Finished Mar 24 01:15:31 PM PDT 24
Peak memory 202068 kb
Host smart-f4d79dd3-949f-4313-9b0a-197416979d07
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918357063 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_ultra_low_pwr.2918357063
Directory /workspace/8.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.2134677536
Short name T469
Test name
Test status
Simulation time 47007081034 ps
CPU time 123.53 seconds
Started Mar 24 01:16:43 PM PDT 24
Finished Mar 24 01:18:47 PM PDT 24
Peak memory 202256 kb
Host smart-6d909312-5b66-4520-be14-df28876ee6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134677536 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.sysrst_ctrl_combo_detect_w
ith_pre_cond.2134677536
Directory /workspace/80.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.950753338
Short name T383
Test name
Test status
Simulation time 57518481656 ps
CPU time 141.04 seconds
Started Mar 24 01:16:41 PM PDT 24
Finished Mar 24 01:19:02 PM PDT 24
Peak memory 202324 kb
Host smart-64149b35-738d-450b-bfd7-5b361c62de6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950753338 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.sysrst_ctrl_combo_detect_wi
th_pre_cond.950753338
Directory /workspace/81.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.1484263230
Short name T677
Test name
Test status
Simulation time 50656766613 ps
CPU time 63.15 seconds
Started Mar 24 01:16:37 PM PDT 24
Finished Mar 24 01:17:40 PM PDT 24
Peak memory 202316 kb
Host smart-1947768a-234f-4a6f-a458-5f75f5b9cd85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484263230 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.sysrst_ctrl_combo_detect_w
ith_pre_cond.1484263230
Directory /workspace/82.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.1633410825
Short name T334
Test name
Test status
Simulation time 128166861182 ps
CPU time 159.33 seconds
Started Mar 24 01:16:35 PM PDT 24
Finished Mar 24 01:19:15 PM PDT 24
Peak memory 202136 kb
Host smart-cb0f38f9-feb4-4704-9e83-45481af9e0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633410825 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.sysrst_ctrl_combo_detect_w
ith_pre_cond.1633410825
Directory /workspace/84.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.1941443825
Short name T405
Test name
Test status
Simulation time 29587421299 ps
CPU time 41 seconds
Started Mar 24 01:16:42 PM PDT 24
Finished Mar 24 01:17:23 PM PDT 24
Peak memory 202276 kb
Host smart-06cd3f81-591d-4872-9d15-a03801916bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941443825 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.sysrst_ctrl_combo_detect_w
ith_pre_cond.1941443825
Directory /workspace/85.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.3763727995
Short name T588
Test name
Test status
Simulation time 84718226291 ps
CPU time 205.03 seconds
Started Mar 24 01:16:39 PM PDT 24
Finished Mar 24 01:20:04 PM PDT 24
Peak memory 202344 kb
Host smart-a67e3f32-d34a-476f-a329-72b3ac48943a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763727995 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.sysrst_ctrl_combo_detect_w
ith_pre_cond.3763727995
Directory /workspace/87.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.2881166173
Short name T642
Test name
Test status
Simulation time 39950496985 ps
CPU time 106.98 seconds
Started Mar 24 01:16:42 PM PDT 24
Finished Mar 24 01:18:29 PM PDT 24
Peak memory 202336 kb
Host smart-30f668c1-af3a-4f1e-9590-e431aa56fd1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881166173 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.sysrst_ctrl_combo_detect_w
ith_pre_cond.2881166173
Directory /workspace/88.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.3578399719
Short name T209
Test name
Test status
Simulation time 16337748794 ps
CPU time 24.56 seconds
Started Mar 24 01:16:34 PM PDT 24
Finished Mar 24 01:16:59 PM PDT 24
Peak memory 202304 kb
Host smart-6b717f4c-1738-441e-874f-96ed95cb26f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578399719 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.sysrst_ctrl_combo_detect_w
ith_pre_cond.3578399719
Directory /workspace/89.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_alert_test.684880702
Short name T543
Test name
Test status
Simulation time 2017303491 ps
CPU time 3.14 seconds
Started Mar 24 01:15:30 PM PDT 24
Finished Mar 24 01:15:33 PM PDT 24
Peak memory 202080 kb
Host smart-a967daf4-17fe-43ba-8bd5-ef4b69d6b028
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684880702 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_alert_test
.684880702
Directory /workspace/9.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.3494436349
Short name T277
Test name
Test status
Simulation time 3257193241 ps
CPU time 8.51 seconds
Started Mar 24 01:15:09 PM PDT 24
Finished Mar 24 01:15:18 PM PDT 24
Peak memory 202348 kb
Host smart-c9c61fe0-a7fe-4306-8886-28499fecc94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494436349 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_auto_blk_key_output.3494436349
Directory /workspace/9.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect.3398473651
Short name T243
Test name
Test status
Simulation time 183334516018 ps
CPU time 490.4 seconds
Started Mar 24 01:15:25 PM PDT 24
Finished Mar 24 01:23:36 PM PDT 24
Peak memory 202288 kb
Host smart-385be22e-d05a-41f4-bafb-5436047d83d7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398473651 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ct
rl_combo_detect.3398473651
Directory /workspace/9.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.466412471
Short name T241
Test name
Test status
Simulation time 24080795577 ps
CPU time 62.59 seconds
Started Mar 24 01:15:15 PM PDT 24
Finished Mar 24 01:16:18 PM PDT 24
Peak memory 202216 kb
Host smart-52f270b3-8dfd-4be7-a384-b85d967fdcbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466412471 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect_wit
h_pre_cond.466412471
Directory /workspace/9.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.3139830113
Short name T684
Test name
Test status
Simulation time 3508214714 ps
CPU time 9.86 seconds
Started Mar 24 01:15:09 PM PDT 24
Finished Mar 24 01:15:19 PM PDT 24
Peak memory 202264 kb
Host smart-c957fef5-a901-41b5-8e0b-2b4e9cc03247
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139830113 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_ec_pwr_on_rst.3139830113
Directory /workspace/9.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_edge_detect.3716365947
Short name T713
Test name
Test status
Simulation time 5251802412 ps
CPU time 2.77 seconds
Started Mar 24 01:15:11 PM PDT 24
Finished Mar 24 01:15:13 PM PDT 24
Peak memory 202048 kb
Host smart-8a98a04e-8765-487d-bb2d-f7b845eb7e13
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716365947 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctr
l_edge_detect.3716365947
Directory /workspace/9.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.2872217651
Short name T698
Test name
Test status
Simulation time 2628730001 ps
CPU time 2.6 seconds
Started Mar 24 01:15:11 PM PDT 24
Finished Mar 24 01:15:14 PM PDT 24
Peak memory 202304 kb
Host smart-d9e01e21-fc74-4ba1-8fd6-a6efabd1f81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872217651 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_flash_wr_prot_out.2872217651
Directory /workspace/9.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.2674967775
Short name T774
Test name
Test status
Simulation time 2480840079 ps
CPU time 1.97 seconds
Started Mar 24 01:15:12 PM PDT 24
Finished Mar 24 01:15:14 PM PDT 24
Peak memory 202072 kb
Host smart-f26cbc3e-4b50-495b-9732-35e718fbb7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674967775 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_in_out_inverted.2674967775
Directory /workspace/9.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_access_test.2743906650
Short name T554
Test name
Test status
Simulation time 2053513354 ps
CPU time 1.59 seconds
Started Mar 24 01:15:16 PM PDT 24
Finished Mar 24 01:15:18 PM PDT 24
Peak memory 202180 kb
Host smart-ef27a902-c5b3-4551-864c-d075db42c920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743906650 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_access_test.2743906650
Directory /workspace/9.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_override_test.3432705456
Short name T201
Test name
Test status
Simulation time 2518225081 ps
CPU time 3.92 seconds
Started Mar 24 01:15:23 PM PDT 24
Finished Mar 24 01:15:28 PM PDT 24
Peak memory 202088 kb
Host smart-5bb6f69d-c133-4517-a017-72504fecff0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432705456 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_override_test.3432705456
Directory /workspace/9.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_smoke.541456021
Short name T490
Test name
Test status
Simulation time 2110317424 ps
CPU time 6.47 seconds
Started Mar 24 01:15:15 PM PDT 24
Finished Mar 24 01:15:21 PM PDT 24
Peak memory 201840 kb
Host smart-2d3f9a58-04bf-4605-967e-da6e38479ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541456021 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_smoke.541456021
Directory /workspace/9.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all.2269297687
Short name T4
Test name
Test status
Simulation time 17650762597 ps
CPU time 33.78 seconds
Started Mar 24 01:15:08 PM PDT 24
Finished Mar 24 01:15:42 PM PDT 24
Peak memory 202076 kb
Host smart-ad06c7dd-86aa-4018-b98e-d0ee2ac92a3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269297687 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_st
ress_all.2269297687
Directory /workspace/9.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.1040823246
Short name T116
Test name
Test status
Simulation time 51331808948 ps
CPU time 130.78 seconds
Started Mar 24 01:15:17 PM PDT 24
Finished Mar 24 01:17:28 PM PDT 24
Peak memory 210656 kb
Host smart-ef1cd361-1a9d-4e34-865b-b0247ecdf83b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040823246 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_stress_all_with_rand_reset.1040823246
Directory /workspace/9.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.2973930532
Short name T222
Test name
Test status
Simulation time 3200199967 ps
CPU time 6.66 seconds
Started Mar 24 01:15:10 PM PDT 24
Finished Mar 24 01:15:16 PM PDT 24
Peak memory 202068 kb
Host smart-3f48d1e7-e733-4a71-a4d9-97e135de81f9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973930532 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_ultra_low_pwr.2973930532
Directory /workspace/9.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.3697349861
Short name T641
Test name
Test status
Simulation time 42790313520 ps
CPU time 27.29 seconds
Started Mar 24 01:16:39 PM PDT 24
Finished Mar 24 01:17:06 PM PDT 24
Peak memory 202300 kb
Host smart-62c710e6-6866-4063-9ce1-ff9510969b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697349861 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.sysrst_ctrl_combo_detect_w
ith_pre_cond.3697349861
Directory /workspace/90.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.1542096655
Short name T737
Test name
Test status
Simulation time 76785285325 ps
CPU time 174.61 seconds
Started Mar 24 01:16:39 PM PDT 24
Finished Mar 24 01:19:34 PM PDT 24
Peak memory 202308 kb
Host smart-dfe1090d-fd71-4a79-92c6-5a1875acf2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542096655 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.sysrst_ctrl_combo_detect_w
ith_pre_cond.1542096655
Directory /workspace/93.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.30514588
Short name T368
Test name
Test status
Simulation time 88183937071 ps
CPU time 196.33 seconds
Started Mar 24 01:16:34 PM PDT 24
Finished Mar 24 01:19:51 PM PDT 24
Peak memory 202232 kb
Host smart-03b83209-4cd0-456a-8453-53567216042a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30514588 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.sysrst_ctrl_combo_detect_wit
h_pre_cond.30514588
Directory /workspace/94.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.3015381449
Short name T662
Test name
Test status
Simulation time 112077507747 ps
CPU time 79.08 seconds
Started Mar 24 01:16:35 PM PDT 24
Finished Mar 24 01:17:54 PM PDT 24
Peak memory 202152 kb
Host smart-217ef1ee-287b-449a-9e15-f266cc9928f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015381449 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.sysrst_ctrl_combo_detect_w
ith_pre_cond.3015381449
Directory /workspace/95.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.1805248499
Short name T365
Test name
Test status
Simulation time 102639584096 ps
CPU time 167.7 seconds
Started Mar 24 01:16:35 PM PDT 24
Finished Mar 24 01:19:23 PM PDT 24
Peak memory 202260 kb
Host smart-d32fda18-2543-4f37-be0b-aa811f90c694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805248499 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.sysrst_ctrl_combo_detect_w
ith_pre_cond.1805248499
Directory /workspace/96.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.1482419388
Short name T242
Test name
Test status
Simulation time 59725417266 ps
CPU time 25.25 seconds
Started Mar 24 01:16:34 PM PDT 24
Finished Mar 24 01:17:00 PM PDT 24
Peak memory 202228 kb
Host smart-3da9895d-6a37-48b2-8d34-c42001e19efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482419388 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.sysrst_ctrl_combo_detect_w
ith_pre_cond.1482419388
Directory /workspace/97.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.1283172200
Short name T87
Test name
Test status
Simulation time 25879515690 ps
CPU time 11.19 seconds
Started Mar 24 01:16:43 PM PDT 24
Finished Mar 24 01:16:54 PM PDT 24
Peak memory 202252 kb
Host smart-ff8c806c-5831-4ded-9662-3be8c57d6025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283172200 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.sysrst_ctrl_combo_detect_w
ith_pre_cond.1283172200
Directory /workspace/98.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.3768718690
Short name T335
Test name
Test status
Simulation time 53649147754 ps
CPU time 138.27 seconds
Started Mar 24 01:16:43 PM PDT 24
Finished Mar 24 01:19:02 PM PDT 24
Peak memory 202316 kb
Host smart-2a6dea16-670e-4485-8fbc-1a4e2ab1b321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768718690 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.sysrst_ctrl_combo_detect_w
ith_pre_cond.3768718690
Directory /workspace/99.sysrst_ctrl_combo_detect_with_pre_cond/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%