Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.46	91.46	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	91.46	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.46	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	7	55	88.71

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	7	24	77.42	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1916

1

T1

7

T2

5

T7

13

auto[1]

770

1

T1

5

T5

2

T2

5

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1948

1

T5

2

T4

10

T7

18

auto[1]

738

1

T1

12

T2

10

T4

7

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2013

1

T1

7

T2

1

T4

15

auto[1]

673

1

T1

5

T5

2

T2

9

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2083

1

T1

11

T5

2

T2

8

auto[1]

603

1

T1

1

T2

2

T4

10

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2471

1

T1

12

T5

2

T2

10

auto[1]

215

1

T11

10

T39

9

T40

4

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2522

1

T1

12

T5

2

T2

10

auto[1]

164

1

T7

5

T11

1

T42

2

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2437

1

T1

12

T5

2

T2

10

auto[1]

249

1

T7

7

T11

5

T42

2

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2494

1

T1

12

T5

2

T2

10

auto[1]

192

1

T7

2

T11

10

T40

7

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2432

1

T1

12

T5

2

T2

10

auto[1]

254

1

T7

4

T11

10

T39

16

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2009

1

T1

4

T2

9

T4

12

auto[1]

677

1

T1

8

T5

2

T2

1

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	7	24	77.42	7
Automatically Generated Cross Bins	31	7	24	77.42	7
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	*	[auto[1]]	[auto[1]]	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1035

1

T1

12

T5

2

T2

5

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

55

1

T39

7

T40

4

T117

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

74

1

T39

10

T261

1

T127

16

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

35

1

T11

4

T118

3

T260

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

48

1

T118

3

T267

1

T355

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

22

1

T11

5

T233

1

T349

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

15

1

T40

4

T349

3

T350

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

77

1

T263

1

T349

3

T355

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

26

1

T283

11

T356

6

T242

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

22

1

T127

3

T342

2

T356

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

11

1

T260

1

T343

1

T357

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

16

1

T347

2

T350

10

T358

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

3

1

T283

3

-

-

-

-

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

18

1

T7

2

T11

5

T74

7

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

41

1

T40

4

T118

4

T260

7

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

21

1

T39

2

T99

2

T356

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

22

1

T39

6

T355

1

T343

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

1

1

T11

1

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

8

1

T359

3

T354

5

-

-

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

5

1

T40

3

T89

2

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

18

1

T7

1

T342

1

T360

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

19

1

T283

6

T361

1

T362

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

4

1

T7

1

T363

2

T359

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

11

1

T364

1

T352

8

T354

2

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

99

1

T7

1

T284

11

T207

10

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

130

1

T10

10

T11

5

T95

11

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

90

1

T129

7

T207

7

T208

6

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

103

1

T10

10

T11

4

T39

10

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

70

1

T4

5

T7

1

T39

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

26

1

T365

6

T360

2

T366

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

28

1

T4

3

T12

3

T95

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

143

1

T12

10

T39

7

T40

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

64

1

T10

5

T40

4

T284

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

67

1

T52

8

T32

6

T118

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

17

1

T5

2

T118

3

T339

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

38

1

T11

1

T39

2

T40

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

21

1

T261

1

T285

3

T127

8

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

28

1

T129

2

T339

2

T344

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

18

1

T4

2

T10

2

T52

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

103

1

T74

7

T260

1

T100

9

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

107

1

T4

7

T7

2

T11

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

73

1

T1

7

T40

4

T130

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

35

1

T12

2

T285

1

T367

7

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

72

1

T95

4

T282

3

T117

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

20

1

T10

4

T55

1

T127

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

37

1

T52

4

T32

3

T368

6

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

12

1

T2

1

T272

2

T273

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

49

1

T95

3

T349

3

T94

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

38

1

T1

4

T2

3

T262

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

31

1

T285

1

T269

2

T190

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

11

1

T129

3

T341

2

T369

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

23

1

T12

2

T243

1

T367

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

27

1

T2

1

T101

4

T103

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

20

1

T236

2

T363

3

T190

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

7

1

T1

1

T10

1

T34

2

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded