Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	160886	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

122367

1

T1

271

T5

241

T6

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	144557	1			T1	395		T5	385		T6	2
values[0x0]	68656	1			T1	67		T5	19		T2	30
values[0x1]	70040	1			T1	74		T5	26		T2	39

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	129838	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

153415

1

T1

316

T5

277

T6

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	944	1			T1	3		T47	1		T43	15
valid_sources[0x01]	1177	1			T1	1		T5	3		T4	3
valid_sources[0x02]	1004	1			T1	3		T4	8		T11	2
valid_sources[0x03]	924	1			T5	2		T4	39		T11	2
valid_sources[0x04]	1109	1			T1	2		T5	2		T15	2
valid_sources[0x05]	1185	1			T1	3		T4	5		T47	4
valid_sources[0x06]	927	1			T1	1		T5	1		T11	6
valid_sources[0x07]	969	1			T5	11		T4	4		T11	9
valid_sources[0x08]	954	1			T1	2		T11	4		T68	3
valid_sources[0x09]	1119	1			T15	1		T47	1		T21	1
valid_sources[0x0a]	813	1			T1	1		T5	1		T13	3
valid_sources[0x0b]	941	1			T1	6		T5	1		T11	6
valid_sources[0x0c]	817	1			T47	2		T21	2		T67	1
valid_sources[0x0d]	1063	1			T5	2		T3	2		T15	3
valid_sources[0x0e]	842	1			T5	3		T21	1		T11	7
valid_sources[0x0f]	1243	1			T2	461		T4	3		T15	1
valid_sources[0x10]	993	1			T65	1		T11	11		T42	3
valid_sources[0x11]	816	1			T1	2		T7	2		T11	3
valid_sources[0x12]	856	1			T1	1		T5	1		T15	1
valid_sources[0x13]	1871	1			T1	4		T5	4		T4	1
valid_sources[0x14]	934	1			T5	4		T4	6		T7	35
valid_sources[0x15]	2251	1			T1	3		T5	1		T7	1
valid_sources[0x16]	745	1			T5	2		T4	1		T15	1
valid_sources[0x17]	879	1			T1	1		T5	6		T4	2
valid_sources[0x18]	1254	1			T5	1		T13	2		T7	23
valid_sources[0x19]	943	1			T1	1		T5	3		T11	8
valid_sources[0x1a]	1339	1			T1	1		T5	1		T9	16
valid_sources[0x1b]	1326	1			T1	2		T21	1		T11	5
valid_sources[0x1c]	1909	1			T1	1		T5	1		T11	7
valid_sources[0x1d]	971	1			T4	13		T15	2		T7	2
valid_sources[0x1e]	930	1			T1	2		T21	1		T11	2
valid_sources[0x1f]	954	1			T5	4		T4	34		T15	1
valid_sources[0x20]	937	1			T1	1		T5	6		T47	2
valid_sources[0x21]	904	1			T1	1		T5	1		T3	1
valid_sources[0x22]	1074	1			T5	2		T4	9		T15	4
valid_sources[0x23]	989	1			T15	1		T11	1		T42	1
valid_sources[0x24]	760	1			T7	2		T47	1		T66	2
valid_sources[0x25]	1254	1			T1	2		T5	1		T15	1
valid_sources[0x26]	973	1			T1	2		T5	2		T7	6
valid_sources[0x27]	1759	1			T1	1		T5	2		T13	1
valid_sources[0x28]	1045	1			T1	5		T5	5		T13	1
valid_sources[0x29]	949	1			T5	2		T4	1		T15	2
valid_sources[0x2a]	988	1			T1	1		T5	2		T7	48
valid_sources[0x2b]	893	1			T1	2		T5	9		T13	13
valid_sources[0x2c]	816	1			T1	1		T21	1		T11	4
valid_sources[0x2d]	1973	1			T1	1		T42	1		T12	6
valid_sources[0x2e]	1093	1			T1	3		T5	7		T15	2
valid_sources[0x2f]	1497	1			T1	1		T15	1		T47	1
valid_sources[0x30]	923	1			T1	2		T5	1		T65	3
valid_sources[0x31]	931	1			T1	7		T5	3		T15	3
valid_sources[0x32]	942	1			T15	1		T11	4		T42	2
valid_sources[0x33]	932	1			T1	1		T5	2		T4	6
valid_sources[0x34]	986	1			T1	7		T47	2		T42	3
valid_sources[0x35]	2024	1			T1	1		T5	4		T8	21
valid_sources[0x36]	1672	1			T1	2		T5	3		T47	1
valid_sources[0x37]	956	1			T1	2		T5	2		T4	52
valid_sources[0x38]	835	1			T1	2		T15	2		T7	1
valid_sources[0x39]	950	1			T1	3		T14	123		T47	1
valid_sources[0x3a]	2790	1			T5	2		T65	3		T11	11
valid_sources[0x3b]	1044	1			T1	1		T5	6		T4	1
valid_sources[0x3c]	852	1			T11	5		T95	2		T386	2
valid_sources[0x3d]	972	1			T1	3		T5	1		T47	1
valid_sources[0x3e]	2239	1			T1	2		T65	1		T11	7
valid_sources[0x3f]	914	1			T1	1		T5	3		T65	1
valid_sources[0x40]	967	1			T1	1		T5	1		T65	2
valid_sources[0x41]	1084	1			T5	10		T13	8		T4	14
valid_sources[0x42]	1838	1			T1	10		T27	427		T47	1
valid_sources[0x43]	868	1			T5	7		T22	2		T11	4
valid_sources[0x44]	865	1			T5	3		T11	3		T69	2
valid_sources[0x45]	1044	1			T15	3		T11	6		T70	4
valid_sources[0x46]	853	1			T1	2		T5	2		T11	5
valid_sources[0x47]	1569	1			T1	1		T5	1		T13	1
valid_sources[0x48]	1063	1			T5	1		T15	1		T7	5
valid_sources[0x49]	1121	1			T1	2		T11	7		T42	1
valid_sources[0x4a]	1051	1			T1	1		T5	3		T4	9
valid_sources[0x4b]	2656	1			T1	4		T5	2		T4	8
valid_sources[0x4c]	830	1			T4	7		T25	1		T11	3
valid_sources[0x4d]	835	1			T1	3		T4	12		T65	2
valid_sources[0x4e]	1007	1			T1	1		T11	4		T12	3
valid_sources[0x4f]	869	1			T1	1		T5	1		T11	3
valid_sources[0x50]	839	1			T1	1		T7	33		T11	8
valid_sources[0x51]	998	1			T1	3		T5	5		T3	1
valid_sources[0x52]	906	1			T1	4		T4	5		T11	11
valid_sources[0x53]	849	1			T1	5		T15	1		T67	1
valid_sources[0x54]	1020	1			T1	2		T11	3		T42	1
valid_sources[0x55]	871	1			T1	2		T11	4		T68	1
valid_sources[0x56]	846	1			T1	2		T5	4		T11	11
valid_sources[0x57]	947	1			T15	1		T47	3		T21	1
valid_sources[0x58]	904	1			T1	2		T13	10		T11	6
valid_sources[0x59]	1845	1			T42	3		T12	4		T41	9
valid_sources[0x5a]	993	1			T1	3		T5	2		T7	49
valid_sources[0x5b]	929	1			T1	2		T5	2		T22	2
valid_sources[0x5c]	1136	1			T1	2		T13	24		T4	5
valid_sources[0x5d]	1316	1			T5	1		T47	1		T11	3
valid_sources[0x5e]	843	1			T1	9		T5	4		T4	8
valid_sources[0x5f]	1028	1			T1	4		T15	2		T11	5
valid_sources[0x60]	1015	1			T1	6		T15	1		T11	5
valid_sources[0x61]	839	1			T1	9		T4	9		T15	1
valid_sources[0x62]	803	1			T1	1		T5	2		T15	1
valid_sources[0x63]	1084	1			T1	1		T47	1		T49	1
valid_sources[0x64]	1084	1			T1	6		T21	1		T11	1
valid_sources[0x65]	911	1			T1	4		T5	3		T4	3
valid_sources[0x66]	1717	1			T1	4		T4	34		T15	1
valid_sources[0x67]	1032	1			T5	1		T11	3		T42	2
valid_sources[0x68]	1198	1			T1	1		T5	2		T15	2
valid_sources[0x69]	1419	1			T1	1		T13	7		T4	2
valid_sources[0x6a]	821	1			T1	2		T5	2		T13	2
valid_sources[0x6b]	1514	1			T1	4		T5	5		T15	2
valid_sources[0x6c]	937	1			T1	2		T7	2		T11	7
valid_sources[0x6d]	1033	1			T7	1		T66	1		T11	3
valid_sources[0x6e]	962	1			T1	5		T5	1		T4	4
valid_sources[0x6f]	2149	1			T1	1		T65	1		T11	2
valid_sources[0x70]	907	1			T5	2		T4	3		T15	1
valid_sources[0x71]	901	1			T1	3		T5	5		T49	1
valid_sources[0x72]	986	1			T1	5		T5	2		T15	1
valid_sources[0x73]	1775	1			T1	4		T5	4		T47	1
valid_sources[0x74]	1099	1			T1	5		T5	2		T15	2
valid_sources[0x75]	726	1			T1	2		T5	2		T15	1
valid_sources[0x76]	917	1			T1	1		T4	2		T15	1
valid_sources[0x77]	1014	1			T1	7		T5	1		T13	10
valid_sources[0x78]	1254	1			T1	4		T7	101		T47	1
valid_sources[0x79]	995	1			T47	3		T11	3		T42	2
valid_sources[0x7a]	860	1			T4	5		T15	1		T11	5
valid_sources[0x7b]	936	1			T15	1		T65	2		T11	7
valid_sources[0x7c]	1144	1			T1	5		T22	2		T11	4
valid_sources[0x7d]	963	1			T5	10		T4	1		T7	11
valid_sources[0x7e]	927	1			T5	2		T3	25		T15	1
valid_sources[0x7f]	1376	1			T1	2		T5	1		T3	3
valid_sources[0x80]	1523	1			T1	2		T5	1		T4	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

64976

1

T1

194

T5

219

T6

1

values[0x0]

all_enables

biggest_size

33498

1

T1

43

T5

9

T2

15

values[0x1]

all_enables

biggest_size

23893

1

T1

34

T5

13

T2

16