Unified Coverage Report :: Group :: dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg

Group : dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_lockable_field_cov.sv

119 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_debounce_ctl.auto_block_enable	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_debounce_ctl.debounce_timer	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key0_out_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key0_out_value	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key1_out_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key1_out_value	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key2_out_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key2_out_value	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_0.detection_timer_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_1.detection_timer_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_2.detection_timer_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_3.detection_timer_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.bat_disable	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.ec_rst	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.interrupt	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.rst_req	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.bat_disable	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.ec_rst	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.interrupt	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.rst_req	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.bat_disable	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.ec_rst	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.interrupt	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.rst_req	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.bat_disable	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.ec_rst	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.interrupt	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.rst_req	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_0.precondition_timer_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_1.precondition_timer_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_2.precondition_timer_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_3.precondition_timer_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.ac_present_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key0_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key1_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key2_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.pwrb_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.ac_present_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key0_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key1_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key2_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.pwrb_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.ac_present_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key0_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key1_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key2_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.pwrb_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.ac_present_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key0_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key1_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key2_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.pwrb_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.ac_present_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key0_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key1_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key2_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.pwrb_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.ac_present_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key0_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key1_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key2_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.pwrb_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.ac_present_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key0_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key1_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key2_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.pwrb_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.ac_present_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key0_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key1_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key2_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.pwrb_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.ec_rst_ctl.ec_rst_pulse	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ac_present_h2l	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ac_present_l2h	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ec_rst_l_h2l	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ec_rst_l_l2h	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.flash_wp_l_h2l	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.flash_wp_l_l2h	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key0_in_h2l	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key0_in_l2h	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key1_in_h2l	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key1_in_l2h	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key2_in_h2l	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key2_in_l2h	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.pwrb_in_h2l	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.pwrb_in_l2h	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_debounce_ctl.debounce_timer	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.ac_present	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.bat_disable	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key0_in	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key0_out	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key1_in	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key1_out	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key2_in	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key2_out	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.lid_open	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.pwrb_in	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.pwrb_out	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.z3_wakeup	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.bat_disable_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.bat_disable_1	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.ec_rst_l_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.ec_rst_l_1	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.flash_wp_l_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.flash_wp_l_1	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key0_out_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key0_out_1	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key1_out_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key1_out_1	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key2_out_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key2_out_1	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.pwrb_out_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.pwrb_out_1	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.z3_wakeup_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.z3_wakeup_1	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_ac_debounce_ctl.ulp_ac_debounce_timer	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_lid_debounce_ctl.ulp_lid_debounce_timer	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_pwrb_debounce_ctl.ulp_pwrb_debounce_timer	100.00	1	100	1	64	64

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_debounce_ctl.auto_block_enable

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_debounce_ctl.auto_block_enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_debounce_ctl.auto_block_enable

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_debounce_ctl.debounce_timer

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_debounce_ctl.debounce_timer

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_debounce_ctl.debounce_timer

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key0_out_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key0_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key0_out_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key0_out_value

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key0_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key0_out_value

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key1_out_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key1_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key1_out_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key1_out_value

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key1_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key1_out_value

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key2_out_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key2_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key2_out_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key2_out_value

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key2_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key2_out_value

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_0.detection_timer_0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_0.detection_timer_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_0.detection_timer_0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_1.detection_timer_0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_1.detection_timer_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_1.detection_timer_0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_2.detection_timer_0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_2.detection_timer_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_2.detection_timer_0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_3.detection_timer_0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_3.detection_timer_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_3.detection_timer_0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.bat_disable

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.bat_disable

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.ec_rst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.ec_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.ec_rst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.interrupt

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.interrupt

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.rst_req

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.rst_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.rst_req

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.bat_disable

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.bat_disable

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.ec_rst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.ec_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.ec_rst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.interrupt

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.interrupt

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.rst_req

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.rst_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.rst_req

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.bat_disable

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.bat_disable

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.ec_rst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.ec_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.ec_rst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.interrupt

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.interrupt

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.rst_req

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.rst_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.rst_req

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.bat_disable

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.bat_disable

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.ec_rst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.ec_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.ec_rst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.interrupt

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.interrupt

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.rst_req

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.rst_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.rst_req

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_0.precondition_timer_0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_0.precondition_timer_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_0.precondition_timer_0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_1.precondition_timer_0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_1.precondition_timer_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_1.precondition_timer_0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_2.precondition_timer_0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_2.precondition_timer_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_2.precondition_timer_0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_3.precondition_timer_0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_3.precondition_timer_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_3.precondition_timer_0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.ac_present_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.ac_present_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key0_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key0_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key1_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key1_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key2_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key2_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.pwrb_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.pwrb_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.ac_present_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.ac_present_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key0_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key0_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key1_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key1_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key2_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key2_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.pwrb_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.pwrb_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.ac_present_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.ac_present_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key0_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key0_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key1_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key1_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key2_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key2_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.pwrb_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.pwrb_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.ac_present_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.ac_present_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key0_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key0_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key1_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key1_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key2_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key2_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.pwrb_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.pwrb_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.ac_present_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.ac_present_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key0_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key0_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key1_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key1_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key2_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key2_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.pwrb_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.pwrb_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.ac_present_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.ac_present_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key0_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key0_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key1_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key1_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key2_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key2_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.pwrb_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.pwrb_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.ac_present_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.ac_present_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key0_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key0_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key1_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key1_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key2_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key2_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.pwrb_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.pwrb_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.ac_present_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.ac_present_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key0_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key0_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key1_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key1_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key2_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key2_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.pwrb_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.pwrb_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.ec_rst_ctl.ec_rst_pulse

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.ec_rst_ctl.ec_rst_pulse

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.ec_rst_ctl.ec_rst_pulse

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ac_present_h2l

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ac_present_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ac_present_h2l

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ac_present_l2h

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ac_present_l2h

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ac_present_l2h

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ec_rst_l_h2l

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ec_rst_l_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ec_rst_l_h2l

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ec_rst_l_l2h

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ec_rst_l_l2h

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ec_rst_l_l2h

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.flash_wp_l_h2l

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.flash_wp_l_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.flash_wp_l_h2l

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

198

1

T293

4

T334

1

T294

1

auto[1]

589

1

T4

3

T25

2

T43

1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

338

1

T30

1

T293

5

T334

1

auto[1]

832

1

T4

3

T25

3

T26

3

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

392

1

T30

2

T293

4

T294

2

auto[1]

397

1

T4

1

T25

2

T26

3

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

344

1

T30

1

T293

4

T294

1

auto[1]

460

1

T4

1

T25

3

T26

1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

361

1

T30

2

T293

2

T304

2

auto[1]

379

1

T4

3

T25

3

T26

2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

374

1

T30

2

T293

4

T304

3

auto[1]

471

1

T4

3

T25

1

T43

3

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

356

1

T29

1

T30

1

T293

2

auto[1]

378

1

T4

2

T25

3

T26

3

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

372

1

T30

3

T293

2

T294

1

auto[1]

398

1

T4

1

T26

2

T44

3

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

317

1

T29

1

T30

3

T293

7

auto[1]

3300

1

T1

20

T5

20

T2

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

392

1

T29

1

T30

3

T293

6

auto[1]

3188

1

T1

20

T5

20

T2

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

304

1

T30

4

T293

2

T294

3

auto[1]

3350

1

T1

20

T5

20

T2

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

439

1

T30

5

T293

5

T320

1

auto[1]

3218

1

T1

20

T5

20

T2

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

228

1

T30

2

T293

3

T294

1

auto[1]

1646

1

T4

12

T7

13

T11

27

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

225

1

T30

3

T293

1

T334

1

auto[1]

1618

1

T1

20

T5

20

T10

40

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

241

1

T30

3

T293

4

T334

1

auto[1]

1753

1

T1

20

T5

20

T4

12

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

225

1

T293

1

T294

2

T304

6

auto[1]

1621

1

T1

20

T5

20

T7

13

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

302

1

T30

1

T293

2

T334

1

auto[1]

1672

1

T5

20

T2

20

T4

12

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

288

1

T29

1

T30

2

T293

1

auto[1]

1564

1

T1

20

T4

12

T7

13

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

234

1

T29

1

T30

1

T293

2

auto[1]

1566

1

T1

20

T2

20

T4

12

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

264

1

T30

3

T293

3

T304

1

auto[1]

1850

1

T2

20

T10

40

T11

27

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

256

1

T29

1

T30

4

T293

3

auto[1]

1795

1

T2

20

T10

20

T12

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

252

1

T30

2

T293

2

T294

3

auto[1]

1760

1

T5

20

T4

12

T10

40

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

238

1

T29

1

T30

3

T293

2

auto[1]

1758

1

T5

20

T4

12

T10

40

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

251

1

T30

3

T293

3

T294

2

auto[1]

1672

1

T1

20

T5

20

T10

40

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

318

1

T29

1

T30

3

T293

2

auto[1]

1891

1

T5

20

T7

13

T10

40

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

271

1

T30

1

T293

3

T320

1

auto[1]

1537

1

T5

20

T10

20

T12

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

313

1

T29

1

T30

2

T293

2

auto[1]

1627

1

T1

20

T4

12

T10

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

319

1

T29

1

T30

2

T293

4

auto[1]

1661

1

T2

20

T4

12

T10

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

367

1

T29

1

T30

7

T293

3

auto[1]

495

1

T28

1

T51

12

T30

11

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

374

1

T30

3

T293

6

T334

1

auto[1]

477

1

T28

1

T51

16

T30

15

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

363

1

T29

1

T30

3

T293

5

auto[1]

488

1

T28

1

T51

7

T30

14

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

379

1

T29

1

T30

4

T293

6

auto[1]

481

1

T28

1

T51

40

T30

14

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

205

1

T29

1

T30

2

T293

2

auto[1]

730

1

T7

13

T11

27

T39

23

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

237

1

T29

1

T30

2

T293

3

auto[1]

778

1

T41

10

T40

13

T74

11

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

219

1

T293

2

T304

1

T325

1

auto[1]

836

1

T42

10

T41

10

T283

18

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

259

1

T30

3

T293

2

T304

3

auto[1]

830

1

T11

27

T40

13

T74

11

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

222

1

T30

2

T293

2

T304

2

auto[1]

886

1

T7

13

T40

13

T74

11

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

313

1

T30

2

T293

3

T294

2

auto[1]

837

1

T11

27

T42

10

T74

11

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

311

1

T29

1

T30

1

T293

1

auto[1]

709

1

T41

10

T39

23

T40

13

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

338

1

T29

1

T30

1

T293

2

auto[1]

725

1

T7

13

T127

18

T263

11

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

334

1

T29

1

T293

3

T294

2

auto[1]

545

1

T7

13

T42

10

T117

16

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

290

1

T29

1

T30

1

T293

2

auto[1]

756

1

T7

13

T11

27

T39

23

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

246

1

T29

1

T30

4

T293

3

auto[1]

651

1

T40

13

T261

12

T267

11

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

276

1

T30

3

T293

3

T294

2

auto[1]

742

1

T7

13

T42

10

T117

16

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

294

1

T29

1

T30

5

T293

3

auto[1]

693

1

T7

13

T11

27

T74

11

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

228

1

T29

1

T30

6

T293

1

auto[1]

873

1

T11

27

T42

10

T41

10

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

304

1

T29

1

T30

5

T293

2

auto[1]

857

1

T11

27

T39

23

T74

11

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

245

1

T293

3

T304

2

T325

1

auto[1]

865

1

T11

27

T39

23

T117

16

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

269

1

T30

1

T293

3

T304

3

auto[1]

799

1

T7

13

T11

27

T42

10

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

221

1

T29

1

T293

2

T294

2

auto[1]

735

1

T7

13

T42

10

T98

11

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

219

1

T30

1

T293

2

T294

1

auto[1]

660

1

T41

10

T40

13

T349

15

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

214

1

T29

1

T293

3

T294

1

auto[1]

818

1

T7

13

T11

27

T40

13

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

169

1

T30

3

T293

1

T294

1

auto[1]

1598

1

T1

20

T4

12

T42

10

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

209

1

T30

4

T293

2

T334

1

auto[1]

1531

1

T1

20

T2

20

T4

12

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

158

1

T30

1

T293

3

T294

2

auto[1]

1694

1

T1

20

T5

20

T2

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

227

1

T30

4

T293

1

T334

1

auto[1]

1505

1

T5

20

T42

10

T12

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

201

1

T30

5

T293

1

T334

1

auto[1]

1451

1

T5

20

T10

20

T11

27

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

318

1

T30

2

T293

3

T294

1

auto[1]

1605

1

T1

20

T5

20

T2

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

314

1

T30

3

T293

3

T304

4

auto[1]

1590

1

T1

20

T2

20

T7

13

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

320

1

T293

3

T294

1

T304

3

auto[1]

1580

1

T1

20

T5

20

T2

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

311

1

T293

2

T294

1

T304

5

auto[1]

1452

1

T4

12

T10

40

T11

27

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

318

1

T30

2

T293

1

T294

2

auto[1]

1425

1

T5

20

T4

12

T10

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

277

1

T29

1

T30

3

T293

2

auto[1]

1526

1

T5

20

T2

20

T4

12

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

295

1

T30

2

T293

2

T320

1

auto[1]

1602

1

T1

20

T5

20

T2

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

340

1

T29

1

T30

3

T293

3

auto[1]

1438

1

T5

20

T52

20

T95

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

286

1

T29

1

T30

1

T293

4

auto[1]

1568

1

T5

20

T2

20

T4

12

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

337

1

T30

3

T293

4

T294

3

auto[1]

1524

1

T1

20

T2

20

T42

10

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

211

1

T30

1

T293

1

T294

2

auto[1]

1603

1

T1

20

T2

20

T4

12

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

302

1

T30

1

T293

1

T294

3

auto[1]

1535

1

T1

20

T2

20

T10

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

250

1

T30

2

T293

3

T294

2

auto[1]

1589

1

T1

20

T2

20

T4

12

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

270

1

T30

3

T293

1

T334

1

auto[1]

1533

1

T1

20

T2

20

T4

12

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

261

1

T30

1

T293

2

T334

1

auto[1]

1567

1

T1

20

T4

12

T10

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

338

1

T29

1

T30

3

T293

8

auto[1]

648

1

T4

1

T48

1

T49

1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

245

1

T30

3

T293

3

T294

4

auto[1]

377

1

T24

1

T36

1

T32

2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

200

1

T30

1

T293

2

T334

1

auto[1]

370

1

T9

1

T36

1

T38

1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

237

1

T30

3

T293

4

T334

1

auto[1]

445

1

T8

1

T9

1

T24

1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

192

1

T30

1

T293

4

T334

1

auto[1]

330

1

T8

1

T9

1

T37

1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

233

1

T30

4

T293

5

T294

1

auto[1]

346

1

T8

1

T9

1

T24

1